1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5 #ifndef __QCOM_SCM_H
6 #define __QCOM_SCM_H
7
8 #include <linux/err.h>
9 #include <linux/types.h>
10 #include <linux/cpumask.h>
11
12 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
15 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
16
17 struct qcom_scm_hdcp_req {
18 u32 addr;
19 u32 val;
20 };
21
22 struct qcom_scm_vmperm {
23 int vmid;
24 int perm;
25 };
26
27 #define QCOM_SCM_VMID_HLOS 0x3
28 #define QCOM_SCM_VMID_MSS_MSA 0xF
29 #define QCOM_SCM_VMID_WLAN 0x18
30 #define QCOM_SCM_VMID_WLAN_CE 0x19
31 #define QCOM_SCM_PERM_READ 0x4
32 #define QCOM_SCM_PERM_WRITE 0x2
33 #define QCOM_SCM_PERM_EXEC 0x1
34 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
35 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
36
37 #if IS_ENABLED(CONFIG_QCOM_SCM)
38 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
39 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
40 extern bool qcom_scm_is_available(void);
41 extern bool qcom_scm_hdcp_available(void);
42 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
43 u32 *resp);
44 extern bool qcom_scm_pas_supported(u32 peripheral);
45 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
46 size_t size);
47 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
48 phys_addr_t size);
49 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
50 extern int qcom_scm_pas_shutdown(u32 peripheral);
51 extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
52 unsigned int *src,
53 const struct qcom_scm_vmperm *newvm,
54 unsigned int dest_cnt);
55 extern void qcom_scm_cpu_power_down(u32 flags);
56 extern u32 qcom_scm_get_version(void);
57 extern int qcom_scm_set_remote_state(u32 state, u32 id);
58 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
59 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
60 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
61 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
62 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
63 #else
64
65 #include <linux/errno.h>
66
67 static inline
qcom_scm_set_cold_boot_addr(void * entry,const cpumask_t * cpus)68 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
69 {
70 return -ENODEV;
71 }
72 static inline
qcom_scm_set_warm_boot_addr(void * entry,const cpumask_t * cpus)73 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
74 {
75 return -ENODEV;
76 }
qcom_scm_is_available(void)77 static inline bool qcom_scm_is_available(void) { return false; }
qcom_scm_hdcp_available(void)78 static inline bool qcom_scm_hdcp_available(void) { return false; }
qcom_scm_hdcp_req(struct qcom_scm_hdcp_req * req,u32 req_cnt,u32 * resp)79 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
80 u32 *resp) { return -ENODEV; }
qcom_scm_pas_supported(u32 peripheral)81 static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
qcom_scm_pas_init_image(u32 peripheral,const void * metadata,size_t size)82 static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
83 size_t size) { return -ENODEV; }
qcom_scm_pas_mem_setup(u32 peripheral,phys_addr_t addr,phys_addr_t size)84 static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
85 phys_addr_t size) { return -ENODEV; }
86 static inline int
qcom_scm_pas_auth_and_reset(u32 peripheral)87 qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
qcom_scm_pas_shutdown(u32 peripheral)88 static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
qcom_scm_assign_mem(phys_addr_t mem_addr,size_t mem_sz,unsigned int * src,const struct qcom_scm_vmperm * newvm,unsigned int dest_cnt)89 static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
90 unsigned int *src,
91 const struct qcom_scm_vmperm *newvm,
92 unsigned int dest_cnt) { return -ENODEV; }
qcom_scm_cpu_power_down(u32 flags)93 static inline void qcom_scm_cpu_power_down(u32 flags) {}
qcom_scm_get_version(void)94 static inline u32 qcom_scm_get_version(void) { return 0; }
95 static inline u32
qcom_scm_set_remote_state(u32 state,u32 id)96 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
qcom_scm_restore_sec_cfg(u32 device_id,u32 spare)97 static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
qcom_scm_iommu_secure_ptbl_size(u32 spare,size_t * size)98 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
qcom_scm_iommu_secure_ptbl_init(u64 addr,u32 size,u32 spare)99 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
qcom_scm_io_readl(phys_addr_t addr,unsigned int * val)100 static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
qcom_scm_io_writel(phys_addr_t addr,unsigned int val)101 static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
102 #endif
103 #endif
104
