1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Flora Fu, MediaTek 5 */ 6 7 #ifndef __MFD_MT6397_CORE_H__ 8 #define __MFD_MT6397_CORE_H__ 9 10 #include <linux/mutex.h> 11 #include <linux/notifier.h> 12 13 enum chip_id { 14 MT6323_CHIP_ID = 0x23, 15 MT6358_CHIP_ID = 0x58, 16 MT6391_CHIP_ID = 0x91, 17 MT6397_CHIP_ID = 0x97, 18 }; 19 20 enum mt6397_irq_numbers { 21 MT6397_IRQ_SPKL_AB = 0, 22 MT6397_IRQ_SPKR_AB, 23 MT6397_IRQ_SPKL, 24 MT6397_IRQ_SPKR, 25 MT6397_IRQ_BAT_L, 26 MT6397_IRQ_BAT_H, 27 MT6397_IRQ_FG_BAT_L, 28 MT6397_IRQ_FG_BAT_H, 29 MT6397_IRQ_WATCHDOG, 30 MT6397_IRQ_PWRKEY, 31 MT6397_IRQ_THR_L, 32 MT6397_IRQ_THR_H, 33 MT6397_IRQ_VBATON_UNDET, 34 MT6397_IRQ_BVALID_DET, 35 MT6397_IRQ_CHRDET, 36 MT6397_IRQ_OV, 37 MT6397_IRQ_LDO, 38 MT6397_IRQ_HOMEKEY, 39 MT6397_IRQ_ACCDET, 40 MT6397_IRQ_AUDIO, 41 MT6397_IRQ_RTC, 42 MT6397_IRQ_PWRKEY_RSTB, 43 MT6397_IRQ_HDMI_SIFM, 44 MT6397_IRQ_HDMI_CEC, 45 MT6397_IRQ_VCA15, 46 MT6397_IRQ_VSRMCA15, 47 MT6397_IRQ_VCORE, 48 MT6397_IRQ_VGPU, 49 MT6397_IRQ_VIO18, 50 MT6397_IRQ_VPCA7, 51 MT6397_IRQ_VSRMCA7, 52 MT6397_IRQ_VDRM, 53 MT6397_IRQ_NR, 54 }; 55 56 struct mt6397_chip { 57 struct device *dev; 58 struct regmap *regmap; 59 struct notifier_block pm_nb; 60 int irq; 61 struct irq_domain *irq_domain; 62 struct mutex irqlock; 63 u16 wake_mask[2]; 64 u16 irq_masks_cur[2]; 65 u16 irq_masks_cache[2]; 66 u16 int_con[2]; 67 u16 int_status[2]; 68 u16 chip_id; 69 void *irq_data; 70 }; 71 72 int mt6358_irq_init(struct mt6397_chip *chip); 73 int mt6397_irq_init(struct mt6397_chip *chip); 74 75 #endif /* __MFD_MT6397_CORE_H__ */ 76
