1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (C) 2020 Marvell.
3  */
4 
5 #ifndef __SOC_OTX2_ASM_H
6 #define __SOC_OTX2_ASM_H
7 
8 #if defined(CONFIG_ARM64)
9 /*
10  * otx2_lmt_flush is used for LMT store operation.
11  * On octeontx2 platform CPT instruction enqueue and
12  * NIX packet send are only possible via LMTST
13  * operations and it uses LDEOR instruction targeting
14  * the coprocessor address.
15  */
16 #define otx2_lmt_flush(ioaddr)                          \
17 ({                                                      \
18 	u64 result = 0;                                 \
19 	__asm__ volatile(".cpu  generic+lse\n"          \
20 			 "ldeor xzr, %x[rf], [%[rs]]"   \
21 			 : [rf]"=r" (result)            \
22 			 : [rs]"r" (ioaddr));           \
23 	(result);                                       \
24 })
25 /*
26  * STEORL store to memory with release semantics.
27  * This will avoid using DMB barrier after each LMTST
28  * operation.
29  */
30 #define cn10k_lmt_flush(val, addr)			\
31 ({							\
32 	__asm__ volatile(".cpu  generic+lse\n"		\
33 			 "steorl %x[rf],[%[rs]]"		\
34 			 : [rf] "+r"(val)		\
35 			 : [rs] "r"(addr));		\
36 })
37 #else
38 #define otx2_lmt_flush(ioaddr)          ({ 0; })
39 #define cn10k_lmt_flush(val, addr)	({ addr = val; })
40 #endif
41 
42 #endif /* __SOC_OTX2_ASM_H */
43