1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 4 */ 5 6 #ifndef K3_UDMA_H_ 7 #define K3_UDMA_H_ 8 9 #include <linux/soc/ti/ti_sci_protocol.h> 10 11 /* Global registers */ 12 #define UDMA_REV_REG 0x0 13 #define UDMA_PERF_CTL_REG 0x4 14 #define UDMA_EMU_CTL_REG 0x8 15 #define UDMA_PSIL_TO_REG 0x10 16 #define UDMA_UTC_CTL_REG 0x1c 17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4)) 18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 20 21 /* TCHANRT/RCHANRT registers */ 22 #define UDMA_CHAN_RT_CTL_REG 0x0 23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8 24 #define UDMA_CHAN_RT_STDATA_REG 0x80 25 26 #define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4)) 27 #define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \ 28 UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */ 29 #define UDMA_CHAN_RT_PEER_STATIC_TR_Z_REG \ 30 UDMA_CHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */ 31 #define UDMA_CHAN_RT_PEER_BCNT_REG \ 32 UDMA_CHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */ 33 #define UDMA_CHAN_RT_PEER_RT_EN_REG \ 34 UDMA_CHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */ 35 36 #define UDMA_CHAN_RT_PCNT_REG 0x400 37 #define UDMA_CHAN_RT_BCNT_REG 0x408 38 #define UDMA_CHAN_RT_SBCNT_REG 0x410 39 40 /* UDMA_CAP Registers */ 41 #define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff) 42 #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) 43 #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) 44 #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) 45 #define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff) 46 #define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff) 47 48 /* UDMA_CHAN_RT_CTL_REG */ 49 #define UDMA_CHAN_RT_CTL_EN BIT(31) 50 #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) 51 #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) 52 #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) 53 #define UDMA_CHAN_RT_CTL_ERROR BIT(0) 54 55 /* UDMA_CHAN_RT_PEER_RT_EN_REG */ 56 #define UDMA_PEER_RT_EN_ENABLE BIT(31) 57 #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) 58 #define UDMA_PEER_RT_EN_PAUSE BIT(29) 59 #define UDMA_PEER_RT_EN_FLUSH BIT(28) 60 #define UDMA_PEER_RT_EN_IDLE BIT(1) 61 62 /* 63 * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG / 64 * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG 65 */ 66 #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24) 67 #define PDMA_STATIC_TR_X_SHIFT (24) 68 #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0) 69 #define PDMA_STATIC_TR_Y_SHIFT (0) 70 71 #define PDMA_STATIC_TR_Y(x) \ 72 (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK) 73 #define PDMA_STATIC_TR_X(x) \ 74 (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK) 75 76 #define PDMA_STATIC_TR_XY_ACC32 BIT(30) 77 #define PDMA_STATIC_TR_XY_BURST BIT(31) 78 79 /* 80 * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG / 81 * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG 82 */ 83 #define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask)) 84 85 struct udma_dev; 86 struct udma_tchan; 87 struct udma_rchan; 88 struct udma_rflow; 89 90 enum udma_rm_range { 91 RM_RANGE_TCHAN = 0, 92 RM_RANGE_RCHAN, 93 RM_RANGE_RFLOW, 94 RM_RANGE_LAST, 95 }; 96 97 struct udma_tisci_rm { 98 const struct ti_sci_handle *tisci; 99 const struct ti_sci_rm_udmap_ops *tisci_udmap_ops; 100 u32 tisci_dev_id; 101 102 /* tisci information for PSI-L thread pairing/unpairing */ 103 const struct ti_sci_rm_psil_ops *tisci_psil_ops; 104 u32 tisci_navss_dev_id; 105 106 struct ti_sci_resource *rm_ranges[RM_RANGE_LAST]; 107 }; 108 109 /* Direct access to UDMA low lever resources for the glue layer */ 110 int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread); 111 int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, 112 u32 dst_thread); 113 114 struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property); 115 void xudma_dev_put(struct udma_dev *ud); 116 u32 xudma_dev_get_psil_base(struct udma_dev *ud); 117 struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud); 118 119 int xudma_alloc_gp_rflow_range(struct udma_dev *ud, int from, int cnt); 120 int xudma_free_gp_rflow_range(struct udma_dev *ud, int from, int cnt); 121 122 struct udma_tchan *xudma_tchan_get(struct udma_dev *ud, int id); 123 struct udma_rchan *xudma_rchan_get(struct udma_dev *ud, int id); 124 struct udma_rflow *xudma_rflow_get(struct udma_dev *ud, int id); 125 126 void xudma_tchan_put(struct udma_dev *ud, struct udma_tchan *p); 127 void xudma_rchan_put(struct udma_dev *ud, struct udma_rchan *p); 128 void xudma_rflow_put(struct udma_dev *ud, struct udma_rflow *p); 129 130 int xudma_tchan_get_id(struct udma_tchan *p); 131 int xudma_rchan_get_id(struct udma_rchan *p); 132 int xudma_rflow_get_id(struct udma_rflow *p); 133 134 u32 xudma_tchanrt_read(struct udma_tchan *tchan, int reg); 135 void xudma_tchanrt_write(struct udma_tchan *tchan, int reg, u32 val); 136 u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg); 137 void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); 138 bool xudma_rflow_is_gp(struct udma_dev *ud, int id); 139 140 #endif /* K3_UDMA_H_ */ 141
