1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_PM_H__ 7 #define __INTEL_PM_H__ 8 9 #include <linux/types.h> 10 11 #include "display/intel_bw.h" 12 #include "display/intel_display.h" 13 #include "display/intel_global_state.h" 14 15 #include "i915_drv.h" 16 #include "i915_reg.h" 17 18 struct drm_device; 19 struct drm_i915_private; 20 struct i915_request; 21 struct intel_atomic_state; 22 struct intel_crtc; 23 struct intel_crtc_state; 24 struct intel_plane; 25 struct skl_ddb_entry; 26 struct skl_pipe_wm; 27 struct skl_wm_level; 28 29 void intel_init_clock_gating(struct drm_i915_private *dev_priv); 30 void intel_suspend_hw(struct drm_i915_private *dev_priv); 31 int ilk_wm_max_level(const struct drm_i915_private *dev_priv); 32 void intel_update_watermarks(struct intel_crtc *crtc); 33 void intel_init_pm(struct drm_i915_private *dev_priv); 34 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); 35 void intel_pm_setup(struct drm_i915_private *dev_priv); 36 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv); 37 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); 38 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); 39 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); 40 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv); 41 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, 42 struct skl_ddb_entry *ddb_y, 43 struct skl_ddb_entry *ddb_uv); 44 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv); 45 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, 46 const struct skl_ddb_entry *entry); 47 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 48 struct skl_pipe_wm *out); 49 void g4x_wm_sanitize(struct drm_i915_private *dev_priv); 50 void vlv_wm_sanitize(struct drm_i915_private *dev_priv); 51 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, 52 const struct intel_bw_state *bw_state); 53 void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 54 void intel_sagv_post_plane_update(struct intel_atomic_state *state); 55 const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 56 enum plane_id plane_id, 57 int level); 58 const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 59 enum plane_id plane_id); 60 bool skl_wm_level_equals(const struct skl_wm_level *l1, 61 const struct skl_wm_level *l2); 62 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 63 const struct skl_ddb_entry *entries, 64 int num_entries, int ignore_idx); 65 void skl_write_plane_wm(struct intel_plane *plane, 66 const struct intel_crtc_state *crtc_state); 67 void skl_write_cursor_wm(struct intel_plane *plane, 68 const struct intel_crtc_state *crtc_state); 69 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv); 70 void intel_init_ipc(struct drm_i915_private *dev_priv); 71 void intel_enable_ipc(struct drm_i915_private *dev_priv); 72 73 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); 74 75 struct intel_dbuf_state { 76 struct intel_global_state base; 77 78 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 79 unsigned int weight[I915_MAX_PIPES]; 80 u8 slices[I915_MAX_PIPES]; 81 u8 enabled_slices; 82 u8 active_pipes; 83 bool joined_mbus; 84 }; 85 86 struct intel_dbuf_state * 87 intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 88 89 #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) 90 #define intel_atomic_get_old_dbuf_state(state) \ 91 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj)) 92 #define intel_atomic_get_new_dbuf_state(state) \ 93 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj)) 94 95 int intel_dbuf_init(struct drm_i915_private *dev_priv); 96 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 97 void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 98 99 #endif /* __INTEL_PM_H__ */ 100
