1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DPIO_PHY_H__
7 #define __INTEL_DPIO_PHY_H__
8 
9 #include <linux/types.h>
10 
11 enum dpio_channel;
12 enum dpio_phy;
13 enum port;
14 struct drm_i915_private;
15 struct intel_crtc_state;
16 struct intel_encoder;
17 
18 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
19 			     enum dpio_phy *phy, enum dpio_channel *ch);
20 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
21 				  enum port port, u32 margin, u32 scale,
22 				  u32 enable, u32 deemphasis);
23 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
24 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
25 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
26 			    enum dpio_phy phy);
27 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
28 			      enum dpio_phy phy);
29 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
30 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
31 				     u8 lane_lat_optim_mask);
32 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
33 
34 void chv_set_phy_signal_level(struct intel_encoder *encoder,
35 			      u32 deemph_reg_value, u32 margin_reg_value,
36 			      bool uniq_trans_scale);
37 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
38 			      const struct intel_crtc_state *crtc_state,
39 			      bool reset);
40 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
41 			    const struct intel_crtc_state *crtc_state);
42 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
43 				const struct intel_crtc_state *crtc_state);
44 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
45 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
46 			      const struct intel_crtc_state *old_crtc_state);
47 
48 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
49 			      u32 demph_reg_value, u32 preemph_reg_value,
50 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
51 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
52 			    const struct intel_crtc_state *crtc_state);
53 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
54 				const struct intel_crtc_state *crtc_state);
55 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
56 			 const struct intel_crtc_state *old_crtc_state);
57 
58 #endif /* __INTEL_DPIO_PHY_H__ */
59