1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 /* Here's the desired hotplug mode */
40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
45 ADPA_CRT_HOTPLUG_ENABLE)
46
47 struct intel_crt {
48 struct intel_encoder base;
49 /* DPMS state is stored in the connector, which we need in the
50 * encoder's enable/disable callbacks */
51 struct intel_connector *connector;
52 bool force_hotplug_required;
53 i915_reg_t adpa_reg;
54 };
55
intel_encoder_to_crt(struct intel_encoder * encoder)56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
57 {
58 return container_of(encoder, struct intel_crt, base);
59 }
60
intel_attached_crt(struct drm_connector * connector)61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
62 {
63 return intel_encoder_to_crt(intel_attached_encoder(connector));
64 }
65
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)66 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
67 i915_reg_t adpa_reg, enum pipe *pipe)
68 {
69 u32 val;
70
71 val = I915_READ(adpa_reg);
72
73 /* asserts want to know the pipe even if the port is disabled */
74 if (HAS_PCH_CPT(dev_priv))
75 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
76 else
77 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
78
79 return val & ADPA_DAC_ENABLE;
80 }
81
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)82 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
83 enum pipe *pipe)
84 {
85 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
86 struct intel_crt *crt = intel_encoder_to_crt(encoder);
87 bool ret;
88
89 if (!intel_display_power_get_if_enabled(dev_priv,
90 encoder->power_domain))
91 return false;
92
93 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
94
95 intel_display_power_put(dev_priv, encoder->power_domain);
96
97 return ret;
98 }
99
intel_crt_get_flags(struct intel_encoder * encoder)100 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
101 {
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
103 struct intel_crt *crt = intel_encoder_to_crt(encoder);
104 u32 tmp, flags = 0;
105
106 tmp = I915_READ(crt->adpa_reg);
107
108 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
109 flags |= DRM_MODE_FLAG_PHSYNC;
110 else
111 flags |= DRM_MODE_FLAG_NHSYNC;
112
113 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
114 flags |= DRM_MODE_FLAG_PVSYNC;
115 else
116 flags |= DRM_MODE_FLAG_NVSYNC;
117
118 return flags;
119 }
120
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)121 static void intel_crt_get_config(struct intel_encoder *encoder,
122 struct intel_crtc_state *pipe_config)
123 {
124 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
125
126 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
127
128 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
129 }
130
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)131 static void hsw_crt_get_config(struct intel_encoder *encoder,
132 struct intel_crtc_state *pipe_config)
133 {
134 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
135
136 intel_ddi_get_config(encoder, pipe_config);
137
138 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
139 DRM_MODE_FLAG_NHSYNC |
140 DRM_MODE_FLAG_PVSYNC |
141 DRM_MODE_FLAG_NVSYNC);
142 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
143
144 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
145 }
146
147 /* Note: The caller is required to filter out dpms modes not supported by the
148 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)149 static void intel_crt_set_dpms(struct intel_encoder *encoder,
150 const struct intel_crtc_state *crtc_state,
151 int mode)
152 {
153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
154 struct intel_crt *crt = intel_encoder_to_crt(encoder);
155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
156 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
157 u32 adpa;
158
159 if (INTEL_GEN(dev_priv) >= 5)
160 adpa = ADPA_HOTPLUG_BITS;
161 else
162 adpa = 0;
163
164 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
165 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
166 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
167 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
168
169 /* For CPT allow 3 pipe config, for others just use A or B */
170 if (HAS_PCH_LPT(dev_priv))
171 ; /* Those bits don't exist here */
172 else if (HAS_PCH_CPT(dev_priv))
173 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
174 else
175 adpa |= ADPA_PIPE_SEL(crtc->pipe);
176
177 if (!HAS_PCH_SPLIT(dev_priv))
178 I915_WRITE(BCLRPAT(crtc->pipe), 0);
179
180 switch (mode) {
181 case DRM_MODE_DPMS_ON:
182 adpa |= ADPA_DAC_ENABLE;
183 break;
184 case DRM_MODE_DPMS_STANDBY:
185 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
186 break;
187 case DRM_MODE_DPMS_SUSPEND:
188 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
189 break;
190 case DRM_MODE_DPMS_OFF:
191 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
192 break;
193 }
194
195 I915_WRITE(crt->adpa_reg, adpa);
196 }
197
intel_disable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)198 static void intel_disable_crt(struct intel_encoder *encoder,
199 const struct intel_crtc_state *old_crtc_state,
200 const struct drm_connector_state *old_conn_state)
201 {
202 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
203 }
204
pch_disable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)205 static void pch_disable_crt(struct intel_encoder *encoder,
206 const struct intel_crtc_state *old_crtc_state,
207 const struct drm_connector_state *old_conn_state)
208 {
209 }
210
pch_post_disable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)211 static void pch_post_disable_crt(struct intel_encoder *encoder,
212 const struct intel_crtc_state *old_crtc_state,
213 const struct drm_connector_state *old_conn_state)
214 {
215 intel_disable_crt(encoder, old_crtc_state, old_conn_state);
216 }
217
hsw_disable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)218 static void hsw_disable_crt(struct intel_encoder *encoder,
219 const struct intel_crtc_state *old_crtc_state,
220 const struct drm_connector_state *old_conn_state)
221 {
222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
223
224 WARN_ON(!old_crtc_state->has_pch_encoder);
225
226 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
227 }
228
hsw_post_disable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
230 const struct intel_crtc_state *old_crtc_state,
231 const struct drm_connector_state *old_conn_state)
232 {
233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
234
235 intel_ddi_disable_pipe_clock(old_crtc_state);
236
237 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
238
239 lpt_disable_pch_transcoder(dev_priv);
240 lpt_disable_iclkip(dev_priv);
241
242 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
243
244 WARN_ON(!old_crtc_state->has_pch_encoder);
245
246 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
247 }
248
hsw_pre_pll_enable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)249 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
250 const struct intel_crtc_state *crtc_state,
251 const struct drm_connector_state *conn_state)
252 {
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254
255 WARN_ON(!crtc_state->has_pch_encoder);
256
257 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
258 }
259
hsw_pre_enable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)260 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
261 const struct intel_crtc_state *crtc_state,
262 const struct drm_connector_state *conn_state)
263 {
264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
266 enum pipe pipe = crtc->pipe;
267
268 WARN_ON(!crtc_state->has_pch_encoder);
269
270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
271
272 dev_priv->display.fdi_link_train(crtc, crtc_state);
273
274 intel_ddi_enable_pipe_clock(crtc_state);
275 }
276
hsw_enable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)277 static void hsw_enable_crt(struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
279 const struct drm_connector_state *conn_state)
280 {
281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
283 enum pipe pipe = crtc->pipe;
284
285 WARN_ON(!crtc_state->has_pch_encoder);
286
287 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
288
289 intel_wait_for_vblank(dev_priv, pipe);
290 intel_wait_for_vblank(dev_priv, pipe);
291 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
292 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
293 }
294
intel_enable_crt(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)295 static void intel_enable_crt(struct intel_encoder *encoder,
296 const struct intel_crtc_state *crtc_state,
297 const struct drm_connector_state *conn_state)
298 {
299 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
300 }
301
302 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)303 intel_crt_mode_valid(struct drm_connector *connector,
304 struct drm_display_mode *mode)
305 {
306 struct drm_device *dev = connector->dev;
307 struct drm_i915_private *dev_priv = to_i915(dev);
308 int max_dotclk = dev_priv->max_dotclk_freq;
309 int max_clock;
310
311 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
312 return MODE_NO_DBLESCAN;
313
314 if (mode->clock < 25000)
315 return MODE_CLOCK_LOW;
316
317 if (HAS_PCH_LPT(dev_priv))
318 max_clock = 180000;
319 else if (IS_VALLEYVIEW(dev_priv))
320 /*
321 * 270 MHz due to current DPLL limits,
322 * DAC limit supposedly 355 MHz.
323 */
324 max_clock = 270000;
325 else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
326 max_clock = 400000;
327 else
328 max_clock = 350000;
329 if (mode->clock > max_clock)
330 return MODE_CLOCK_HIGH;
331
332 if (mode->clock > max_dotclk)
333 return MODE_CLOCK_HIGH;
334
335 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
336 if (HAS_PCH_LPT(dev_priv) &&
337 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
338 return MODE_CLOCK_HIGH;
339
340 /* HSW/BDW FDI limited to 4k */
341 if (mode->hdisplay > 4096)
342 return MODE_H_ILLEGAL;
343
344 return MODE_OK;
345 }
346
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)347 static bool intel_crt_compute_config(struct intel_encoder *encoder,
348 struct intel_crtc_state *pipe_config,
349 struct drm_connector_state *conn_state)
350 {
351 struct drm_display_mode *adjusted_mode =
352 &pipe_config->base.adjusted_mode;
353
354 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
355 return false;
356
357 return true;
358 }
359
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)360 static bool pch_crt_compute_config(struct intel_encoder *encoder,
361 struct intel_crtc_state *pipe_config,
362 struct drm_connector_state *conn_state)
363 {
364 struct drm_display_mode *adjusted_mode =
365 &pipe_config->base.adjusted_mode;
366
367 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
368 return false;
369
370 pipe_config->has_pch_encoder = true;
371
372 return true;
373 }
374
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)375 static bool hsw_crt_compute_config(struct intel_encoder *encoder,
376 struct intel_crtc_state *pipe_config,
377 struct drm_connector_state *conn_state)
378 {
379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
380 struct drm_display_mode *adjusted_mode =
381 &pipe_config->base.adjusted_mode;
382
383 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
384 return false;
385
386 /* HSW/BDW FDI limited to 4k */
387 if (adjusted_mode->crtc_hdisplay > 4096 ||
388 adjusted_mode->crtc_hblank_start > 4096)
389 return false;
390
391 pipe_config->has_pch_encoder = true;
392
393 /* LPT FDI RX only supports 8bpc. */
394 if (HAS_PCH_LPT(dev_priv)) {
395 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
396 DRM_DEBUG_KMS("LPT only supports 24bpp\n");
397 return false;
398 }
399
400 pipe_config->pipe_bpp = 24;
401 }
402
403 /* FDI must always be 2.7 GHz */
404 pipe_config->port_clock = 135000 * 2;
405
406 return true;
407 }
408
intel_ironlake_crt_detect_hotplug(struct drm_connector * connector)409 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
410 {
411 struct drm_device *dev = connector->dev;
412 struct intel_crt *crt = intel_attached_crt(connector);
413 struct drm_i915_private *dev_priv = to_i915(dev);
414 u32 adpa;
415 bool ret;
416
417 /* The first time through, trigger an explicit detection cycle */
418 if (crt->force_hotplug_required) {
419 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
420 u32 save_adpa;
421
422 crt->force_hotplug_required = 0;
423
424 save_adpa = adpa = I915_READ(crt->adpa_reg);
425 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
426
427 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
428 if (turn_off_dac)
429 adpa &= ~ADPA_DAC_ENABLE;
430
431 I915_WRITE(crt->adpa_reg, adpa);
432
433 if (intel_wait_for_register(dev_priv,
434 crt->adpa_reg,
435 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
436 1000))
437 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
438
439 if (turn_off_dac) {
440 I915_WRITE(crt->adpa_reg, save_adpa);
441 POSTING_READ(crt->adpa_reg);
442 }
443 }
444
445 /* Check the status to see if both blue and green are on now */
446 adpa = I915_READ(crt->adpa_reg);
447 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
448 ret = true;
449 else
450 ret = false;
451 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
452
453 return ret;
454 }
455
valleyview_crt_detect_hotplug(struct drm_connector * connector)456 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
457 {
458 struct drm_device *dev = connector->dev;
459 struct intel_crt *crt = intel_attached_crt(connector);
460 struct drm_i915_private *dev_priv = to_i915(dev);
461 bool reenable_hpd;
462 u32 adpa;
463 bool ret;
464 u32 save_adpa;
465
466 /*
467 * Doing a force trigger causes a hpd interrupt to get sent, which can
468 * get us stuck in a loop if we're polling:
469 * - We enable power wells and reset the ADPA
470 * - output_poll_exec does force probe on VGA, triggering a hpd
471 * - HPD handler waits for poll to unlock dev->mode_config.mutex
472 * - output_poll_exec shuts off the ADPA, unlocks
473 * dev->mode_config.mutex
474 * - HPD handler runs, resets ADPA and brings us back to the start
475 *
476 * Just disable HPD interrupts here to prevent this
477 */
478 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
479
480 save_adpa = adpa = I915_READ(crt->adpa_reg);
481 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
482
483 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
484
485 I915_WRITE(crt->adpa_reg, adpa);
486
487 if (intel_wait_for_register(dev_priv,
488 crt->adpa_reg,
489 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
490 1000)) {
491 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
492 I915_WRITE(crt->adpa_reg, save_adpa);
493 }
494
495 /* Check the status to see if both blue and green are on now */
496 adpa = I915_READ(crt->adpa_reg);
497 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
498 ret = true;
499 else
500 ret = false;
501
502 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
503
504 if (reenable_hpd)
505 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
506
507 return ret;
508 }
509
intel_crt_detect_hotplug(struct drm_connector * connector)510 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
511 {
512 struct drm_device *dev = connector->dev;
513 struct drm_i915_private *dev_priv = to_i915(dev);
514 u32 stat;
515 bool ret = false;
516 int i, tries = 0;
517
518 if (HAS_PCH_SPLIT(dev_priv))
519 return intel_ironlake_crt_detect_hotplug(connector);
520
521 if (IS_VALLEYVIEW(dev_priv))
522 return valleyview_crt_detect_hotplug(connector);
523
524 /*
525 * On 4 series desktop, CRT detect sequence need to be done twice
526 * to get a reliable result.
527 */
528
529 if (IS_G45(dev_priv))
530 tries = 2;
531 else
532 tries = 1;
533
534 for (i = 0; i < tries ; i++) {
535 /* turn on the FORCE_DETECT */
536 i915_hotplug_interrupt_update(dev_priv,
537 CRT_HOTPLUG_FORCE_DETECT,
538 CRT_HOTPLUG_FORCE_DETECT);
539 /* wait for FORCE_DETECT to go off */
540 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
541 CRT_HOTPLUG_FORCE_DETECT, 0,
542 1000))
543 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
544 }
545
546 stat = I915_READ(PORT_HOTPLUG_STAT);
547 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
548 ret = true;
549
550 /* clear the interrupt we just generated, if any */
551 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
552
553 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
554
555 return ret;
556 }
557
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)558 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
559 struct i2c_adapter *i2c)
560 {
561 struct edid *edid;
562
563 edid = drm_get_edid(connector, i2c);
564
565 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
566 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
567 intel_gmbus_force_bit(i2c, true);
568 edid = drm_get_edid(connector, i2c);
569 intel_gmbus_force_bit(i2c, false);
570 }
571
572 return edid;
573 }
574
575 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)576 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
577 struct i2c_adapter *adapter)
578 {
579 struct edid *edid;
580 int ret;
581
582 edid = intel_crt_get_edid(connector, adapter);
583 if (!edid)
584 return 0;
585
586 ret = intel_connector_update_modes(connector, edid);
587 kfree(edid);
588
589 return ret;
590 }
591
intel_crt_detect_ddc(struct drm_connector * connector)592 static bool intel_crt_detect_ddc(struct drm_connector *connector)
593 {
594 struct intel_crt *crt = intel_attached_crt(connector);
595 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
596 struct edid *edid;
597 struct i2c_adapter *i2c;
598 bool ret = false;
599
600 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
601
602 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
603 edid = intel_crt_get_edid(connector, i2c);
604
605 if (edid) {
606 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
607
608 /*
609 * This may be a DVI-I connector with a shared DDC
610 * link between analog and digital outputs, so we
611 * have to check the EDID input spec of the attached device.
612 */
613 if (!is_digital) {
614 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
615 ret = true;
616 } else {
617 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
618 }
619 } else {
620 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
621 }
622
623 kfree(edid);
624
625 return ret;
626 }
627
628 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,uint32_t pipe)629 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
630 {
631 struct drm_device *dev = crt->base.base.dev;
632 struct drm_i915_private *dev_priv = to_i915(dev);
633 uint32_t save_bclrpat;
634 uint32_t save_vtotal;
635 uint32_t vtotal, vactive;
636 uint32_t vsample;
637 uint32_t vblank, vblank_start, vblank_end;
638 uint32_t dsl;
639 i915_reg_t bclrpat_reg, vtotal_reg,
640 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
641 uint8_t st00;
642 enum drm_connector_status status;
643
644 DRM_DEBUG_KMS("starting load-detect on CRT\n");
645
646 bclrpat_reg = BCLRPAT(pipe);
647 vtotal_reg = VTOTAL(pipe);
648 vblank_reg = VBLANK(pipe);
649 vsync_reg = VSYNC(pipe);
650 pipeconf_reg = PIPECONF(pipe);
651 pipe_dsl_reg = PIPEDSL(pipe);
652
653 save_bclrpat = I915_READ(bclrpat_reg);
654 save_vtotal = I915_READ(vtotal_reg);
655 vblank = I915_READ(vblank_reg);
656
657 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
658 vactive = (save_vtotal & 0x7ff) + 1;
659
660 vblank_start = (vblank & 0xfff) + 1;
661 vblank_end = ((vblank >> 16) & 0xfff) + 1;
662
663 /* Set the border color to purple. */
664 I915_WRITE(bclrpat_reg, 0x500050);
665
666 if (!IS_GEN2(dev_priv)) {
667 uint32_t pipeconf = I915_READ(pipeconf_reg);
668 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
669 POSTING_READ(pipeconf_reg);
670 /* Wait for next Vblank to substitue
671 * border color for Color info */
672 intel_wait_for_vblank(dev_priv, pipe);
673 st00 = I915_READ8(_VGA_MSR_WRITE);
674 status = ((st00 & (1 << 4)) != 0) ?
675 connector_status_connected :
676 connector_status_disconnected;
677
678 I915_WRITE(pipeconf_reg, pipeconf);
679 } else {
680 bool restore_vblank = false;
681 int count, detect;
682
683 /*
684 * If there isn't any border, add some.
685 * Yes, this will flicker
686 */
687 if (vblank_start <= vactive && vblank_end >= vtotal) {
688 uint32_t vsync = I915_READ(vsync_reg);
689 uint32_t vsync_start = (vsync & 0xffff) + 1;
690
691 vblank_start = vsync_start;
692 I915_WRITE(vblank_reg,
693 (vblank_start - 1) |
694 ((vblank_end - 1) << 16));
695 restore_vblank = true;
696 }
697 /* sample in the vertical border, selecting the larger one */
698 if (vblank_start - vactive >= vtotal - vblank_end)
699 vsample = (vblank_start + vactive) >> 1;
700 else
701 vsample = (vtotal + vblank_end) >> 1;
702
703 /*
704 * Wait for the border to be displayed
705 */
706 while (I915_READ(pipe_dsl_reg) >= vactive)
707 ;
708 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
709 ;
710 /*
711 * Watch ST00 for an entire scanline
712 */
713 detect = 0;
714 count = 0;
715 do {
716 count++;
717 /* Read the ST00 VGA status register */
718 st00 = I915_READ8(_VGA_MSR_WRITE);
719 if (st00 & (1 << 4))
720 detect++;
721 } while ((I915_READ(pipe_dsl_reg) == dsl));
722
723 /* restore vblank if necessary */
724 if (restore_vblank)
725 I915_WRITE(vblank_reg, vblank);
726 /*
727 * If more than 3/4 of the scanline detected a monitor,
728 * then it is assumed to be present. This works even on i830,
729 * where there isn't any way to force the border color across
730 * the screen
731 */
732 status = detect * 4 > count * 3 ?
733 connector_status_connected :
734 connector_status_disconnected;
735 }
736
737 /* Restore previous settings */
738 I915_WRITE(bclrpat_reg, save_bclrpat);
739
740 return status;
741 }
742
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)743 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
744 {
745 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
746 return 1;
747 }
748
749 static const struct dmi_system_id intel_spurious_crt_detect[] = {
750 {
751 .callback = intel_spurious_crt_detect_dmi_callback,
752 .ident = "ACER ZGB",
753 .matches = {
754 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
755 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
756 },
757 },
758 {
759 .callback = intel_spurious_crt_detect_dmi_callback,
760 .ident = "Intel DZ77BH-55K",
761 .matches = {
762 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
763 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
764 },
765 },
766 { }
767 };
768
769 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)770 intel_crt_detect(struct drm_connector *connector,
771 struct drm_modeset_acquire_ctx *ctx,
772 bool force)
773 {
774 struct drm_i915_private *dev_priv = to_i915(connector->dev);
775 struct intel_crt *crt = intel_attached_crt(connector);
776 struct intel_encoder *intel_encoder = &crt->base;
777 int status, ret;
778 struct intel_load_detect_pipe tmp;
779
780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
781 connector->base.id, connector->name,
782 force);
783
784 if (i915_modparams.load_detect_test) {
785 intel_display_power_get(dev_priv, intel_encoder->power_domain);
786 goto load_detect;
787 }
788
789 /* Skip machines without VGA that falsely report hotplug events */
790 if (dmi_check_system(intel_spurious_crt_detect))
791 return connector_status_disconnected;
792
793 intel_display_power_get(dev_priv, intel_encoder->power_domain);
794
795 if (I915_HAS_HOTPLUG(dev_priv)) {
796 /* We can not rely on the HPD pin always being correctly wired
797 * up, for example many KVM do not pass it through, and so
798 * only trust an assertion that the monitor is connected.
799 */
800 if (intel_crt_detect_hotplug(connector)) {
801 DRM_DEBUG_KMS("CRT detected via hotplug\n");
802 status = connector_status_connected;
803 goto out;
804 } else
805 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
806 }
807
808 if (intel_crt_detect_ddc(connector)) {
809 status = connector_status_connected;
810 goto out;
811 }
812
813 /* Load detection is broken on HPD capable machines. Whoever wants a
814 * broken monitor (without edid) to work behind a broken kvm (that fails
815 * to have the right resistors for HP detection) needs to fix this up.
816 * For now just bail out. */
817 if (I915_HAS_HOTPLUG(dev_priv)) {
818 status = connector_status_disconnected;
819 goto out;
820 }
821
822 load_detect:
823 if (!force) {
824 status = connector->status;
825 goto out;
826 }
827
828 /* for pre-945g platforms use load detect */
829 ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
830 if (ret > 0) {
831 if (intel_crt_detect_ddc(connector))
832 status = connector_status_connected;
833 else if (INTEL_GEN(dev_priv) < 4)
834 status = intel_crt_load_detect(crt,
835 to_intel_crtc(connector->state->crtc)->pipe);
836 else if (i915_modparams.load_detect_test)
837 status = connector_status_disconnected;
838 else
839 status = connector_status_unknown;
840 intel_release_load_detect_pipe(connector, &tmp, ctx);
841 } else if (ret == 0) {
842 status = connector_status_unknown;
843 } else {
844 status = ret;
845 }
846
847 out:
848 intel_display_power_put(dev_priv, intel_encoder->power_domain);
849 return status;
850 }
851
intel_crt_destroy(struct drm_connector * connector)852 static void intel_crt_destroy(struct drm_connector *connector)
853 {
854 drm_connector_cleanup(connector);
855 kfree(connector);
856 }
857
intel_crt_get_modes(struct drm_connector * connector)858 static int intel_crt_get_modes(struct drm_connector *connector)
859 {
860 struct drm_device *dev = connector->dev;
861 struct drm_i915_private *dev_priv = to_i915(dev);
862 struct intel_crt *crt = intel_attached_crt(connector);
863 struct intel_encoder *intel_encoder = &crt->base;
864 int ret;
865 struct i2c_adapter *i2c;
866
867 intel_display_power_get(dev_priv, intel_encoder->power_domain);
868
869 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
870 ret = intel_crt_ddc_get_modes(connector, i2c);
871 if (ret || !IS_G4X(dev_priv))
872 goto out;
873
874 /* Try to probe digital port for output in DVI-I -> VGA mode. */
875 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
876 ret = intel_crt_ddc_get_modes(connector, i2c);
877
878 out:
879 intel_display_power_put(dev_priv, intel_encoder->power_domain);
880
881 return ret;
882 }
883
intel_crt_reset(struct drm_encoder * encoder)884 void intel_crt_reset(struct drm_encoder *encoder)
885 {
886 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
887 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
888
889 if (INTEL_GEN(dev_priv) >= 5) {
890 u32 adpa;
891
892 adpa = I915_READ(crt->adpa_reg);
893 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
894 adpa |= ADPA_HOTPLUG_BITS;
895 I915_WRITE(crt->adpa_reg, adpa);
896 POSTING_READ(crt->adpa_reg);
897
898 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
899 crt->force_hotplug_required = 1;
900 }
901
902 }
903
904 /*
905 * Routines for controlling stuff on the analog port
906 */
907
908 static const struct drm_connector_funcs intel_crt_connector_funcs = {
909 .fill_modes = drm_helper_probe_single_connector_modes,
910 .late_register = intel_connector_register,
911 .early_unregister = intel_connector_unregister,
912 .destroy = intel_crt_destroy,
913 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
914 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
915 };
916
917 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
918 .detect_ctx = intel_crt_detect,
919 .mode_valid = intel_crt_mode_valid,
920 .get_modes = intel_crt_get_modes,
921 };
922
923 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
924 .reset = intel_crt_reset,
925 .destroy = intel_encoder_destroy,
926 };
927
intel_crt_init(struct drm_i915_private * dev_priv)928 void intel_crt_init(struct drm_i915_private *dev_priv)
929 {
930 struct drm_connector *connector;
931 struct intel_crt *crt;
932 struct intel_connector *intel_connector;
933 i915_reg_t adpa_reg;
934 u32 adpa;
935
936 if (HAS_PCH_SPLIT(dev_priv))
937 adpa_reg = PCH_ADPA;
938 else if (IS_VALLEYVIEW(dev_priv))
939 adpa_reg = VLV_ADPA;
940 else
941 adpa_reg = ADPA;
942
943 adpa = I915_READ(adpa_reg);
944 if ((adpa & ADPA_DAC_ENABLE) == 0) {
945 /*
946 * On some machines (some IVB at least) CRT can be
947 * fused off, but there's no known fuse bit to
948 * indicate that. On these machine the ADPA register
949 * works normally, except the DAC enable bit won't
950 * take. So the only way to tell is attempt to enable
951 * it and see what happens.
952 */
953 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
954 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
955 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
956 return;
957 I915_WRITE(adpa_reg, adpa);
958 }
959
960 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
961 if (!crt)
962 return;
963
964 intel_connector = intel_connector_alloc();
965 if (!intel_connector) {
966 kfree(crt);
967 return;
968 }
969
970 connector = &intel_connector->base;
971 crt->connector = intel_connector;
972 drm_connector_init(&dev_priv->drm, &intel_connector->base,
973 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
974
975 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
976 DRM_MODE_ENCODER_DAC, "CRT");
977
978 intel_connector_attach_encoder(intel_connector, &crt->base);
979
980 crt->base.type = INTEL_OUTPUT_ANALOG;
981 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
982 if (IS_I830(dev_priv))
983 crt->base.crtc_mask = (1 << 0);
984 else
985 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
986
987 if (IS_GEN2(dev_priv))
988 connector->interlace_allowed = 0;
989 else
990 connector->interlace_allowed = 1;
991 connector->doublescan_allowed = 0;
992
993 crt->adpa_reg = adpa_reg;
994
995 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
996
997 if (I915_HAS_HOTPLUG(dev_priv) &&
998 !dmi_check_system(intel_spurious_crt_detect)) {
999 crt->base.hpd_pin = HPD_CRT;
1000 crt->base.hotplug = intel_encoder_hotplug;
1001 }
1002
1003 if (HAS_DDI(dev_priv)) {
1004 crt->base.port = PORT_E;
1005 crt->base.get_config = hsw_crt_get_config;
1006 crt->base.get_hw_state = intel_ddi_get_hw_state;
1007 crt->base.compute_config = hsw_crt_compute_config;
1008 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1009 crt->base.pre_enable = hsw_pre_enable_crt;
1010 crt->base.enable = hsw_enable_crt;
1011 crt->base.disable = hsw_disable_crt;
1012 crt->base.post_disable = hsw_post_disable_crt;
1013 } else {
1014 if (HAS_PCH_SPLIT(dev_priv)) {
1015 crt->base.compute_config = pch_crt_compute_config;
1016 crt->base.disable = pch_disable_crt;
1017 crt->base.post_disable = pch_post_disable_crt;
1018 } else {
1019 crt->base.compute_config = intel_crt_compute_config;
1020 crt->base.disable = intel_disable_crt;
1021 }
1022 crt->base.port = PORT_NONE;
1023 crt->base.get_config = intel_crt_get_config;
1024 crt->base.get_hw_state = intel_crt_get_hw_state;
1025 crt->base.enable = intel_enable_crt;
1026 }
1027 intel_connector->get_hw_state = intel_connector_get_hw_state;
1028
1029 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1030
1031 if (!I915_HAS_HOTPLUG(dev_priv))
1032 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1033
1034 /*
1035 * Configure the automatic hotplug detection stuff
1036 */
1037 crt->force_hotplug_required = 0;
1038
1039 /*
1040 * TODO: find a proper way to discover whether we need to set the the
1041 * polarity and link reversal bits or not, instead of relying on the
1042 * BIOS.
1043 */
1044 if (HAS_PCH_LPT(dev_priv)) {
1045 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1046 FDI_RX_LINK_REVERSAL_OVERRIDE;
1047
1048 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1049 }
1050
1051 intel_crt_reset(&crt->base.base);
1052 }
1053
