1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2017-2018, Intel Corporation
4  */
5 
6 #ifndef __STRATIX10_SMC_H
7 #define __STRATIX10_SMC_H
8 
9 #include <linux/arm-smccc.h>
10 #include <linux/bitops.h>
11 
12 /**
13  * This file defines the Secure Monitor Call (SMC) message protocol used for
14  * service layer driver in normal world (EL1) to communicate with secure
15  * monitor software in Secure Monitor Exception Level 3 (EL3).
16  *
17  * This file is shared with secure firmware (FW) which is out of kernel tree.
18  *
19  * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20  * register values as arguments, and can return up to 4 64-bit register
21  * value. The operation of the secure monitor is determined by the parameter
22  * values passed in through registers.
23  *
24  * EL1 and EL3 communicates pointer as physical address rather than the
25  * virtual address.
26  *
27  * Functions specified by ARM SMC Calling convention:
28  *
29  * FAST call executes atomic operations, returns when the requested operation
30  * has completed.
31  * STD call starts a operation which can be preempted by a non-secure
32  * interrupt. The call can return before the requested operation has
33  * completed.
34  *
35  * a0..a7 is used as register names in the descriptions below, on arm32
36  * that translates to r0..r7 and on arm64 to w0..w7.
37  */
38 
39 /**
40  * @func_num: function ID
41  */
42 #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
43 	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
44 	ARM_SMCCC_OWNER_SIP, (func_num))
45 
46 #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
47 	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
48 	ARM_SMCCC_OWNER_SIP, (func_num))
49 
50 /**
51  * Return values in INTEL_SIP_SMC_* call
52  *
53  * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
54  * Secure monitor software doesn't recognize the request.
55  *
56  * INTEL_SIP_SMC_STATUS_OK:
57  * FPGA configuration completed successfully,
58  * In case of FPGA configuration write operation, it means secure monitor
59  * software can accept the next chunk of FPGA configuration data.
60  *
61  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
62  * In case of FPGA configuration write operation, it means secure monitor
63  * software is still processing previous data & can't accept the next chunk
64  * of data. Service driver needs to issue
65  * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
66  * completed block(s).
67  *
68  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
69  * There is error during the FPGA configuration process.
70  *
71  * INTEL_SIP_SMC_REG_ERROR:
72  * There is error during a read or write operation of the protected registers.
73  *
74  * INTEL_SIP_SMC_RSU_ERROR:
75  * There is error during a remote status update.
76  */
77 #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION		0xFFFFFFFF
78 #define INTEL_SIP_SMC_STATUS_OK				0x0
79 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY		0x1
80 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED       0x2
81 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR		0x4
82 #define INTEL_SIP_SMC_REG_ERROR				0x5
83 #define INTEL_SIP_SMC_RSU_ERROR				0x7
84 
85 /**
86  * Request INTEL_SIP_SMC_FPGA_CONFIG_START
87  *
88  * Sync call used by service driver at EL1 to request the FPGA in EL3 to
89  * be prepare to receive a new configuration.
90  *
91  * Call register usage:
92  * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
93  * a1: flag for full or partial configuration. 0 for full and 1 for partial
94  * configuration.
95  * a2-7: not used.
96  *
97  * Return status:
98  * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
99  * a1-3: not used.
100  */
101 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
102 #define INTEL_SIP_SMC_FPGA_CONFIG_START \
103 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
104 
105 /**
106  * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
107  *
108  * Async call used by service driver at EL1 to provide FPGA configuration data
109  * to secure world.
110  *
111  * Call register usage:
112  * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
113  * a1: 64bit physical address of the configuration data memory block
114  * a2: Size of configuration data block.
115  * a3-7: not used.
116  *
117  * Return status:
118  * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
119  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
120  * a1: 64bit physical address of 1st completed memory block if any completed
121  * block, otherwise zero value.
122  * a2: 64bit physical address of 2nd completed memory block if any completed
123  * block, otherwise zero value.
124  * a3: 64bit physical address of 3rd completed memory block if any completed
125  * block, otherwise zero value.
126  */
127 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
128 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
129 	INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
130 
131 /**
132  * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
133  *
134  * Sync call used by service driver at EL1 to track the completed write
135  * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
136  * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY.
137  *
138  * Call register usage:
139  * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
140  * a1-7: not used.
141  *
142  * Return status:
143  * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
144  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
145  * a1: 64bit physical address of 1st completed memory block.
146  * a2: 64bit physical address of 2nd completed memory block if
147  * any completed block, otherwise zero value.
148  * a3: 64bit physical address of 3rd completed memory block if
149  * any completed block, otherwise zero value.
150  */
151 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
152 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
153 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
154 
155 /**
156  * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
157  *
158  * Sync call used by service driver at EL1 to inform secure world that all
159  * data are sent, to check whether or not the secure world had completed
160  * the FPGA configuration process.
161  *
162  * Call register usage:
163  * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
164  * a1-7: not used.
165  *
166  * Return status:
167  * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
168  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
169  * a1-3: not used.
170  */
171 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
172 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
173 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
174 
175 /**
176  * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
177  *
178  * Sync call used by service driver at EL1 to query the physical address of
179  * memory block reserved by secure monitor software.
180  *
181  * Call register usage:
182  * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
183  * a1-7: not used.
184  *
185  * Return status:
186  * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
187  * a1: start of physical address of reserved memory block.
188  * a2: size of reserved memory block.
189  * a3: not used.
190  */
191 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
192 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
193 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
194 
195 /**
196  * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
197  *
198  * For SMC loop-back mode only, used for internal integration, debugging
199  * or troubleshooting.
200  *
201  * Call register usage:
202  * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
203  * a1-7: not used.
204  *
205  * Return status:
206  * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
207  * a1-3: not used.
208  */
209 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
210 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
211 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
212 
213 /**
214  * Request INTEL_SIP_SMC_REG_READ
215  *
216  * Read a protected register at EL3
217  *
218  * Call register usage:
219  * a0: INTEL_SIP_SMC_REG_READ.
220  * a1: register address.
221  * a2-7: not used.
222  *
223  * Return status:
224  * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
225  * a1: value in the register
226  * a2-3: not used.
227  */
228 #define INTEL_SIP_SMC_FUNCID_REG_READ 7
229 #define INTEL_SIP_SMC_REG_READ \
230 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
231 
232 /**
233  * Request INTEL_SIP_SMC_REG_WRITE
234  *
235  * Write a protected register at EL3
236  *
237  * Call register usage:
238  * a0: INTEL_SIP_SMC_REG_WRITE.
239  * a1: register address
240  * a2: value to program into register.
241  * a3-7: not used.
242  *
243  * Return status:
244  * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
245  * a1-3: not used.
246  */
247 #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
248 #define INTEL_SIP_SMC_REG_WRITE \
249 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
250 
251 /**
252  * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
253  *
254  * Update one or more bits in a protected register at EL3 using a
255  * read-modify-write operation.
256  *
257  * Call register usage:
258  * a0: INTEL_SIP_SMC_REG_UPDATE.
259  * a1: register address
260  * a2: write Mask.
261  * a3: value to write.
262  * a4-7: not used.
263  *
264  * Return status:
265  * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
266  * a1-3: Not used.
267  */
268 #define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
269 #define INTEL_SIP_SMC_REG_UPDATE \
270 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
271 
272 /**
273  * Request INTEL_SIP_SMC_RSU_STATUS
274  *
275  * Request remote status update boot log, call is synchronous.
276  *
277  * Call register usage:
278  * a0 INTEL_SIP_SMC_RSU_STATUS
279  * a1-7 not used
280  *
281  * Return status
282  * a0: Current Image
283  * a1: Last Failing Image
284  * a2: Version | State
285  * a3: Error details | Error location
286  *
287  * Or
288  *
289  * a0: INTEL_SIP_SMC_RSU_ERROR
290  */
291 #define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
292 #define INTEL_SIP_SMC_RSU_STATUS \
293 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
294 
295 /**
296  * Request INTEL_SIP_SMC_RSU_UPDATE
297  *
298  * Request to set the offset of the bitstream to boot after reboot, call
299  * is synchronous.
300  *
301  * Call register usage:
302  * a0 INTEL_SIP_SMC_RSU_UPDATE
303  * a1 64bit physical address of the configuration data memory in flash
304  * a2-7 not used
305  *
306  * Return status
307  * a0 INTEL_SIP_SMC_STATUS_OK
308  */
309 #define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
310 #define INTEL_SIP_SMC_RSU_UPDATE \
311 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
312 
313 /**
314  * Request INTEL_SIP_SMC_ECC_DBE
315  *
316  * Sync call used by service driver at EL1 to alert EL3 that a Double
317  * Bit ECC error has occurred.
318  *
319  * Call register usage:
320  * a0 INTEL_SIP_SMC_ECC_DBE
321  * a1 SysManager Double Bit Error value
322  * a2-7 not used
323  *
324  * Return status
325  * a0 INTEL_SIP_SMC_STATUS_OK
326  */
327 #define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
328 #define INTEL_SIP_SMC_ECC_DBE \
329 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
330 
331 #endif
332 
333 /**
334  * Request INTEL_SIP_SMC_RSU_NOTIFY
335  *
336  * Sync call used by service driver at EL1 to report hard processor
337  * system execution stage to firmware
338  *
339  * Call register usage:
340  * a0 INTEL_SIP_SMC_RSU_NOTIFY
341  * a1 32bit value representing hard processor system execution stage
342  * a2-7 not used
343  *
344  * Return status
345  * a0 INTEL_SIP_SMC_STATUS_OK
346  */
347 #define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
348 #define INTEL_SIP_SMC_RSU_NOTIFY \
349 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
350 
351 /**
352  * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
353  *
354  * Sync call used by service driver at EL1 to query RSU retry counter
355  *
356  * Call register usage:
357  * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
358  * a1-7 not used
359  *
360  * Return status
361  * a0 INTEL_SIP_SMC_STATUS_OK
362  * a1 the retry counter
363  *
364  * Or
365  *
366  * a0 INTEL_SIP_SMC_RSU_ERROR
367  */
368 #define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
369 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
370 	INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
371