1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include "imx7s.dtsi"
7#include <dt-bindings/reset/imx7-reset.h>
8
9/ {
10	cpus {
11		cpu0: cpu@0 {
12			clock-frequency = <996000000>;
13			operating-points-v2 = <&cpu0_opp_table>;
14			#cooling-cells = <2>;
15		};
16
17		cpu1: cpu@1 {
18			compatible = "arm,cortex-a7";
19			device_type = "cpu";
20			reg = <1>;
21			clock-frequency = <996000000>;
22			operating-points-v2 = <&cpu0_opp_table>;
23		};
24	};
25
26	cpu0_opp_table: opp-table {
27		compatible = "operating-points-v2";
28		opp-shared;
29
30		opp-792000000 {
31			opp-hz = /bits/ 64 <792000000>;
32			opp-microvolt = <975000>;
33			clock-latency-ns = <150000>;
34		};
35
36		opp-996000000 {
37			opp-hz = /bits/ 64 <996000000>;
38			opp-microvolt = <1075000>;
39			clock-latency-ns = <150000>;
40			opp-suspend;
41		};
42	};
43
44	usbphynop2: usbphynop2 {
45		compatible = "usb-nop-xceiv";
46		clocks = <&clks IMX7D_USB_PHY2_CLK>;
47		clock-names = "main_clk";
48		#phy-cells = <0>;
49	};
50
51	soc {
52		etm@3007d000 {
53			compatible = "arm,coresight-etm3x", "arm,primecell";
54			reg = <0x3007d000 0x1000>;
55
56			/*
57			 * System will hang if added nosmp in kernel command line
58			 * without arm,primecell-periphid because amba bus try to
59			 * read id and core1 power off at this time.
60			 */
61			arm,primecell-periphid = <0xbb956>;
62			cpu = <&cpu1>;
63			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
64			clock-names = "apb_pclk";
65
66			port {
67				etm1_out_port: endpoint {
68					remote-endpoint = <&ca_funnel_in_port1>;
69				};
70			};
71		};
72	};
73};
74
75&aips3 {
76	usbotg2: usb@30b20000 {
77		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
78		reg = <0x30b20000 0x200>;
79		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
80		clocks = <&clks IMX7D_USB_CTRL_CLK>;
81		fsl,usbphy = <&usbphynop2>;
82		fsl,usbmisc = <&usbmisc2 0>;
83		phy-clkgate-delay-us = <400>;
84		status = "disabled";
85	};
86
87	usbmisc2: usbmisc@30b20200 {
88		#index-cells = <1>;
89		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
90		reg = <0x30b20200 0x200>;
91	};
92
93	fec2: ethernet@30bf0000 {
94		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
95		reg = <0x30bf0000 0x10000>;
96		interrupt-names = "int0", "int1", "int2", "pps";
97		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
98			<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
99			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
100			<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
101		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
102			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
103			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
104			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
105			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
106		clock-names = "ipg", "ahb", "ptp",
107			"enet_clk_ref", "enet_out";
108		fsl,num-tx-queues=<3>;
109		fsl,num-rx-queues=<3>;
110		status = "disabled";
111	};
112
113	pcie: pcie@33800000 {
114		compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
115		reg = <0x33800000 0x4000>,
116		      <0x4ff00000 0x80000>;
117		reg-names = "dbi", "config";
118		#address-cells = <3>;
119		#size-cells = <2>;
120		device_type = "pci";
121		bus-range = <0x00 0xff>;
122		ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
123			  0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
124		num-lanes = <1>;
125		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
126		interrupt-names = "msi";
127		#interrupt-cells = <1>;
128		interrupt-map-mask = <0 0 0 0x7>;
129		/*
130		 * Reference manual lists pci irqs incorrectly
131		 * Real hardware ordering is same as imx6: D+MSI, C, B, A
132		 */
133		interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
134				<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
135				<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
136				<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
137		clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
138			 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
139			 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
140		clock-names = "pcie", "pcie_bus", "pcie_phy";
141		assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
142				  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
143		assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
144					 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
145
146		fsl,max-link-speed = <2>;
147		power-domains = <&pgc_pcie_phy>;
148		resets = <&src IMX7_RESET_PCIEPHY>,
149			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
150		reset-names = "pciephy", "apps";
151		status = "disabled";
152	};
153};
154
155&ca_funnel_ports {
156	port@1 {
157		reg = <1>;
158		ca_funnel_in_port1: endpoint {
159			slave-mode;
160			remote-endpoint = <&etm1_out_port>;
161		};
162	};
163};
164