1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11	chosen {
12		stdout-path = &uart1;
13	};
14
15	memory@10000000 {
16		device_type = "memory";
17		reg = <0x10000000 0x40000000>;
18	};
19
20	reg_usb_otg_vbus: regulator-usb-otg-vbus {
21		compatible = "regulator-fixed";
22		regulator-name = "usb_otg_vbus";
23		regulator-min-microvolt = <5000000>;
24		regulator-max-microvolt = <5000000>;
25		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
26		enable-active-high;
27		vin-supply = <&swbst_reg>;
28	};
29
30	reg_usb_h1_vbus: regulator-usb-h1-vbus {
31		compatible = "regulator-fixed";
32		regulator-name = "usb_h1_vbus";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
36		enable-active-high;
37		vin-supply = <&swbst_reg>;
38	};
39
40	reg_audio: regulator-audio {
41		compatible = "regulator-fixed";
42		regulator-name = "wm8962-supply";
43		gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46
47	reg_pcie: regulator-pcie {
48		compatible = "regulator-fixed";
49		pinctrl-names = "default";
50		pinctrl-0 = <&pinctrl_pcie_reg>;
51		regulator-name = "MPCIE_3V3";
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	reg_sensors: regulator-sensors {
59		compatible = "regulator-fixed";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_sensors_reg>;
62		regulator-name = "sensors-supply";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67	};
68
69	gpio-keys {
70		compatible = "gpio-keys";
71		pinctrl-names = "default";
72		pinctrl-0 = <&pinctrl_gpio_keys>;
73
74		power {
75			label = "Power Button";
76			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
77			wakeup-source;
78			linux,code = <KEY_POWER>;
79		};
80
81		volume-up {
82			label = "Volume Up";
83			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
84			wakeup-source;
85			linux,code = <KEY_VOLUMEUP>;
86		};
87
88		volume-down {
89			label = "Volume Down";
90			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
91			wakeup-source;
92			linux,code = <KEY_VOLUMEDOWN>;
93		};
94	};
95
96	sound {
97		compatible = "fsl,imx6q-sabresd-wm8962",
98			   "fsl,imx-audio-wm8962";
99		model = "wm8962-audio";
100		ssi-controller = <&ssi2>;
101		audio-codec = <&codec>;
102		audio-routing =
103			"Headphone Jack", "HPOUTL",
104			"Headphone Jack", "HPOUTR",
105			"Ext Spk", "SPKOUTL",
106			"Ext Spk", "SPKOUTR",
107			"AMIC", "MICBIAS",
108			"IN3R", "AMIC";
109		mux-int-port = <2>;
110		mux-ext-port = <3>;
111	};
112
113	backlight_lvds: backlight-lvds {
114		compatible = "pwm-backlight";
115		pwms = <&pwm1 0 5000000>;
116		brightness-levels = <0 4 8 16 32 64 128 255>;
117		default-brightness-level = <7>;
118		status = "okay";
119	};
120
121	leds {
122		compatible = "gpio-leds";
123		pinctrl-names = "default";
124		pinctrl-0 = <&pinctrl_gpio_leds>;
125
126		red {
127			gpios = <&gpio1 2 0>;
128			default-state = "on";
129		};
130	};
131
132	panel {
133		compatible = "hannstar,hsd100pxn1";
134		backlight = <&backlight_lvds>;
135
136		port {
137			panel_in: endpoint {
138				remote-endpoint = <&lvds0_out>;
139			};
140		};
141	};
142};
143
144&ipu1_csi0_from_ipu1_csi0_mux {
145	bus-width = <8>;
146	data-shift = <12>; /* Lines 19:12 used */
147	hsync-active = <1>;
148	vsync-active = <1>;
149};
150
151&ipu1_csi0_mux_from_parallel_sensor {
152	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
153};
154
155&ipu1_csi0 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&pinctrl_ipu1_csi0>;
158};
159
160&mipi_csi {
161	status = "okay";
162
163	port@0 {
164		reg = <0>;
165
166		mipi_csi2_in: endpoint {
167			remote-endpoint = <&ov5640_to_mipi_csi2>;
168			clock-lanes = <0>;
169			data-lanes = <1 2>;
170		};
171	};
172};
173
174&audmux {
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_audmux>;
177	status = "okay";
178};
179
180&clks {
181	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
182			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
183	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
184				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
185};
186
187&ecspi1 {
188	cs-gpios = <&gpio4 9 0>;
189	pinctrl-names = "default";
190	pinctrl-0 = <&pinctrl_ecspi1>;
191	status = "okay";
192
193	flash: m25p80@0 {
194		#address-cells = <1>;
195		#size-cells = <1>;
196		compatible = "st,m25p32", "jedec,spi-nor";
197		spi-max-frequency = <20000000>;
198		reg = <0>;
199	};
200};
201
202&fec {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_enet>;
205	phy-mode = "rgmii-id";
206	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
207	status = "okay";
208};
209
210&hdmi {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_hdmi_cec>;
213	ddc-i2c-bus = <&i2c2>;
214	status = "okay";
215};
216
217&i2c1 {
218	clock-frequency = <100000>;
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_i2c1>;
221	status = "okay";
222
223	codec: wm8962@1a {
224		compatible = "wlf,wm8962";
225		reg = <0x1a>;
226		clocks = <&clks IMX6QDL_CLK_CKO>;
227		DCVDD-supply = <&reg_audio>;
228		DBVDD-supply = <&reg_audio>;
229		AVDD-supply = <&reg_audio>;
230		CPVDD-supply = <&reg_audio>;
231		MICVDD-supply = <&reg_audio>;
232		PLLVDD-supply = <&reg_audio>;
233		SPKVDD1-supply = <&reg_audio>;
234		SPKVDD2-supply = <&reg_audio>;
235		gpio-cfg = <
236			0x0000 /* 0:Default */
237			0x0000 /* 1:Default */
238			0x0013 /* 2:FN_DMICCLK */
239			0x0000 /* 3:Default */
240			0x8014 /* 4:FN_DMICCDAT */
241			0x0000 /* 5:Default */
242		>;
243	};
244
245	accelerometer@1c {
246		compatible = "fsl,mma8451";
247		reg = <0x1c>;
248		pinctrl-names = "default";
249		pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
250		interrupt-parent = <&gpio1>;
251		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
252		vdd-supply = <&reg_sensors>;
253		vddio-supply = <&reg_sensors>;
254	};
255
256	ov5642: camera@3c {
257		compatible = "ovti,ov5642";
258		pinctrl-names = "default";
259		pinctrl-0 = <&pinctrl_ov5642>;
260		clocks = <&clks IMX6QDL_CLK_CKO>;
261		clock-names = "xclk";
262		reg = <0x3c>;
263		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
264		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
265						rev B board is VGEN5 */
266		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
267		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
268		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
269		status = "disabled";
270
271		port {
272			ov5642_to_ipu1_csi0_mux: endpoint {
273				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
274				bus-width = <8>;
275				hsync-active = <1>;
276				vsync-active = <1>;
277			};
278		};
279	};
280};
281
282&i2c2 {
283	clock-frequency = <100000>;
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_i2c2>;
286	status = "okay";
287
288	touchscreen@4 {
289		compatible = "eeti,egalax_ts";
290		reg = <0x04>;
291		pinctrl-names = "default";
292		pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
293		interrupt-parent = <&gpio6>;
294		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
295		wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
296	};
297
298	ov5640: camera@3c {
299		compatible = "ovti,ov5640";
300		pinctrl-names = "default";
301		pinctrl-0 = <&pinctrl_ov5640>;
302		reg = <0x3c>;
303		clocks = <&clks IMX6QDL_CLK_CKO>;
304		clock-names = "xclk";
305		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
306		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
307						rev B board is VGEN5 */
308		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
309		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
310		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
311
312		port {
313			ov5640_to_mipi_csi2: endpoint {
314				remote-endpoint = <&mipi_csi2_in>;
315				clock-lanes = <0>;
316				data-lanes = <1 2>;
317			};
318		};
319	};
320
321	pmic: pfuze100@8 {
322		compatible = "fsl,pfuze100";
323		reg = <0x08>;
324
325		regulators {
326			sw1a_reg: sw1ab {
327				regulator-min-microvolt = <300000>;
328				regulator-max-microvolt = <1875000>;
329				regulator-boot-on;
330				regulator-always-on;
331				regulator-ramp-delay = <6250>;
332			};
333
334			sw1c_reg: sw1c {
335				regulator-min-microvolt = <300000>;
336				regulator-max-microvolt = <1875000>;
337				regulator-boot-on;
338				regulator-always-on;
339				regulator-ramp-delay = <6250>;
340			};
341
342			sw2_reg: sw2 {
343				regulator-min-microvolt = <800000>;
344				regulator-max-microvolt = <3300000>;
345				regulator-boot-on;
346				regulator-always-on;
347				regulator-ramp-delay = <6250>;
348			};
349
350			sw3a_reg: sw3a {
351				regulator-min-microvolt = <400000>;
352				regulator-max-microvolt = <1975000>;
353				regulator-boot-on;
354				regulator-always-on;
355			};
356
357			sw3b_reg: sw3b {
358				regulator-min-microvolt = <400000>;
359				regulator-max-microvolt = <1975000>;
360				regulator-boot-on;
361				regulator-always-on;
362			};
363
364			sw4_reg: sw4 {
365				regulator-min-microvolt = <800000>;
366				regulator-max-microvolt = <3300000>;
367				regulator-always-on;
368			};
369
370			swbst_reg: swbst {
371				regulator-min-microvolt = <5000000>;
372				regulator-max-microvolt = <5150000>;
373			};
374
375			snvs_reg: vsnvs {
376				regulator-min-microvolt = <1000000>;
377				regulator-max-microvolt = <3000000>;
378				regulator-boot-on;
379				regulator-always-on;
380			};
381
382			vref_reg: vrefddr {
383				regulator-boot-on;
384				regulator-always-on;
385			};
386
387			vgen1_reg: vgen1 {
388				regulator-min-microvolt = <800000>;
389				regulator-max-microvolt = <1550000>;
390			};
391
392			vgen2_reg: vgen2 {
393				regulator-min-microvolt = <800000>;
394				regulator-max-microvolt = <1550000>;
395			};
396
397			vgen3_reg: vgen3 {
398				regulator-min-microvolt = <1800000>;
399				regulator-max-microvolt = <3300000>;
400			};
401
402			vgen4_reg: vgen4 {
403				regulator-min-microvolt = <1800000>;
404				regulator-max-microvolt = <3300000>;
405				regulator-always-on;
406			};
407
408			vgen5_reg: vgen5 {
409				regulator-min-microvolt = <1800000>;
410				regulator-max-microvolt = <3300000>;
411				regulator-always-on;
412			};
413
414			vgen6_reg: vgen6 {
415				regulator-min-microvolt = <1800000>;
416				regulator-max-microvolt = <3300000>;
417				regulator-always-on;
418			};
419		};
420	};
421};
422
423&i2c3 {
424	clock-frequency = <100000>;
425	pinctrl-names = "default";
426	pinctrl-0 = <&pinctrl_i2c3>;
427	status = "okay";
428
429	egalax_ts@4 {
430		compatible = "eeti,egalax_ts";
431		reg = <0x04>;
432		interrupt-parent = <&gpio6>;
433		interrupts = <7 2>;
434		wakeup-gpios = <&gpio6 7 0>;
435	};
436
437	magnetometer@e {
438		compatible = "fsl,mag3110";
439		reg = <0x0e>;
440		pinctrl-names = "default";
441		pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
442		interrupt-parent = <&gpio3>;
443		interrupts = <16 IRQ_TYPE_EDGE_RISING>;
444		vdd-supply = <&reg_sensors>;
445		vddio-supply = <&reg_sensors>;
446	};
447
448	light-sensor@44 {
449		compatible = "isil,isl29023";
450		reg = <0x44>;
451		pinctrl-names = "default";
452		pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
453		interrupt-parent = <&gpio3>;
454		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
455		vcc-supply = <&reg_sensors>;
456	};
457};
458
459&iomuxc {
460	pinctrl-names = "default";
461	pinctrl-0 = <&pinctrl_hog>;
462
463	imx6qdl-sabresd {
464		pinctrl_hog: hoggrp {
465			fsl,pins = <
466				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
467				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
468				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
469				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
470				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
471				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
472				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
473				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
474				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
475			>;
476		};
477
478		pinctrl_audmux: audmuxgrp {
479			fsl,pins = <
480				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
481				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
482				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
483				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
484			>;
485		};
486
487		pinctrl_ecspi1: ecspi1grp {
488			fsl,pins = <
489				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
490				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
491				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
492				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
493			>;
494		};
495
496		pinctrl_enet: enetgrp {
497			fsl,pins = <
498				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
499				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
500				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
501				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
502				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
503				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
504				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
505				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
506				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
507				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
508				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
509				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
510				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
511				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
512				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
513				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
514			>;
515		};
516
517		pinctrl_gpio_keys: gpio_keysgrp {
518			fsl,pins = <
519				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
520				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
521				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
522			>;
523		};
524
525		pinctrl_hdmi_cec: hdmicecgrp {
526			fsl,pins = <
527				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
528			>;
529		};
530
531		pinctrl_i2c1: i2c1grp {
532			fsl,pins = <
533				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
534				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
535			>;
536		};
537
538		pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
539			fsl,pins = <
540				MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0xb0b1
541			>;
542		};
543
544		pinctrl_i2c2: i2c2grp {
545			fsl,pins = <
546				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
547				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
548			>;
549		};
550
551		pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
552			fsl,pins = <
553				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x1b0b0
554			>;
555		};
556
557		pinctrl_i2c3: i2c3grp {
558			fsl,pins = <
559				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
560				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
561			>;
562		};
563
564		pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
565			fsl,pins = <
566				MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0xb0b1
567			>;
568		};
569
570		pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
571			fsl,pins = <
572				MX6QDL_PAD_EIM_D16__GPIO3_IO16		0xb0b1
573			>;
574		};
575
576		pinctrl_ipu1_csi0: ipu1csi0grp {
577			fsl,pins = <
578				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
579				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
580				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
581				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
582				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
583				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
584				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
585				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
586				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
587				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
588				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
589			>;
590		};
591
592		pinctrl_ov5640: ov5640grp {
593			fsl,pins = <
594				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
595				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
596			>;
597		};
598
599		pinctrl_ov5642: ov5642grp {
600			fsl,pins = <
601				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
602				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
603			>;
604		};
605
606		pinctrl_pcie: pciegrp {
607			fsl,pins = <
608				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
609			>;
610		};
611
612		pinctrl_pcie_reg: pciereggrp {
613			fsl,pins = <
614				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
615			>;
616		};
617
618		pinctrl_pwm1: pwm1grp {
619			fsl,pins = <
620				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
621			>;
622		};
623
624		pinctrl_sensors_reg: sensorsreggrp {
625			fsl,pins = <
626				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b0
627			>;
628		};
629
630		pinctrl_uart1: uart1grp {
631			fsl,pins = <
632				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
633				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
634			>;
635		};
636
637		pinctrl_usbotg: usbotggrp {
638			fsl,pins = <
639				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
640			>;
641		};
642
643		pinctrl_usdhc2: usdhc2grp {
644			fsl,pins = <
645				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
646				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
647				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
648				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
649				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
650				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
651				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
652				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
653				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
654				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
655			>;
656		};
657
658		pinctrl_usdhc3: usdhc3grp {
659			fsl,pins = <
660				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
661				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
662				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
663				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
664				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
665				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
666				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
667				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
668				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
669				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
670			>;
671		};
672
673		pinctrl_usdhc4: usdhc4grp {
674			fsl,pins = <
675				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
676				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
677				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
678				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
679				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
680				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
681				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
682				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
683				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
684				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
685			>;
686		};
687
688		pinctrl_wdog: wdoggrp {
689			fsl,pins = <
690				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
691			>;
692		};
693	};
694
695	gpio_leds {
696		pinctrl_gpio_leds: gpioledsgrp {
697			fsl,pins = <
698				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
699			>;
700		};
701	};
702};
703
704&ldb {
705	status = "okay";
706
707	lvds-channel@1 {
708		fsl,data-mapping = "spwg";
709		fsl,data-width = <18>;
710		status = "okay";
711
712		port@4 {
713			reg = <4>;
714
715			lvds0_out: endpoint {
716				remote-endpoint = <&panel_in>;
717			};
718		};
719	};
720};
721
722&pcie {
723	pinctrl-names = "default";
724	pinctrl-0 = <&pinctrl_pcie>;
725	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
726	vpcie-supply = <&reg_pcie>;
727	status = "okay";
728};
729
730&pwm1 {
731	pinctrl-names = "default";
732	pinctrl-0 = <&pinctrl_pwm1>;
733	status = "okay";
734};
735
736&reg_arm {
737       vin-supply = <&sw1a_reg>;
738};
739
740&reg_pu {
741       vin-supply = <&sw1c_reg>;
742};
743
744&reg_soc {
745       vin-supply = <&sw1c_reg>;
746};
747
748&reg_vdd1p1 {
749	vin-supply = <&vgen5_reg>;
750};
751
752&reg_vdd3p0 {
753	vin-supply = <&sw2_reg>;
754};
755
756&reg_vdd2p5 {
757	vin-supply = <&vgen5_reg>;
758};
759
760&snvs_poweroff {
761	status = "okay";
762};
763
764&snvs_pwrkey {
765	status = "okay";
766};
767
768&ssi2 {
769	status = "okay";
770};
771
772&uart1 {
773	pinctrl-names = "default";
774	pinctrl-0 = <&pinctrl_uart1>;
775	status = "okay";
776};
777
778&usbh1 {
779	vbus-supply = <&reg_usb_h1_vbus>;
780	status = "okay";
781};
782
783&usbotg {
784	vbus-supply = <&reg_usb_otg_vbus>;
785	pinctrl-names = "default";
786	pinctrl-0 = <&pinctrl_usbotg>;
787	disable-over-current;
788	status = "okay";
789};
790
791&usdhc2 {
792	pinctrl-names = "default";
793	pinctrl-0 = <&pinctrl_usdhc2>;
794	bus-width = <8>;
795	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
796	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
797	status = "okay";
798};
799
800&usdhc3 {
801	pinctrl-names = "default";
802	pinctrl-0 = <&pinctrl_usdhc3>;
803	bus-width = <8>;
804	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
805	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
806	status = "okay";
807};
808
809&usdhc4 {
810	pinctrl-names = "default";
811	pinctrl-0 = <&pinctrl_usdhc4>;
812	bus-width = <8>;
813	non-removable;
814	no-1-8-v;
815	status = "okay";
816};
817
818&wdog1 {
819	status = "disabled";
820};
821
822&wdog2 {
823	pinctrl-names = "default";
824	pinctrl-0 = <&pinctrl_wdog>;
825	fsl,ext-reset-output;
826	status = "okay";
827};
828