1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/sound/fsl-imx-audmux.h>
8
9/ {
10	/* these are used by bootloader for disabling nodes */
11	aliases {
12		led0 = &led0;
13		led1 = &led1;
14		led2 = &led2;
15		nand = &gpmi;
16		ssi0 = &ssi1;
17		usb0 = &usbh1;
18		usb1 = &usbotg;
19	};
20
21	chosen {
22		bootargs = "console=ttymxc1,115200";
23	};
24
25	backlight {
26		compatible = "pwm-backlight";
27		pwms = <&pwm4 0 5000000>;
28		brightness-levels = <0 4 8 16 32 64 128 255>;
29		default-brightness-level = <7>;
30	};
31
32	leds {
33		compatible = "gpio-leds";
34		pinctrl-names = "default";
35		pinctrl-0 = <&pinctrl_gpio_leds>;
36
37		led0: user1 {
38			label = "user1";
39			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
40			default-state = "on";
41			linux,default-trigger = "heartbeat";
42		};
43
44		led1: user2 {
45			label = "user2";
46			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
47			default-state = "off";
48		};
49
50		led2: user3 {
51			label = "user3";
52			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
53			default-state = "off";
54		};
55	};
56
57	memory@10000000 {
58		device_type = "memory";
59		reg = <0x10000000 0x40000000>;
60	};
61
62	pps {
63		compatible = "pps-gpio";
64		pinctrl-names = "default";
65		pinctrl-0 = <&pinctrl_pps>;
66		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
67		status = "okay";
68	};
69
70	regulators {
71		compatible = "simple-bus";
72		#address-cells = <1>;
73		#size-cells = <0>;
74
75		reg_1p0v: regulator@0 {
76			compatible = "regulator-fixed";
77			reg = <0>;
78			regulator-name = "1P0V";
79			regulator-min-microvolt = <1000000>;
80			regulator-max-microvolt = <1000000>;
81			regulator-always-on;
82		};
83
84		reg_3p3v: regulator@1 {
85			compatible = "regulator-fixed";
86			reg = <1>;
87			regulator-name = "3P3V";
88			regulator-min-microvolt = <3300000>;
89			regulator-max-microvolt = <3300000>;
90			regulator-always-on;
91		};
92
93		reg_usb_h1_vbus: regulator@2 {
94			compatible = "regulator-fixed";
95			reg = <2>;
96			regulator-name = "usb_h1_vbus";
97			regulator-min-microvolt = <5000000>;
98			regulator-max-microvolt = <5000000>;
99			regulator-always-on;
100		};
101
102		reg_usb_otg_vbus: regulator@3 {
103			compatible = "regulator-fixed";
104			reg = <3>;
105			regulator-name = "usb_otg_vbus";
106			regulator-min-microvolt = <5000000>;
107			regulator-max-microvolt = <5000000>;
108			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
109			enable-active-high;
110		};
111	};
112
113	sound-analog {
114		compatible = "fsl,imx6q-ventana-sgtl5000",
115			     "fsl,imx-audio-sgtl5000";
116		model = "sgtl5000-audio";
117		ssi-controller = <&ssi1>;
118		audio-codec = <&sgtl5000>;
119		audio-routing =
120			"MIC_IN", "Mic Jack",
121			"Mic Jack", "Mic Bias",
122			"Headphone Jack", "HP_OUT";
123		mux-int-port = <1>;
124		mux-ext-port = <4>;
125	};
126};
127
128&audmux {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
131	status = "okay";
132
133	ssi2 {
134		fsl,audmux-port = <1>;
135		fsl,port-config = <
136			(IMX_AUDMUX_V2_PTCR_TFSDIR |
137			IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
138			IMX_AUDMUX_V2_PTCR_TCLKDIR |
139			IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
140			IMX_AUDMUX_V2_PTCR_SYN)
141			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
142		>;
143	};
144
145	aud5 {
146		fsl,audmux-port = <4>;
147		fsl,port-config = <
148			IMX_AUDMUX_V2_PTCR_SYN
149			IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
150	};
151};
152
153&can1 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_flexcan1>;
156	status = "okay";
157};
158
159&clks {
160	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
161			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
162	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
163				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
164};
165
166&ecspi2 {
167	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
168	pinctrl-names = "default";
169	pinctrl-0 = <&pinctrl_ecspi2>;
170	status = "okay";
171};
172
173&fec {
174	pinctrl-names = "default";
175	pinctrl-0 = <&pinctrl_enet>;
176	phy-mode = "rgmii-id";
177	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
178	status = "okay";
179};
180
181&gpmi {
182	pinctrl-names = "default";
183	pinctrl-0 = <&pinctrl_gpmi_nand>;
184	status = "okay";
185};
186
187&hdmi {
188	ddc-i2c-bus = <&i2c3>;
189	status = "okay";
190};
191
192&i2c1 {
193	clock-frequency = <100000>;
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_i2c1>;
196	status = "okay";
197
198	eeprom1: eeprom@50 {
199		compatible = "atmel,24c02";
200		reg = <0x50>;
201		pagesize = <16>;
202	};
203
204	eeprom2: eeprom@51 {
205		compatible = "atmel,24c02";
206		reg = <0x51>;
207		pagesize = <16>;
208	};
209
210	eeprom3: eeprom@52 {
211		compatible = "atmel,24c02";
212		reg = <0x52>;
213		pagesize = <16>;
214	};
215
216	eeprom4: eeprom@53 {
217		compatible = "atmel,24c02";
218		reg = <0x53>;
219		pagesize = <16>;
220	};
221
222	gpio: pca9555@23 {
223		compatible = "nxp,pca9555";
224		reg = <0x23>;
225		gpio-controller;
226		#gpio-cells = <2>;
227	};
228
229	rtc: ds1672@68 {
230		compatible = "dallas,ds1672";
231		reg = <0x68>;
232	};
233};
234
235&i2c2 {
236	clock-frequency = <100000>;
237	pinctrl-names = "default";
238	pinctrl-0 = <&pinctrl_i2c2>;
239	status = "okay";
240
241	pmic: pfuze100@8 {
242		compatible = "fsl,pfuze100";
243		reg = <0x08>;
244
245		regulators {
246			sw1a_reg: sw1ab {
247				regulator-min-microvolt = <300000>;
248				regulator-max-microvolt = <1875000>;
249				regulator-boot-on;
250				regulator-always-on;
251				regulator-ramp-delay = <6250>;
252			};
253
254			sw1c_reg: sw1c {
255				regulator-min-microvolt = <300000>;
256				regulator-max-microvolt = <1875000>;
257				regulator-boot-on;
258				regulator-always-on;
259				regulator-ramp-delay = <6250>;
260			};
261
262			sw2_reg: sw2 {
263				regulator-min-microvolt = <800000>;
264				regulator-max-microvolt = <3950000>;
265				regulator-boot-on;
266				regulator-always-on;
267			};
268
269			sw3a_reg: sw3a {
270				regulator-min-microvolt = <400000>;
271				regulator-max-microvolt = <1975000>;
272				regulator-boot-on;
273				regulator-always-on;
274			};
275
276			sw3b_reg: sw3b {
277				regulator-min-microvolt = <400000>;
278				regulator-max-microvolt = <1975000>;
279				regulator-boot-on;
280				regulator-always-on;
281			};
282
283			sw4_reg: sw4 {
284				regulator-min-microvolt = <800000>;
285				regulator-max-microvolt = <3300000>;
286			};
287
288			swbst_reg: swbst {
289				regulator-min-microvolt = <5000000>;
290				regulator-max-microvolt = <5150000>;
291				regulator-boot-on;
292				regulator-always-on;
293			};
294
295			snvs_reg: vsnvs {
296				regulator-min-microvolt = <1000000>;
297				regulator-max-microvolt = <3000000>;
298				regulator-boot-on;
299				regulator-always-on;
300			};
301
302			vref_reg: vrefddr {
303				regulator-boot-on;
304				regulator-always-on;
305			};
306
307			vgen1_reg: vgen1 {
308				regulator-min-microvolt = <800000>;
309				regulator-max-microvolt = <1550000>;
310			};
311
312			vgen2_reg: vgen2 {
313				regulator-min-microvolt = <800000>;
314				regulator-max-microvolt = <1550000>;
315			};
316
317			vgen3_reg: vgen3 {
318				regulator-min-microvolt = <1800000>;
319				regulator-max-microvolt = <3300000>;
320			};
321
322			vgen4_reg: vgen4 {
323				regulator-min-microvolt = <1800000>;
324				regulator-max-microvolt = <3300000>;
325				regulator-always-on;
326			};
327
328			vgen5_reg: vgen5 {
329				regulator-min-microvolt = <1800000>;
330				regulator-max-microvolt = <3300000>;
331				regulator-always-on;
332			};
333
334			vgen6_reg: vgen6 {
335				regulator-min-microvolt = <1800000>;
336				regulator-max-microvolt = <3300000>;
337				regulator-always-on;
338			};
339		};
340	};
341};
342
343&i2c3 {
344	clock-frequency = <100000>;
345	pinctrl-names = "default";
346	pinctrl-0 = <&pinctrl_i2c3>;
347	status = "okay";
348
349	sgtl5000: audio-codec@a {
350		compatible = "fsl,sgtl5000";
351		reg = <0x0a>;
352		clocks = <&clks IMX6QDL_CLK_CKO>;
353		VDDA-supply = <&sw4_reg>;
354		VDDIO-supply = <&reg_3p3v>;
355	};
356
357	touchscreen: egalax_ts@4 {
358		compatible = "eeti,egalax_ts";
359		reg = <0x04>;
360		interrupt-parent = <&gpio7>;
361		interrupts = <12 2>;
362		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
363	};
364};
365
366&ldb {
367	status = "okay";
368
369	lvds-channel@0 {
370		fsl,data-mapping = "spwg";
371		fsl,data-width = <18>;
372		status = "okay";
373
374		display-timings {
375			native-mode = <&timing0>;
376			timing0: hsd100pxn1 {
377				clock-frequency = <65000000>;
378				hactive = <1024>;
379				vactive = <768>;
380				hback-porch = <220>;
381				hfront-porch = <40>;
382				vback-porch = <21>;
383				vfront-porch = <7>;
384				hsync-len = <60>;
385				vsync-len = <10>;
386			};
387		};
388	};
389};
390
391&pcie {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_pcie>;
394	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
395	status = "okay";
396};
397
398&pwm1 {
399	pinctrl-names = "default";
400	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
401	status = "disabled";
402};
403
404&pwm2 {
405	pinctrl-names = "default";
406	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
407	status = "disabled";
408};
409
410&pwm3 {
411	pinctrl-names = "default";
412	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
413	status = "disabled";
414};
415
416&pwm4 {
417	pinctrl-names = "default", "state_dio";
418	pinctrl-0 = <&pinctrl_pwm4_backlight>;
419	pinctrl-1 = <&pinctrl_pwm4_dio>;
420	status = "okay";
421};
422
423&ssi1 {
424	status = "okay";
425};
426
427&ssi2 {
428	status = "okay";
429};
430
431&uart1 {
432	pinctrl-names = "default";
433	pinctrl-0 = <&pinctrl_uart1>;
434	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
435	status = "okay";
436};
437
438&uart2 {
439	pinctrl-names = "default";
440	pinctrl-0 = <&pinctrl_uart2>;
441	status = "okay";
442};
443
444&uart5 {
445	pinctrl-names = "default";
446	pinctrl-0 = <&pinctrl_uart5>;
447	status = "okay";
448};
449
450&usbotg {
451	vbus-supply = <&reg_usb_otg_vbus>;
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_usbotg>;
454	disable-over-current;
455	status = "okay";
456};
457
458&usbh1 {
459	vbus-supply = <&reg_usb_h1_vbus>;
460	status = "okay";
461};
462
463&usdhc3 {
464	pinctrl-names = "default", "state_100mhz", "state_200mhz";
465	pinctrl-0 = <&pinctrl_usdhc3>;
466	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
467	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
468	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
469	vmmc-supply = <&reg_3p3v>;
470	no-1-8-v; /* firmware will remove if board revision supports */
471	status = "okay";
472};
473
474&wdog1 {
475	status = "disabled";
476};
477
478&wdog2 {
479	pinctrl-names = "default";
480	pinctrl-0 = <&pinctrl_wdog>;
481	fsl,ext-reset-output;
482	status = "okay";
483};
484
485&iomuxc {
486	pinctrl_audmux: audmuxgrp {
487		fsl,pins = <
488			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
489			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
490			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
491			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
492			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0 /* AUD4_MCK */
493			MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
494			MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
495			MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
496		>;
497	};
498
499	pinctrl_enet: enetgrp {
500		fsl,pins = <
501			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
502			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
503			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
504			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
505			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
506			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
507			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
508			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
509			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
510			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
511			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
512			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
513			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
514			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
515			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
516			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
517		>;
518	};
519
520	pinctrl_ecspi2: escpi2grp {
521		fsl,pins = <
522			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
523			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
524			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
525			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
526		>;
527	};
528
529	pinctrl_flexcan1: flexcan1grp {
530		fsl,pins = <
531			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
532			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
533			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0 /* CAN_STBY */
534		>;
535	};
536
537	pinctrl_gpio_leds: gpioledsgrp {
538		fsl,pins = <
539			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
540			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
541			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
542		>;
543	};
544
545	pinctrl_gpmi_nand: gpminandgrp {
546		fsl,pins = <
547			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
548			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
549			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
550			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
551			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
552			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
553			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
554			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
555			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
556			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
557			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
558			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
559			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
560			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
561			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
562		>;
563	};
564
565	pinctrl_i2c1: i2c1grp {
566		fsl,pins = <
567			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
568			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
569		>;
570	};
571
572	pinctrl_i2c2: i2c2grp {
573		fsl,pins = <
574			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
575			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
576		>;
577	};
578
579	pinctrl_i2c3: i2c3grp {
580		fsl,pins = <
581			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
582			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
583		>;
584	};
585
586	pinctrl_pcie: pciegrp {
587		fsl,pins = <
588			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0 /* PCIE IRQ */
589			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE RST */
590		>;
591	};
592
593	pinctrl_pps: ppsgrp {
594		fsl,pins = <
595			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
596		>;
597	};
598
599	pinctrl_pwm1: pwm1grp {
600		fsl,pins = <
601			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
602		>;
603	};
604
605	pinctrl_pwm2: pwm2grp {
606		fsl,pins = <
607			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
608		>;
609	};
610
611	pinctrl_pwm3: pwm3grp {
612		fsl,pins = <
613			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
614		>;
615	};
616
617	pinctrl_pwm4_backlight: pwm4grpbacklight {
618		fsl,pins = <
619			/* LVDS_PWM J6.5 */
620			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
621		>;
622	};
623
624	pinctrl_pwm4_dio: pwm4grpdio {
625		fsl,pins = <
626			/* DIO3 J16.4 */
627			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
628		>;
629	};
630
631	pinctrl_uart1: uart1grp {
632		fsl,pins = <
633			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
634			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
635			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
636		>;
637	};
638
639	pinctrl_uart2: uart2grp {
640		fsl,pins = <
641			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
642			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
643		>;
644	};
645
646	pinctrl_uart5: uart5grp {
647		fsl,pins = <
648			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
649			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
650		>;
651	};
652
653	pinctrl_usbotg: usbotggrp {
654		fsl,pins = <
655			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
656			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
657		>;
658	};
659
660	pinctrl_usdhc3: usdhc3grp {
661		fsl,pins = <
662			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
663			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
664			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
665			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
666			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
667			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
668			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
669			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
670		>;
671	};
672
673	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
674		fsl,pins = <
675			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
676			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
677			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
678			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
679			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
680			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
681			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
682			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
683		>;
684	};
685
686	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
687		fsl,pins = <
688			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
689			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
690			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
691			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
692			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
693			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
694			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
695			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
696		>;
697	};
698
699	pinctrl_wdog: wdoggrp {
700		fsl,pins = <
701			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
702		>;
703	};
704};
705