1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #ifndef _I40E_TYPE_H_
5 #define _I40E_TYPE_H_
6
7 #include "i40e_status.h"
8 #include "i40e_osdep.h"
9 #include "i40e_register.h"
10 #include "i40e_adminq.h"
11 #include "i40e_hmc.h"
12 #include "i40e_lan_hmc.h"
13 #include "i40e_devids.h"
14
15 /* I40E_MASK is a macro used on 32 bit registers */
16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
17
18 #define I40E_MAX_VSI_QP 16
19 #define I40E_MAX_VF_VSI 4
20 #define I40E_MAX_CHAINED_RX_BUFFERS 5
21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
22
23 /* Max default timeout in ms, */
24 #define I40E_MAX_NVM_TIMEOUT 18000
25
26 /* Max timeout in ms for the phy to respond */
27 #define I40E_MAX_PHY_TIMEOUT 500
28
29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
30 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
31
32 /* forward declaration */
33 struct i40e_hw;
34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
35
36 /* Data type manipulation macros. */
37
38 #define I40E_DESC_UNUSED(R) \
39 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
40 (R)->next_to_clean - (R)->next_to_use - 1)
41
42 /* bitfields for Tx queue mapping in QTX_CTL */
43 #define I40E_QTX_CTL_VF_QUEUE 0x0
44 #define I40E_QTX_CTL_VM_QUEUE 0x1
45 #define I40E_QTX_CTL_PF_QUEUE 0x2
46
47 /* debug masks - set these bits in hw->debug_mask to control output */
48 enum i40e_debug_mask {
49 I40E_DEBUG_INIT = 0x00000001,
50 I40E_DEBUG_RELEASE = 0x00000002,
51
52 I40E_DEBUG_LINK = 0x00000010,
53 I40E_DEBUG_PHY = 0x00000020,
54 I40E_DEBUG_HMC = 0x00000040,
55 I40E_DEBUG_NVM = 0x00000080,
56 I40E_DEBUG_LAN = 0x00000100,
57 I40E_DEBUG_FLOW = 0x00000200,
58 I40E_DEBUG_DCB = 0x00000400,
59 I40E_DEBUG_DIAG = 0x00000800,
60 I40E_DEBUG_FD = 0x00001000,
61 I40E_DEBUG_PACKAGE = 0x00002000,
62 I40E_DEBUG_IWARP = 0x00F00000,
63 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
64 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
65 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
66 I40E_DEBUG_AQ_COMMAND = 0x06000000,
67 I40E_DEBUG_AQ = 0x0F000000,
68
69 I40E_DEBUG_USER = 0xF0000000,
70
71 I40E_DEBUG_ALL = 0xFFFFFFFF
72 };
73
74 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
75 I40E_GLGEN_MSCA_STCODE_SHIFT)
76 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
77 I40E_GLGEN_MSCA_OPCODE_SHIFT)
78 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
79 I40E_GLGEN_MSCA_OPCODE_SHIFT)
80
81 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
82 I40E_GLGEN_MSCA_STCODE_SHIFT)
83 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
84 I40E_GLGEN_MSCA_OPCODE_SHIFT)
85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
86 I40E_GLGEN_MSCA_OPCODE_SHIFT)
87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
88 I40E_GLGEN_MSCA_OPCODE_SHIFT)
89 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
90 I40E_GLGEN_MSCA_OPCODE_SHIFT)
91
92 #define I40E_PHY_COM_REG_PAGE 0x1E
93 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
94 #define I40E_PHY_LED_MANUAL_ON 0x100
95 #define I40E_PHY_LED_PROV_REG_1 0xC430
96 #define I40E_PHY_LED_MODE_MASK 0xFFFF
97 #define I40E_PHY_LED_MODE_ORIG 0x80000000
98
99 /* These are structs for managing the hardware information and the operations.
100 * The structures of function pointers are filled out at init time when we
101 * know for sure exactly which hardware we're working with. This gives us the
102 * flexibility of using the same main driver code but adapting to slightly
103 * different hardware needs as new parts are developed. For this architecture,
104 * the Firmware and AdminQ are intended to insulate the driver from most of the
105 * future changes, but these structures will also do part of the job.
106 */
107 enum i40e_mac_type {
108 I40E_MAC_UNKNOWN = 0,
109 I40E_MAC_XL710,
110 I40E_MAC_VF,
111 I40E_MAC_X722,
112 I40E_MAC_X722_VF,
113 I40E_MAC_GENERIC,
114 };
115
116 enum i40e_media_type {
117 I40E_MEDIA_TYPE_UNKNOWN = 0,
118 I40E_MEDIA_TYPE_FIBER,
119 I40E_MEDIA_TYPE_BASET,
120 I40E_MEDIA_TYPE_BACKPLANE,
121 I40E_MEDIA_TYPE_CX4,
122 I40E_MEDIA_TYPE_DA,
123 I40E_MEDIA_TYPE_VIRTUAL
124 };
125
126 enum i40e_fc_mode {
127 I40E_FC_NONE = 0,
128 I40E_FC_RX_PAUSE,
129 I40E_FC_TX_PAUSE,
130 I40E_FC_FULL,
131 I40E_FC_PFC,
132 I40E_FC_DEFAULT
133 };
134
135 enum i40e_set_fc_aq_failures {
136 I40E_SET_FC_AQ_FAIL_NONE = 0,
137 I40E_SET_FC_AQ_FAIL_GET = 1,
138 I40E_SET_FC_AQ_FAIL_SET = 2,
139 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
140 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
141 };
142
143 enum i40e_vsi_type {
144 I40E_VSI_MAIN = 0,
145 I40E_VSI_VMDQ1 = 1,
146 I40E_VSI_VMDQ2 = 2,
147 I40E_VSI_CTRL = 3,
148 I40E_VSI_FCOE = 4,
149 I40E_VSI_MIRROR = 5,
150 I40E_VSI_SRIOV = 6,
151 I40E_VSI_FDIR = 7,
152 I40E_VSI_IWARP = 8,
153 I40E_VSI_TYPE_UNKNOWN
154 };
155
156 enum i40e_queue_type {
157 I40E_QUEUE_TYPE_RX = 0,
158 I40E_QUEUE_TYPE_TX,
159 I40E_QUEUE_TYPE_PE_CEQ,
160 I40E_QUEUE_TYPE_UNKNOWN
161 };
162
163 struct i40e_link_status {
164 enum i40e_aq_phy_type phy_type;
165 enum i40e_aq_link_speed link_speed;
166 u8 link_info;
167 u8 an_info;
168 u8 req_fec_info;
169 u8 fec_info;
170 u8 ext_info;
171 u8 loopback;
172 /* is Link Status Event notification to SW enabled */
173 bool lse_enable;
174 u16 max_frame_size;
175 bool crc_enable;
176 u8 pacing;
177 u8 requested_speeds;
178 u8 module_type[3];
179 /* 1st byte: module identifier */
180 #define I40E_MODULE_TYPE_SFP 0x03
181 #define I40E_MODULE_TYPE_QSFP 0x0D
182 /* 2nd byte: ethernet compliance codes for 10/40G */
183 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
184 #define I40E_MODULE_TYPE_40G_LR4 0x02
185 #define I40E_MODULE_TYPE_40G_SR4 0x04
186 #define I40E_MODULE_TYPE_40G_CR4 0x08
187 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
188 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
189 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
190 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
191 /* 3rd byte: ethernet compliance codes for 1G */
192 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
193 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
194 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
195 #define I40E_MODULE_TYPE_1000BASE_T 0x08
196 };
197
198 struct i40e_phy_info {
199 struct i40e_link_status link_info;
200 struct i40e_link_status link_info_old;
201 bool get_link_info;
202 enum i40e_media_type media_type;
203 /* all the phy types the NVM is capable of */
204 u64 phy_types;
205 };
206
207 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
208 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
209 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
210 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
211 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
212 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
213 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
214 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
215 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
216 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
217 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
218 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
219 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
220 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
221 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
222 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
223 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
224 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
225 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
226 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
227 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
228 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
229 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
230 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
231 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
232 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
233 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
234 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
235 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
236 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
237 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
238 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
239 * a shift is needed to adjust for this with values larger than 31. The
240 * only affected values are I40E_PHY_TYPE_25GBASE_*.
241 */
242 #define I40E_PHY_TYPE_OFFSET 1
243 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
244 I40E_PHY_TYPE_OFFSET)
245 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
246 I40E_PHY_TYPE_OFFSET)
247 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
248 I40E_PHY_TYPE_OFFSET)
249 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
250 I40E_PHY_TYPE_OFFSET)
251 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
252 I40E_PHY_TYPE_OFFSET)
253 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
254 I40E_PHY_TYPE_OFFSET)
255 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
256 #define I40E_PHY_TYPE_OFFSET2 (-10)
257 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
258 I40E_PHY_TYPE_OFFSET2)
259 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
260 I40E_PHY_TYPE_OFFSET2)
261 #define I40E_HW_CAP_MAX_GPIO 30
262 /* Capabilities of a PF or a VF or the whole device */
263 struct i40e_hw_capabilities {
264 u32 switch_mode;
265 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
266 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
267 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
268
269 /* Cloud filter modes:
270 * Mode1: Filter on L4 port only
271 * Mode2: Filter for non-tunneled traffic
272 * Mode3: Filter for tunnel traffic
273 */
274 #define I40E_CLOUD_FILTER_MODE1 0x6
275 #define I40E_CLOUD_FILTER_MODE2 0x7
276 #define I40E_CLOUD_FILTER_MODE3 0x8
277 #define I40E_SWITCH_MODE_MASK 0xF
278
279 u32 management_mode;
280 u32 mng_protocols_over_mctp;
281 #define I40E_MNG_PROTOCOL_PLDM 0x2
282 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
283 #define I40E_MNG_PROTOCOL_NCSI 0x8
284 u32 npar_enable;
285 u32 os2bmc;
286 u32 valid_functions;
287 bool sr_iov_1_1;
288 bool vmdq;
289 bool evb_802_1_qbg; /* Edge Virtual Bridging */
290 bool evb_802_1_qbh; /* Bridge Port Extension */
291 bool dcb;
292 bool fcoe;
293 bool iscsi; /* Indicates iSCSI enabled */
294 bool flex10_enable;
295 bool flex10_capable;
296 u32 flex10_mode;
297 #define I40E_FLEX10_MODE_UNKNOWN 0x0
298 #define I40E_FLEX10_MODE_DCC 0x1
299 #define I40E_FLEX10_MODE_DCI 0x2
300
301 u32 flex10_status;
302 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
303 #define I40E_FLEX10_STATUS_VC_MODE 0x2
304
305 bool sec_rev_disabled;
306 bool update_disabled;
307 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
308 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
309
310 bool mgmt_cem;
311 bool ieee_1588;
312 bool iwarp;
313 bool fd;
314 u32 fd_filters_guaranteed;
315 u32 fd_filters_best_effort;
316 bool rss;
317 u32 rss_table_size;
318 u32 rss_table_entry_width;
319 bool led[I40E_HW_CAP_MAX_GPIO];
320 bool sdp[I40E_HW_CAP_MAX_GPIO];
321 u32 nvm_image_type;
322 u32 num_flow_director_filters;
323 u32 num_vfs;
324 u32 vf_base_id;
325 u32 num_vsis;
326 u32 num_rx_qp;
327 u32 num_tx_qp;
328 u32 base_queue;
329 u32 num_msix_vectors;
330 u32 num_msix_vectors_vf;
331 u32 led_pin_num;
332 u32 sdp_pin_num;
333 u32 mdio_port_num;
334 u32 mdio_port_mode;
335 u8 rx_buf_chain_len;
336 u32 enabled_tcmap;
337 u32 maxtc;
338 u64 wr_csr_prot;
339 };
340
341 struct i40e_mac_info {
342 enum i40e_mac_type type;
343 u8 addr[ETH_ALEN];
344 u8 perm_addr[ETH_ALEN];
345 u8 san_addr[ETH_ALEN];
346 u8 port_addr[ETH_ALEN];
347 u16 max_fcoeq;
348 };
349
350 enum i40e_aq_resources_ids {
351 I40E_NVM_RESOURCE_ID = 1
352 };
353
354 enum i40e_aq_resource_access_type {
355 I40E_RESOURCE_READ = 1,
356 I40E_RESOURCE_WRITE
357 };
358
359 struct i40e_nvm_info {
360 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
361 u32 timeout; /* [ms] */
362 u16 sr_size; /* Shadow RAM size in words */
363 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
364 u16 version; /* NVM package version */
365 u32 eetrack; /* NVM data version */
366 u32 oem_ver; /* OEM version info */
367 };
368
369 /* definitions used in NVM update support */
370
371 enum i40e_nvmupd_cmd {
372 I40E_NVMUPD_INVALID,
373 I40E_NVMUPD_READ_CON,
374 I40E_NVMUPD_READ_SNT,
375 I40E_NVMUPD_READ_LCB,
376 I40E_NVMUPD_READ_SA,
377 I40E_NVMUPD_WRITE_ERA,
378 I40E_NVMUPD_WRITE_CON,
379 I40E_NVMUPD_WRITE_SNT,
380 I40E_NVMUPD_WRITE_LCB,
381 I40E_NVMUPD_WRITE_SA,
382 I40E_NVMUPD_CSUM_CON,
383 I40E_NVMUPD_CSUM_SA,
384 I40E_NVMUPD_CSUM_LCB,
385 I40E_NVMUPD_STATUS,
386 I40E_NVMUPD_EXEC_AQ,
387 I40E_NVMUPD_GET_AQ_RESULT,
388 I40E_NVMUPD_GET_AQ_EVENT,
389 };
390
391 enum i40e_nvmupd_state {
392 I40E_NVMUPD_STATE_INIT,
393 I40E_NVMUPD_STATE_READING,
394 I40E_NVMUPD_STATE_WRITING,
395 I40E_NVMUPD_STATE_INIT_WAIT,
396 I40E_NVMUPD_STATE_WRITE_WAIT,
397 I40E_NVMUPD_STATE_ERROR
398 };
399
400 /* nvm_access definition and its masks/shifts need to be accessible to
401 * application, core driver, and shared code. Where is the right file?
402 */
403 #define I40E_NVM_READ 0xB
404 #define I40E_NVM_WRITE 0xC
405
406 #define I40E_NVM_MOD_PNT_MASK 0xFF
407
408 #define I40E_NVM_TRANS_SHIFT 8
409 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
410 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
411 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
412 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
413 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
414 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
415 #define I40E_NVM_CON 0x0
416 #define I40E_NVM_SNT 0x1
417 #define I40E_NVM_LCB 0x2
418 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
419 #define I40E_NVM_ERA 0x4
420 #define I40E_NVM_CSUM 0x8
421 #define I40E_NVM_AQE 0xe
422 #define I40E_NVM_EXEC 0xf
423
424 #define I40E_NVM_ADAPT_SHIFT 16
425 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
426
427 #define I40E_NVMUPD_MAX_DATA 4096
428 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
429
430 struct i40e_nvm_access {
431 u32 command;
432 u32 config;
433 u32 offset; /* in bytes */
434 u32 data_size; /* in bytes */
435 u8 data[1];
436 };
437
438 /* (Q)SFP module access definitions */
439 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
440 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
441 #define I40E_MODULE_TYPE_ADDR 0x00
442 #define I40E_MODULE_REVISION_ADDR 0x01
443 #define I40E_MODULE_SFF_8472_COMP 0x5E
444 #define I40E_MODULE_SFF_8472_SWAP 0x5C
445 #define I40E_MODULE_SFF_ADDR_MODE 0x04
446 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40
447 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
448 #define I40E_MODULE_TYPE_QSFP28 0x11
449 #define I40E_MODULE_QSFP_MAX_LEN 640
450
451 /* PCI bus types */
452 enum i40e_bus_type {
453 i40e_bus_type_unknown = 0,
454 i40e_bus_type_pci,
455 i40e_bus_type_pcix,
456 i40e_bus_type_pci_express,
457 i40e_bus_type_reserved
458 };
459
460 /* PCI bus speeds */
461 enum i40e_bus_speed {
462 i40e_bus_speed_unknown = 0,
463 i40e_bus_speed_33 = 33,
464 i40e_bus_speed_66 = 66,
465 i40e_bus_speed_100 = 100,
466 i40e_bus_speed_120 = 120,
467 i40e_bus_speed_133 = 133,
468 i40e_bus_speed_2500 = 2500,
469 i40e_bus_speed_5000 = 5000,
470 i40e_bus_speed_8000 = 8000,
471 i40e_bus_speed_reserved
472 };
473
474 /* PCI bus widths */
475 enum i40e_bus_width {
476 i40e_bus_width_unknown = 0,
477 i40e_bus_width_pcie_x1 = 1,
478 i40e_bus_width_pcie_x2 = 2,
479 i40e_bus_width_pcie_x4 = 4,
480 i40e_bus_width_pcie_x8 = 8,
481 i40e_bus_width_32 = 32,
482 i40e_bus_width_64 = 64,
483 i40e_bus_width_reserved
484 };
485
486 /* Bus parameters */
487 struct i40e_bus_info {
488 enum i40e_bus_speed speed;
489 enum i40e_bus_width width;
490 enum i40e_bus_type type;
491
492 u16 func;
493 u16 device;
494 u16 lan_id;
495 u16 bus_id;
496 };
497
498 /* Flow control (FC) parameters */
499 struct i40e_fc_info {
500 enum i40e_fc_mode current_mode; /* FC mode in effect */
501 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
502 };
503
504 #define I40E_MAX_TRAFFIC_CLASS 8
505 #define I40E_MAX_USER_PRIORITY 8
506 #define I40E_DCBX_MAX_APPS 32
507 #define I40E_LLDPDU_SIZE 1500
508 #define I40E_TLV_STATUS_OPER 0x1
509 #define I40E_TLV_STATUS_SYNC 0x2
510 #define I40E_TLV_STATUS_ERR 0x4
511 #define I40E_CEE_OPER_MAX_APPS 3
512 #define I40E_APP_PROTOID_FCOE 0x8906
513 #define I40E_APP_PROTOID_ISCSI 0x0cbc
514 #define I40E_APP_PROTOID_FIP 0x8914
515 #define I40E_APP_SEL_ETHTYPE 0x1
516 #define I40E_APP_SEL_TCPIP 0x2
517 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
518 #define I40E_CEE_APP_SEL_TCPIP 0x1
519
520 /* CEE or IEEE 802.1Qaz ETS Configuration data */
521 struct i40e_dcb_ets_config {
522 u8 willing;
523 u8 cbs;
524 u8 maxtcs;
525 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
526 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
527 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
528 };
529
530 /* CEE or IEEE 802.1Qaz PFC Configuration data */
531 struct i40e_dcb_pfc_config {
532 u8 willing;
533 u8 mbc;
534 u8 pfccap;
535 u8 pfcenable;
536 };
537
538 /* CEE or IEEE 802.1Qaz Application Priority data */
539 struct i40e_dcb_app_priority_table {
540 u8 priority;
541 u8 selector;
542 u16 protocolid;
543 };
544
545 struct i40e_dcbx_config {
546 u8 dcbx_mode;
547 #define I40E_DCBX_MODE_CEE 0x1
548 #define I40E_DCBX_MODE_IEEE 0x2
549 u8 app_mode;
550 #define I40E_DCBX_APPS_NON_WILLING 0x1
551 u32 numapps;
552 u32 tlv_status; /* CEE mode TLV status */
553 struct i40e_dcb_ets_config etscfg;
554 struct i40e_dcb_ets_config etsrec;
555 struct i40e_dcb_pfc_config pfc;
556 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
557 };
558
559 /* Port hardware description */
560 struct i40e_hw {
561 u8 __iomem *hw_addr;
562 void *back;
563
564 /* subsystem structs */
565 struct i40e_phy_info phy;
566 struct i40e_mac_info mac;
567 struct i40e_bus_info bus;
568 struct i40e_nvm_info nvm;
569 struct i40e_fc_info fc;
570
571 /* pci info */
572 u16 device_id;
573 u16 vendor_id;
574 u16 subsystem_device_id;
575 u16 subsystem_vendor_id;
576 u8 revision_id;
577 u8 port;
578 bool adapter_stopped;
579
580 /* capabilities for entire device and PCI func */
581 struct i40e_hw_capabilities dev_caps;
582 struct i40e_hw_capabilities func_caps;
583
584 /* Flow Director shared filter space */
585 u16 fdir_shared_filter_count;
586
587 /* device profile info */
588 u8 pf_id;
589 u16 main_vsi_seid;
590
591 /* for multi-function MACs */
592 u16 partition_id;
593 u16 num_partitions;
594 u16 num_ports;
595
596 /* Closest numa node to the device */
597 u16 numa_node;
598
599 /* Admin Queue info */
600 struct i40e_adminq_info aq;
601
602 /* state of nvm update process */
603 enum i40e_nvmupd_state nvmupd_state;
604 struct i40e_aq_desc nvm_wb_desc;
605 struct i40e_aq_desc nvm_aq_event_desc;
606 struct i40e_virt_mem nvm_buff;
607 bool nvm_release_on_done;
608 u16 nvm_wait_opcode;
609
610 /* HMC info */
611 struct i40e_hmc_info hmc; /* HMC info struct */
612
613 /* LLDP/DCBX Status */
614 u16 dcbx_status;
615
616 /* DCBX info */
617 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
618 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
619 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
620
621 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
622 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
623 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
624 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
625 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
626 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
627 #define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
628 u64 flags;
629
630 /* Used in set switch config AQ command */
631 u16 switch_tag;
632 u16 first_tag;
633 u16 second_tag;
634
635 /* debug mask */
636 u32 debug_mask;
637 char err_str[16];
638 };
639
i40e_is_vf(struct i40e_hw * hw)640 static inline bool i40e_is_vf(struct i40e_hw *hw)
641 {
642 return (hw->mac.type == I40E_MAC_VF ||
643 hw->mac.type == I40E_MAC_X722_VF);
644 }
645
646 struct i40e_driver_version {
647 u8 major_version;
648 u8 minor_version;
649 u8 build_version;
650 u8 subbuild_version;
651 u8 driver_string[32];
652 };
653
654 /* RX Descriptors */
655 union i40e_16byte_rx_desc {
656 struct {
657 __le64 pkt_addr; /* Packet buffer address */
658 __le64 hdr_addr; /* Header buffer address */
659 } read;
660 struct {
661 struct {
662 struct {
663 union {
664 __le16 mirroring_status;
665 __le16 fcoe_ctx_id;
666 } mirr_fcoe;
667 __le16 l2tag1;
668 } lo_dword;
669 union {
670 __le32 rss; /* RSS Hash */
671 __le32 fd_id; /* Flow director filter id */
672 __le32 fcoe_param; /* FCoE DDP Context id */
673 } hi_dword;
674 } qword0;
675 struct {
676 /* ext status/error/pktype/length */
677 __le64 status_error_len;
678 } qword1;
679 } wb; /* writeback */
680 };
681
682 union i40e_32byte_rx_desc {
683 struct {
684 __le64 pkt_addr; /* Packet buffer address */
685 __le64 hdr_addr; /* Header buffer address */
686 /* bit 0 of hdr_buffer_addr is DD bit */
687 __le64 rsvd1;
688 __le64 rsvd2;
689 } read;
690 struct {
691 struct {
692 struct {
693 union {
694 __le16 mirroring_status;
695 __le16 fcoe_ctx_id;
696 } mirr_fcoe;
697 __le16 l2tag1;
698 } lo_dword;
699 union {
700 __le32 rss; /* RSS Hash */
701 __le32 fcoe_param; /* FCoE DDP Context id */
702 /* Flow director filter id in case of
703 * Programming status desc WB
704 */
705 __le32 fd_id;
706 } hi_dword;
707 } qword0;
708 struct {
709 /* status/error/pktype/length */
710 __le64 status_error_len;
711 } qword1;
712 struct {
713 __le16 ext_status; /* extended status */
714 __le16 rsvd;
715 __le16 l2tag2_1;
716 __le16 l2tag2_2;
717 } qword2;
718 struct {
719 union {
720 __le32 flex_bytes_lo;
721 __le32 pe_status;
722 } lo_dword;
723 union {
724 __le32 flex_bytes_hi;
725 __le32 fd_id;
726 } hi_dword;
727 } qword3;
728 } wb; /* writeback */
729 };
730
731 enum i40e_rx_desc_status_bits {
732 /* Note: These are predefined bit offsets */
733 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
734 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
735 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
736 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
737 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
738 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
739 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
740 /* Note: Bit 8 is reserved in X710 and XL710 */
741 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
742 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
743 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
744 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
745 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
746 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
747 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
748 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
749 * UDP header
750 */
751 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
752 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
753 };
754
755 #define I40E_RXD_QW1_STATUS_SHIFT 0
756 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
757 << I40E_RXD_QW1_STATUS_SHIFT)
758
759 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
760 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
761 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
762
763 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
764 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
765 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
766
767 enum i40e_rx_desc_fltstat_values {
768 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
769 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
770 I40E_RX_DESC_FLTSTAT_RSV = 2,
771 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
772 };
773
774 #define I40E_RXD_QW1_ERROR_SHIFT 19
775 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
776
777 enum i40e_rx_desc_error_bits {
778 /* Note: These are predefined bit offsets */
779 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
780 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
781 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
782 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
783 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
784 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
785 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
786 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
787 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
788 };
789
790 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
791 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
792 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
793 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
794 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
795 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
796 };
797
798 #define I40E_RXD_QW1_PTYPE_SHIFT 30
799 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
800
801 /* Packet type non-ip values */
802 enum i40e_rx_l2_ptype {
803 I40E_RX_PTYPE_L2_RESERVED = 0,
804 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
805 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
806 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
807 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
808 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
809 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
810 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
811 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
812 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
813 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
814 I40E_RX_PTYPE_L2_ARP = 11,
815 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
816 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
817 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
818 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
819 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
820 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
821 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
822 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
823 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
824 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
825 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
826 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
827 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
828 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
829 };
830
831 struct i40e_rx_ptype_decoded {
832 u32 ptype:8;
833 u32 known:1;
834 u32 outer_ip:1;
835 u32 outer_ip_ver:1;
836 u32 outer_frag:1;
837 u32 tunnel_type:3;
838 u32 tunnel_end_prot:2;
839 u32 tunnel_end_frag:1;
840 u32 inner_prot:4;
841 u32 payload_layer:3;
842 };
843
844 enum i40e_rx_ptype_outer_ip {
845 I40E_RX_PTYPE_OUTER_L2 = 0,
846 I40E_RX_PTYPE_OUTER_IP = 1
847 };
848
849 enum i40e_rx_ptype_outer_ip_ver {
850 I40E_RX_PTYPE_OUTER_NONE = 0,
851 I40E_RX_PTYPE_OUTER_IPV4 = 0,
852 I40E_RX_PTYPE_OUTER_IPV6 = 1
853 };
854
855 enum i40e_rx_ptype_outer_fragmented {
856 I40E_RX_PTYPE_NOT_FRAG = 0,
857 I40E_RX_PTYPE_FRAG = 1
858 };
859
860 enum i40e_rx_ptype_tunnel_type {
861 I40E_RX_PTYPE_TUNNEL_NONE = 0,
862 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
863 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
864 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
865 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
866 };
867
868 enum i40e_rx_ptype_tunnel_end_prot {
869 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
870 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
871 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
872 };
873
874 enum i40e_rx_ptype_inner_prot {
875 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
876 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
877 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
878 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
879 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
880 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
881 };
882
883 enum i40e_rx_ptype_payload_layer {
884 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
885 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
886 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
887 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
888 };
889
890 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
891 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
892 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
893
894 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
895 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
896 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
897
898 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
899 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
900
901 enum i40e_rx_desc_ext_status_bits {
902 /* Note: These are predefined bit offsets */
903 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
904 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
905 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
906 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
907 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
908 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
909 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
910 };
911
912 enum i40e_rx_desc_pe_status_bits {
913 /* Note: These are predefined bit offsets */
914 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
915 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
916 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
917 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
918 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
919 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
920 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
921 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
922 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
923 };
924
925 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
926 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
927
928 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
929 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
930 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
931
932 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
933 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
934 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
935
936 enum i40e_rx_prog_status_desc_status_bits {
937 /* Note: These are predefined bit offsets */
938 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
939 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
940 };
941
942 enum i40e_rx_prog_status_desc_prog_id_masks {
943 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
944 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
945 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
946 };
947
948 enum i40e_rx_prog_status_desc_error_bits {
949 /* Note: These are predefined bit offsets */
950 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
951 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
952 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
953 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
954 };
955
956 /* TX Descriptor */
957 struct i40e_tx_desc {
958 __le64 buffer_addr; /* Address of descriptor's data buf */
959 __le64 cmd_type_offset_bsz;
960 };
961
962 #define I40E_TXD_QW1_DTYPE_SHIFT 0
963 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
964
965 enum i40e_tx_desc_dtype_value {
966 I40E_TX_DESC_DTYPE_DATA = 0x0,
967 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
968 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
969 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
970 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
971 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
972 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
973 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
974 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
975 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
976 };
977
978 #define I40E_TXD_QW1_CMD_SHIFT 4
979 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
980
981 enum i40e_tx_desc_cmd_bits {
982 I40E_TX_DESC_CMD_EOP = 0x0001,
983 I40E_TX_DESC_CMD_RS = 0x0002,
984 I40E_TX_DESC_CMD_ICRC = 0x0004,
985 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
986 I40E_TX_DESC_CMD_DUMMY = 0x0010,
987 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
988 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
989 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
990 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
991 I40E_TX_DESC_CMD_FCOET = 0x0080,
992 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
993 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
994 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
995 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
996 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
997 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
998 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
999 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1000 };
1001
1002 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1003 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1004 I40E_TXD_QW1_OFFSET_SHIFT)
1005
1006 enum i40e_tx_desc_length_fields {
1007 /* Note: These are predefined bit offsets */
1008 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1009 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1010 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1011 };
1012
1013 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1014 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1015 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1016
1017 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1018 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1019
1020 /* Context descriptors */
1021 struct i40e_tx_context_desc {
1022 __le32 tunneling_params;
1023 __le16 l2tag2;
1024 __le16 rsvd;
1025 __le64 type_cmd_tso_mss;
1026 };
1027
1028 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1029 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1030
1031 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1032 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1033
1034 enum i40e_tx_ctx_desc_cmd_bits {
1035 I40E_TX_CTX_DESC_TSO = 0x01,
1036 I40E_TX_CTX_DESC_TSYN = 0x02,
1037 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1038 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1039 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1040 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1041 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1042 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1043 I40E_TX_CTX_DESC_SWPE = 0x40
1044 };
1045
1046 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1047 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1048 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1049
1050 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1051 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1052 I40E_TXD_CTX_QW1_MSS_SHIFT)
1053
1054 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1055 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1056
1057 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1058 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1059 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1060
1061 enum i40e_tx_ctx_desc_eipt_offload {
1062 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1063 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1064 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1065 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1066 };
1067
1068 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1069 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1070 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1071
1072 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1073 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1074
1075 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1076 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1077
1078 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1079 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1080 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1081
1082 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1083
1084 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1085 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1086 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1087
1088 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1089 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1090 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1091
1092 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1093 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1094 struct i40e_filter_program_desc {
1095 __le32 qindex_flex_ptype_vsi;
1096 __le32 rsvd;
1097 __le32 dtype_cmd_cntindex;
1098 __le32 fd_id;
1099 };
1100 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1101 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1102 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1103 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1104 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1105 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1106 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1107 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1108 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1109
1110 /* Packet Classifier Types for filters */
1111 enum i40e_filter_pctype {
1112 /* Note: Values 0-28 are reserved for future use.
1113 * Value 29, 30, 32 are not supported on XL710 and X710.
1114 */
1115 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1116 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1117 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1118 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1119 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1120 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1121 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1122 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1123 /* Note: Values 37-38 are reserved for future use.
1124 * Value 39, 40, 42 are not supported on XL710 and X710.
1125 */
1126 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1127 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1128 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1129 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1130 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1131 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1132 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1133 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1134 /* Note: Value 47 is reserved for future use */
1135 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1136 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1137 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1138 /* Note: Values 51-62 are reserved for future use */
1139 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1140 };
1141
1142 enum i40e_filter_program_desc_dest {
1143 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1144 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1145 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1146 };
1147
1148 enum i40e_filter_program_desc_fd_status {
1149 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1150 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1151 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1152 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1153 };
1154
1155 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1156 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1157 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1158
1159 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1160 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1161 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1162
1163 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1165
1166 enum i40e_filter_program_desc_pcmd {
1167 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1168 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1169 };
1170
1171 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1172 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1173
1174 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1175 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1176
1177 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1178 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1179 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1180 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1181
1182 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1183 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1184 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1185
1186 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1187 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1188 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1189
1190 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1191 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1192 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1193
1194 enum i40e_filter_type {
1195 I40E_FLOW_DIRECTOR_FLTR = 0,
1196 I40E_PE_QUAD_HASH_FLTR = 1,
1197 I40E_ETHERTYPE_FLTR,
1198 I40E_FCOE_CTX_FLTR,
1199 I40E_MAC_VLAN_FLTR,
1200 I40E_HASH_FLTR
1201 };
1202
1203 struct i40e_vsi_context {
1204 u16 seid;
1205 u16 uplink_seid;
1206 u16 vsi_number;
1207 u16 vsis_allocated;
1208 u16 vsis_unallocated;
1209 u16 flags;
1210 u8 pf_num;
1211 u8 vf_num;
1212 u8 connection_type;
1213 struct i40e_aqc_vsi_properties_data info;
1214 };
1215
1216 struct i40e_veb_context {
1217 u16 seid;
1218 u16 uplink_seid;
1219 u16 veb_number;
1220 u16 vebs_allocated;
1221 u16 vebs_unallocated;
1222 u16 flags;
1223 struct i40e_aqc_get_veb_parameters_completion info;
1224 };
1225
1226 /* Statistics collected by each port, VSI, VEB, and S-channel */
1227 struct i40e_eth_stats {
1228 u64 rx_bytes; /* gorc */
1229 u64 rx_unicast; /* uprc */
1230 u64 rx_multicast; /* mprc */
1231 u64 rx_broadcast; /* bprc */
1232 u64 rx_discards; /* rdpc */
1233 u64 rx_unknown_protocol; /* rupp */
1234 u64 tx_bytes; /* gotc */
1235 u64 tx_unicast; /* uptc */
1236 u64 tx_multicast; /* mptc */
1237 u64 tx_broadcast; /* bptc */
1238 u64 tx_discards; /* tdpc */
1239 u64 tx_errors; /* tepc */
1240 };
1241
1242 /* Statistics collected per VEB per TC */
1243 struct i40e_veb_tc_stats {
1244 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1245 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1246 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1247 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1248 };
1249
1250 /* Statistics collected by the MAC */
1251 struct i40e_hw_port_stats {
1252 /* eth stats collected by the port */
1253 struct i40e_eth_stats eth;
1254
1255 /* additional port specific stats */
1256 u64 tx_dropped_link_down; /* tdold */
1257 u64 crc_errors; /* crcerrs */
1258 u64 illegal_bytes; /* illerrc */
1259 u64 error_bytes; /* errbc */
1260 u64 mac_local_faults; /* mlfc */
1261 u64 mac_remote_faults; /* mrfc */
1262 u64 rx_length_errors; /* rlec */
1263 u64 link_xon_rx; /* lxonrxc */
1264 u64 link_xoff_rx; /* lxoffrxc */
1265 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1266 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1267 u64 link_xon_tx; /* lxontxc */
1268 u64 link_xoff_tx; /* lxofftxc */
1269 u64 priority_xon_tx[8]; /* pxontxc[8] */
1270 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1271 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1272 u64 rx_size_64; /* prc64 */
1273 u64 rx_size_127; /* prc127 */
1274 u64 rx_size_255; /* prc255 */
1275 u64 rx_size_511; /* prc511 */
1276 u64 rx_size_1023; /* prc1023 */
1277 u64 rx_size_1522; /* prc1522 */
1278 u64 rx_size_big; /* prc9522 */
1279 u64 rx_undersize; /* ruc */
1280 u64 rx_fragments; /* rfc */
1281 u64 rx_oversize; /* roc */
1282 u64 rx_jabber; /* rjc */
1283 u64 tx_size_64; /* ptc64 */
1284 u64 tx_size_127; /* ptc127 */
1285 u64 tx_size_255; /* ptc255 */
1286 u64 tx_size_511; /* ptc511 */
1287 u64 tx_size_1023; /* ptc1023 */
1288 u64 tx_size_1522; /* ptc1522 */
1289 u64 tx_size_big; /* ptc9522 */
1290 u64 mac_short_packet_dropped; /* mspdc */
1291 u64 checksum_error; /* xec */
1292 /* flow director stats */
1293 u64 fd_atr_match;
1294 u64 fd_sb_match;
1295 u64 fd_atr_tunnel_match;
1296 u32 fd_atr_status;
1297 u32 fd_sb_status;
1298 /* EEE LPI */
1299 u32 tx_lpi_status;
1300 u32 rx_lpi_status;
1301 u64 tx_lpi_count; /* etlpic */
1302 u64 rx_lpi_count; /* erlpic */
1303 };
1304
1305 /* Checksum and Shadow RAM pointers */
1306 #define I40E_SR_NVM_CONTROL_WORD 0x00
1307 #define I40E_EMP_MODULE_PTR 0x0F
1308 #define I40E_SR_EMP_MODULE_PTR 0x48
1309 #define I40E_SR_PBA_FLAGS 0x15
1310 #define I40E_SR_PBA_BLOCK_PTR 0x16
1311 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1312 #define I40E_NVM_OEM_VER_OFF 0x83
1313 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1314 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1315 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1316 #define I40E_SR_NVM_EETRACK_LO 0x2D
1317 #define I40E_SR_NVM_EETRACK_HI 0x2E
1318 #define I40E_SR_VPD_PTR 0x2F
1319 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1320 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1321 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1322
1323 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1324 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1325 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1326 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1327 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1328 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
1329 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
1330 #define I40E_PTR_TYPE BIT(15)
1331 #define I40E_SR_OCP_CFG_WORD0 0x2B
1332 #define I40E_SR_OCP_ENABLED BIT(15)
1333
1334 /* Shadow RAM related */
1335 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1336 #define I40E_SR_WORDS_IN_1KB 512
1337 /* Checksum should be calculated such that after adding all the words,
1338 * including the checksum word itself, the sum should be 0xBABA.
1339 */
1340 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1341
1342 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1343
1344 enum i40e_switch_element_types {
1345 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1346 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1347 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1348 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1349 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1350 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1351 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1352 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1353 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1354 };
1355
1356 /* Supported EtherType filters */
1357 enum i40e_ether_type_index {
1358 I40E_ETHER_TYPE_1588 = 0,
1359 I40E_ETHER_TYPE_FIP = 1,
1360 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1361 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1362 I40E_ETHER_TYPE_LLDP = 4,
1363 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1364 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1365 I40E_ETHER_TYPE_QCN_CNM = 7,
1366 I40E_ETHER_TYPE_8021X = 8,
1367 I40E_ETHER_TYPE_ARP = 9,
1368 I40E_ETHER_TYPE_RSV1 = 10,
1369 I40E_ETHER_TYPE_RSV2 = 11,
1370 };
1371
1372 /* Filter context base size is 1K */
1373 #define I40E_HASH_FILTER_BASE_SIZE 1024
1374 /* Supported Hash filter values */
1375 enum i40e_hash_filter_size {
1376 I40E_HASH_FILTER_SIZE_1K = 0,
1377 I40E_HASH_FILTER_SIZE_2K = 1,
1378 I40E_HASH_FILTER_SIZE_4K = 2,
1379 I40E_HASH_FILTER_SIZE_8K = 3,
1380 I40E_HASH_FILTER_SIZE_16K = 4,
1381 I40E_HASH_FILTER_SIZE_32K = 5,
1382 I40E_HASH_FILTER_SIZE_64K = 6,
1383 I40E_HASH_FILTER_SIZE_128K = 7,
1384 I40E_HASH_FILTER_SIZE_256K = 8,
1385 I40E_HASH_FILTER_SIZE_512K = 9,
1386 I40E_HASH_FILTER_SIZE_1M = 10,
1387 };
1388
1389 /* DMA context base size is 0.5K */
1390 #define I40E_DMA_CNTX_BASE_SIZE 512
1391 /* Supported DMA context values */
1392 enum i40e_dma_cntx_size {
1393 I40E_DMA_CNTX_SIZE_512 = 0,
1394 I40E_DMA_CNTX_SIZE_1K = 1,
1395 I40E_DMA_CNTX_SIZE_2K = 2,
1396 I40E_DMA_CNTX_SIZE_4K = 3,
1397 I40E_DMA_CNTX_SIZE_8K = 4,
1398 I40E_DMA_CNTX_SIZE_16K = 5,
1399 I40E_DMA_CNTX_SIZE_32K = 6,
1400 I40E_DMA_CNTX_SIZE_64K = 7,
1401 I40E_DMA_CNTX_SIZE_128K = 8,
1402 I40E_DMA_CNTX_SIZE_256K = 9,
1403 };
1404
1405 /* Supported Hash look up table (LUT) sizes */
1406 enum i40e_hash_lut_size {
1407 I40E_HASH_LUT_SIZE_128 = 0,
1408 I40E_HASH_LUT_SIZE_512 = 1,
1409 };
1410
1411 /* Structure to hold a per PF filter control settings */
1412 struct i40e_filter_control_settings {
1413 /* number of PE Quad Hash filter buckets */
1414 enum i40e_hash_filter_size pe_filt_num;
1415 /* number of PE Quad Hash contexts */
1416 enum i40e_dma_cntx_size pe_cntx_num;
1417 /* number of FCoE filter buckets */
1418 enum i40e_hash_filter_size fcoe_filt_num;
1419 /* number of FCoE DDP contexts */
1420 enum i40e_dma_cntx_size fcoe_cntx_num;
1421 /* size of the Hash LUT */
1422 enum i40e_hash_lut_size hash_lut_size;
1423 /* enable FDIR filters for PF and its VFs */
1424 bool enable_fdir;
1425 /* enable Ethertype filters for PF and its VFs */
1426 bool enable_ethtype;
1427 /* enable MAC/VLAN filters for PF and its VFs */
1428 bool enable_macvlan;
1429 };
1430
1431 /* Structure to hold device level control filter counts */
1432 struct i40e_control_filter_stats {
1433 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1434 u16 etype_used; /* Used perfect EtherType filters */
1435 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1436 u16 etype_free; /* Un-used perfect EtherType filters */
1437 };
1438
1439 enum i40e_reset_type {
1440 I40E_RESET_POR = 0,
1441 I40E_RESET_CORER = 1,
1442 I40E_RESET_GLOBR = 2,
1443 I40E_RESET_EMPR = 3,
1444 };
1445
1446 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1447 #define I40E_NVM_LLDP_CFG_PTR 0x06
1448 #define I40E_SR_LLDP_CFG_PTR 0x31
1449 struct i40e_lldp_variables {
1450 u16 length;
1451 u16 adminstatus;
1452 u16 msgfasttx;
1453 u16 msgtxinterval;
1454 u16 txparams;
1455 u16 timers;
1456 u16 crc8;
1457 };
1458
1459 /* Offsets into Alternate Ram */
1460 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1461 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1462 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1463 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1464 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1465 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1466
1467 /* Alternate Ram Bandwidth Masks */
1468 #define I40E_ALT_BW_VALUE_MASK 0xFF
1469 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1470 #define I40E_ALT_BW_VALID_MASK 0x80000000
1471
1472 /* RSS Hash Table Size */
1473 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1474
1475 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1476 #define I40E_L3_SRC_SHIFT 47
1477 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1478 #define I40E_L3_V6_SRC_SHIFT 43
1479 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1480 #define I40E_L3_DST_SHIFT 35
1481 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1482 #define I40E_L3_V6_DST_SHIFT 35
1483 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1484 #define I40E_L4_SRC_SHIFT 34
1485 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1486 #define I40E_L4_DST_SHIFT 33
1487 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1488 #define I40E_VERIFY_TAG_SHIFT 31
1489 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1490
1491 #define I40E_FLEX_50_SHIFT 13
1492 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1493 #define I40E_FLEX_51_SHIFT 12
1494 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1495 #define I40E_FLEX_52_SHIFT 11
1496 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1497 #define I40E_FLEX_53_SHIFT 10
1498 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1499 #define I40E_FLEX_54_SHIFT 9
1500 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1501 #define I40E_FLEX_55_SHIFT 8
1502 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1503 #define I40E_FLEX_56_SHIFT 7
1504 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1505 #define I40E_FLEX_57_SHIFT 6
1506 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1507
1508 /* Version format for Dynamic Device Personalization(DDP) */
1509 struct i40e_ddp_version {
1510 u8 major;
1511 u8 minor;
1512 u8 update;
1513 u8 draft;
1514 };
1515
1516 #define I40E_DDP_NAME_SIZE 32
1517
1518 /* Package header */
1519 struct i40e_package_header {
1520 struct i40e_ddp_version version;
1521 u32 segment_count;
1522 u32 segment_offset[1];
1523 };
1524
1525 /* Generic segment header */
1526 struct i40e_generic_seg_header {
1527 #define SEGMENT_TYPE_METADATA 0x00000001
1528 #define SEGMENT_TYPE_NOTES 0x00000002
1529 #define SEGMENT_TYPE_I40E 0x00000011
1530 #define SEGMENT_TYPE_X722 0x00000012
1531 u32 type;
1532 struct i40e_ddp_version version;
1533 u32 size;
1534 char name[I40E_DDP_NAME_SIZE];
1535 };
1536
1537 struct i40e_metadata_segment {
1538 struct i40e_generic_seg_header header;
1539 struct i40e_ddp_version version;
1540 #define I40E_DDP_TRACKID_RDONLY 0
1541 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1542 u32 track_id;
1543 char name[I40E_DDP_NAME_SIZE];
1544 };
1545
1546 struct i40e_device_id_entry {
1547 u32 vendor_dev_id;
1548 u32 sub_vendor_dev_id;
1549 };
1550
1551 struct i40e_profile_segment {
1552 struct i40e_generic_seg_header header;
1553 struct i40e_ddp_version version;
1554 char name[I40E_DDP_NAME_SIZE];
1555 u32 device_table_count;
1556 struct i40e_device_id_entry device_table[1];
1557 };
1558
1559 struct i40e_section_table {
1560 u32 section_count;
1561 u32 section_offset[1];
1562 };
1563
1564 struct i40e_profile_section_header {
1565 u16 tbl_size;
1566 u16 data_end;
1567 struct {
1568 #define SECTION_TYPE_INFO 0x00000010
1569 #define SECTION_TYPE_MMIO 0x00000800
1570 #define SECTION_TYPE_RB_MMIO 0x00001800
1571 #define SECTION_TYPE_AQ 0x00000801
1572 #define SECTION_TYPE_RB_AQ 0x00001801
1573 #define SECTION_TYPE_NOTE 0x80000000
1574 #define SECTION_TYPE_NAME 0x80000001
1575 #define SECTION_TYPE_PROTO 0x80000002
1576 #define SECTION_TYPE_PCTYPE 0x80000003
1577 #define SECTION_TYPE_PTYPE 0x80000004
1578 u32 type;
1579 u32 offset;
1580 u32 size;
1581 } section;
1582 };
1583
1584 struct i40e_profile_tlv_section_record {
1585 u8 rtype;
1586 u8 type;
1587 u16 len;
1588 u8 data[12];
1589 };
1590
1591 /* Generic AQ section in proflie */
1592 struct i40e_profile_aq_section {
1593 u16 opcode;
1594 u16 flags;
1595 u8 param[16];
1596 u16 datalen;
1597 u8 data[1];
1598 };
1599
1600 struct i40e_profile_info {
1601 u32 track_id;
1602 struct i40e_ddp_version version;
1603 u8 op;
1604 #define I40E_DDP_ADD_TRACKID 0x01
1605 #define I40E_DDP_REMOVE_TRACKID 0x02
1606 u8 reserved[7];
1607 u8 name[I40E_DDP_NAME_SIZE];
1608 };
1609 #endif /* _I40E_TYPE_H_ */
1610
