1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 /* File hw_atl_llh_internal.h: Preprocessor definitions 11 * for Atlantic registers. 12 */ 13 14 #ifndef HW_ATL_LLH_INTERNAL_H 15 #define HW_ATL_LLH_INTERNAL_H 16 17 /* global microprocessor semaphore definitions 18 * base address: 0x000003a0 19 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 20 */ 21 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 22 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 23 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 24 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 25 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 26 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 27 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 28 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 29 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 30 31 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 32 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 33 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 34 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 35 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 36 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 37 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 38 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 39 40 /* preprocessor definitions for msm rx errors counter register */ 41 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 42 43 /* preprocessor definitions for msm rx unicast frames counter register */ 44 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 45 46 /* preprocessor definitions for msm rx multicast frames counter register */ 47 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 48 49 /* preprocessor definitions for msm rx broadcast frames counter register */ 50 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 51 52 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 53 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 54 55 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 56 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 57 58 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 59 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 60 61 /* preprocessor definitions for rx dma statistics counter 7 */ 62 #define HW_ATL_RX_DMA_STAT_COUNTER7_ADR 0x00006818u 63 64 /* preprocessor definitions for msm tx unicast frames counter register */ 65 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 66 67 /* preprocessor definitions for msm tx multicast frames counter register */ 68 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 69 70 /* preprocessor definitions for global mif identification */ 71 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 72 73 /* register address for bitfield iamr_lsw[1f:0] */ 74 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 75 /* register address for bitfield rx dma drop packet counter [1f:0] */ 76 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 77 78 /* register address for bitfield imcr_lsw[1f:0] */ 79 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 80 /* register address for bitfield imsr_lsw[1f:0] */ 81 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 82 /* register address for bitfield itr_reg_res_dsbl */ 83 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 84 /* bitmask for bitfield itr_reg_res_dsbl */ 85 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 86 /* lower bit position of bitfield itr_reg_res_dsbl */ 87 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 88 /* register address for bitfield iscr_lsw[1f:0] */ 89 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 90 /* register address for bitfield isr_lsw[1f:0] */ 91 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000 92 /* register address for bitfield itr_reset */ 93 #define HW_ATL_ITR_RES_ADR 0x00002300 94 /* bitmask for bitfield itr_reset */ 95 #define HW_ATL_ITR_RES_MSK 0x80000000 96 /* lower bit position of bitfield itr_reset */ 97 #define HW_ATL_ITR_RES_SHIFT 31 98 /* register address for bitfield dca{d}_cpuid[7:0] */ 99 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 100 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 101 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 102 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 103 #define HW_ATL_RDM_DCADCPUID_SHIFT 0 104 /* register address for bitfield dca_en */ 105 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 106 107 /* rx dca_en bitfield definitions 108 * preprocessor definitions for the bitfield "dca_en". 109 * port="pif_rdm_dca_en_i" 110 */ 111 112 /* register address for bitfield dca_en */ 113 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 114 /* bitmask for bitfield dca_en */ 115 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000 116 /* inverted bitmask for bitfield dca_en */ 117 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 118 /* lower bit position of bitfield dca_en */ 119 #define HW_ATL_RDM_DCA_EN_SHIFT 31 120 /* width of bitfield dca_en */ 121 #define HW_ATL_RDM_DCA_EN_WIDTH 1 122 /* default value of bitfield dca_en */ 123 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 124 125 /* rx dca_mode[3:0] bitfield definitions 126 * preprocessor definitions for the bitfield "dca_mode[3:0]". 127 * port="pif_rdm_dca_mode_i[3:0]" 128 */ 129 130 /* register address for bitfield dca_mode[3:0] */ 131 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 132 /* bitmask for bitfield dca_mode[3:0] */ 133 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 134 /* inverted bitmask for bitfield dca_mode[3:0] */ 135 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 136 /* lower bit position of bitfield dca_mode[3:0] */ 137 #define HW_ATL_RDM_DCA_MODE_SHIFT 0 138 /* width of bitfield dca_mode[3:0] */ 139 #define HW_ATL_RDM_DCA_MODE_WIDTH 4 140 /* default value of bitfield dca_mode[3:0] */ 141 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 142 143 /* rx desc{d}_data_size[4:0] bitfield definitions 144 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 145 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 146 * port="pif_rdm_desc0_data_size_i[4:0]" 147 */ 148 149 /* register address for bitfield desc{d}_data_size[4:0] */ 150 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 151 (0x00005b18 + (descriptor) * 0x20) 152 /* bitmask for bitfield desc{d}_data_size[4:0] */ 153 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 154 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 155 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 156 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 157 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 158 /* width of bitfield desc{d}_data_size[4:0] */ 159 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 160 /* default value of bitfield desc{d}_data_size[4:0] */ 161 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 162 163 /* rx dca{d}_desc_en bitfield definitions 164 * preprocessor definitions for the bitfield "dca{d}_desc_en". 165 * parameter: dca {d} | stride size 0x4 | range [0, 31] 166 * port="pif_rdm_dca_desc_en_i[0]" 167 */ 168 169 /* register address for bitfield dca{d}_desc_en */ 170 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 171 /* bitmask for bitfield dca{d}_desc_en */ 172 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 173 /* inverted bitmask for bitfield dca{d}_desc_en */ 174 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 175 /* lower bit position of bitfield dca{d}_desc_en */ 176 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 177 /* width of bitfield dca{d}_desc_en */ 178 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 179 /* default value of bitfield dca{d}_desc_en */ 180 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 181 182 /* rx desc{d}_en bitfield definitions 183 * preprocessor definitions for the bitfield "desc{d}_en". 184 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 185 * port="pif_rdm_desc_en_i[0]" 186 */ 187 188 /* register address for bitfield desc{d}_en */ 189 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 190 /* bitmask for bitfield desc{d}_en */ 191 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000 192 /* inverted bitmask for bitfield desc{d}_en */ 193 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 194 /* lower bit position of bitfield desc{d}_en */ 195 #define HW_ATL_RDM_DESCDEN_SHIFT 31 196 /* width of bitfield desc{d}_en */ 197 #define HW_ATL_RDM_DESCDEN_WIDTH 1 198 /* default value of bitfield desc{d}_en */ 199 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 200 201 /* rx desc{d}_hdr_size[4:0] bitfield definitions 202 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 203 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 204 * port="pif_rdm_desc0_hdr_size_i[4:0]" 205 */ 206 207 /* register address for bitfield desc{d}_hdr_size[4:0] */ 208 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 209 (0x00005b18 + (descriptor) * 0x20) 210 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 211 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 212 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 213 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 214 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 215 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 216 /* width of bitfield desc{d}_hdr_size[4:0] */ 217 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 218 /* default value of bitfield desc{d}_hdr_size[4:0] */ 219 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 220 221 /* rx desc{d}_hdr_split bitfield definitions 222 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 223 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 224 * port="pif_rdm_desc_hdr_split_i[0]" 225 */ 226 227 /* register address for bitfield desc{d}_hdr_split */ 228 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 229 (0x00005b08 + (descriptor) * 0x20) 230 /* bitmask for bitfield desc{d}_hdr_split */ 231 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 232 /* inverted bitmask for bitfield desc{d}_hdr_split */ 233 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 234 /* lower bit position of bitfield desc{d}_hdr_split */ 235 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 236 /* width of bitfield desc{d}_hdr_split */ 237 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 238 /* default value of bitfield desc{d}_hdr_split */ 239 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 240 241 /* rx desc{d}_hd[c:0] bitfield definitions 242 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 243 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 244 * port="rdm_pif_desc0_hd_o[12:0]" 245 */ 246 247 /* register address for bitfield desc{d}_hd[c:0] */ 248 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 249 /* bitmask for bitfield desc{d}_hd[c:0] */ 250 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 251 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 252 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 253 /* lower bit position of bitfield desc{d}_hd[c:0] */ 254 #define HW_ATL_RDM_DESCDHD_SHIFT 0 255 /* width of bitfield desc{d}_hd[c:0] */ 256 #define HW_ATL_RDM_DESCDHD_WIDTH 13 257 258 /* rx desc{d}_len[9:0] bitfield definitions 259 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 260 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 261 * port="pif_rdm_desc0_len_i[9:0]" 262 */ 263 264 /* register address for bitfield desc{d}_len[9:0] */ 265 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 266 /* bitmask for bitfield desc{d}_len[9:0] */ 267 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 268 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 269 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 270 /* lower bit position of bitfield desc{d}_len[9:0] */ 271 #define HW_ATL_RDM_DESCDLEN_SHIFT 3 272 /* width of bitfield desc{d}_len[9:0] */ 273 #define HW_ATL_RDM_DESCDLEN_WIDTH 10 274 /* default value of bitfield desc{d}_len[9:0] */ 275 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 276 277 /* rx desc{d}_reset bitfield definitions 278 * preprocessor definitions for the bitfield "desc{d}_reset". 279 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 280 * port="pif_rdm_q_pf_res_i[0]" 281 */ 282 283 /* register address for bitfield desc{d}_reset */ 284 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 285 /* bitmask for bitfield desc{d}_reset */ 286 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 287 /* inverted bitmask for bitfield desc{d}_reset */ 288 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 289 /* lower bit position of bitfield desc{d}_reset */ 290 #define HW_ATL_RDM_DESCDRESET_SHIFT 25 291 /* width of bitfield desc{d}_reset */ 292 #define HW_ATL_RDM_DESCDRESET_WIDTH 1 293 /* default value of bitfield desc{d}_reset */ 294 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 295 296 /* rx int_desc_wrb_en bitfield definitions 297 * preprocessor definitions for the bitfield "int_desc_wrb_en". 298 * port="pif_rdm_int_desc_wrb_en_i" 299 */ 300 301 /* register address for bitfield int_desc_wrb_en */ 302 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 303 /* bitmask for bitfield int_desc_wrb_en */ 304 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 305 /* inverted bitmask for bitfield int_desc_wrb_en */ 306 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 307 /* lower bit position of bitfield int_desc_wrb_en */ 308 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 309 /* width of bitfield int_desc_wrb_en */ 310 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 311 /* default value of bitfield int_desc_wrb_en */ 312 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 313 314 /* rx dca{d}_hdr_en bitfield definitions 315 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 316 * parameter: dca {d} | stride size 0x4 | range [0, 31] 317 * port="pif_rdm_dca_hdr_en_i[0]" 318 */ 319 320 /* register address for bitfield dca{d}_hdr_en */ 321 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 322 /* bitmask for bitfield dca{d}_hdr_en */ 323 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 324 /* inverted bitmask for bitfield dca{d}_hdr_en */ 325 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 326 /* lower bit position of bitfield dca{d}_hdr_en */ 327 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 328 /* width of bitfield dca{d}_hdr_en */ 329 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 330 /* default value of bitfield dca{d}_hdr_en */ 331 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 332 333 /* rx dca{d}_pay_en bitfield definitions 334 * preprocessor definitions for the bitfield "dca{d}_pay_en". 335 * parameter: dca {d} | stride size 0x4 | range [0, 31] 336 * port="pif_rdm_dca_pay_en_i[0]" 337 */ 338 339 /* register address for bitfield dca{d}_pay_en */ 340 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 341 /* bitmask for bitfield dca{d}_pay_en */ 342 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 343 /* inverted bitmask for bitfield dca{d}_pay_en */ 344 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 345 /* lower bit position of bitfield dca{d}_pay_en */ 346 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 347 /* width of bitfield dca{d}_pay_en */ 348 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 349 /* default value of bitfield dca{d}_pay_en */ 350 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 351 352 /* RX rdm_int_rim_en Bitfield Definitions 353 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 354 * PORT="pif_rdm_int_rim_en_i" 355 */ 356 357 /* Register address for bitfield rdm_int_rim_en */ 358 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 359 /* Bitmask for bitfield rdm_int_rim_en */ 360 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 361 /* Inverted bitmask for bitfield rdm_int_rim_en */ 362 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 363 /* Lower bit position of bitfield rdm_int_rim_en */ 364 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 365 /* Width of bitfield rdm_int_rim_en */ 366 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 367 /* Default value of bitfield rdm_int_rim_en */ 368 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 369 370 /* general interrupt mapping register definitions 371 * preprocessor definitions for general interrupt mapping register 372 * base address: 0x00002180 373 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 374 */ 375 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 376 377 /* general interrupt status register definitions 378 * preprocessor definitions for general interrupt status register 379 * address: 0x000021A0 380 */ 381 382 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 383 384 /* interrupt global control register definitions 385 * preprocessor definitions for interrupt global control register 386 * address: 0x00002300 387 */ 388 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 389 390 /* interrupt throttle register definitions 391 * preprocessor definitions for interrupt throttle register 392 * base address: 0x00002800 393 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 394 */ 395 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 396 397 /* rx dma descriptor base address lsw definitions 398 * preprocessor definitions for rx dma descriptor base address lsw 399 * base address: 0x00005b00 400 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 401 */ 402 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 403 (0x00005b00u + (descriptor) * 0x20) 404 405 /* rx dma descriptor base address msw definitions 406 * preprocessor definitions for rx dma descriptor base address msw 407 * base address: 0x00005b04 408 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 409 */ 410 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 411 (0x00005b04u + (descriptor) * 0x20) 412 413 /* rx dma descriptor status register definitions 414 * preprocessor definitions for rx dma descriptor status register 415 * base address: 0x00005b14 416 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 417 */ 418 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 419 (0x00005b14u + (descriptor) * 0x20) 420 421 /* rx dma descriptor tail pointer register definitions 422 * preprocessor definitions for rx dma descriptor tail pointer register 423 * base address: 0x00005b10 424 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 425 */ 426 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 427 (0x00005b10u + (descriptor) * 0x20) 428 429 /* rx interrupt moderation control register definitions 430 * Preprocessor definitions for RX Interrupt Moderation Control Register 431 * Base Address: 0x00005A40 432 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 433 */ 434 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 435 436 /* rx filter multicast filter mask register definitions 437 * preprocessor definitions for rx filter multicast filter mask register 438 * address: 0x00005270 439 */ 440 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 441 442 /* rx filter multicast filter register definitions 443 * preprocessor definitions for rx filter multicast filter register 444 * base address: 0x00005250 445 * parameter: filter {f} | stride size 0x4 | range [0, 7] 446 */ 447 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 448 449 /* RX Filter RSS Control Register 1 Definitions 450 * Preprocessor definitions for RX Filter RSS Control Register 1 451 * Address: 0x000054C0 452 */ 453 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 454 455 /* RX Filter Control Register 2 Definitions 456 * Preprocessor definitions for RX Filter Control Register 2 457 * Address: 0x00005104 458 */ 459 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 460 461 /* tx tx dma debug control [1f:0] bitfield definitions 462 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 463 * port="pif_tdm_debug_cntl_i[31:0]" 464 */ 465 466 /* register address for bitfield tx dma debug control [1f:0] */ 467 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 468 /* bitmask for bitfield tx dma debug control [1f:0] */ 469 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 470 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 471 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 472 /* lower bit position of bitfield tx dma debug control [1f:0] */ 473 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 474 /* width of bitfield tx dma debug control [1f:0] */ 475 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 476 /* default value of bitfield tx dma debug control [1f:0] */ 477 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 478 479 /* tx dma descriptor base address lsw definitions 480 * preprocessor definitions for tx dma descriptor base address lsw 481 * base address: 0x00007c00 482 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 483 */ 484 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 485 (0x00007c00u + (descriptor) * 0x40) 486 487 /* tx dma descriptor tail pointer register definitions 488 * preprocessor definitions for tx dma descriptor tail pointer register 489 * base address: 0x00007c10 490 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 491 */ 492 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 493 (0x00007c10u + (descriptor) * 0x40) 494 495 /* rx dma_sys_loopback bitfield definitions 496 * preprocessor definitions for the bitfield "dma_sys_loopback". 497 * port="pif_rpb_dma_sys_lbk_i" 498 */ 499 500 /* register address for bitfield dma_sys_loopback */ 501 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 502 /* bitmask for bitfield dma_sys_loopback */ 503 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 504 /* inverted bitmask for bitfield dma_sys_loopback */ 505 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 506 /* lower bit position of bitfield dma_sys_loopback */ 507 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 508 /* width of bitfield dma_sys_loopback */ 509 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 510 /* default value of bitfield dma_sys_loopback */ 511 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 512 513 /* rx rx_tc_mode bitfield definitions 514 * preprocessor definitions for the bitfield "rx_tc_mode". 515 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 516 */ 517 518 /* register address for bitfield rx_tc_mode */ 519 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 520 /* bitmask for bitfield rx_tc_mode */ 521 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 522 /* inverted bitmask for bitfield rx_tc_mode */ 523 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 524 /* lower bit position of bitfield rx_tc_mode */ 525 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 526 /* width of bitfield rx_tc_mode */ 527 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 528 /* default value of bitfield rx_tc_mode */ 529 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 530 531 /* rx rx_buf_en bitfield definitions 532 * preprocessor definitions for the bitfield "rx_buf_en". 533 * port="pif_rpb_rx_buf_en_i" 534 */ 535 536 /* register address for bitfield rx_buf_en */ 537 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 538 /* bitmask for bitfield rx_buf_en */ 539 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 540 /* inverted bitmask for bitfield rx_buf_en */ 541 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 542 /* lower bit position of bitfield rx_buf_en */ 543 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 544 /* width of bitfield rx_buf_en */ 545 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 546 /* default value of bitfield rx_buf_en */ 547 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 548 549 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 550 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 551 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 552 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 553 */ 554 555 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 556 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 557 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 558 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 559 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 560 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 561 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 562 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 563 /* width of bitfield rx{b}_hi_thresh[d:0] */ 564 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 565 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 566 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 567 568 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 569 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 570 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 571 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 572 */ 573 574 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 575 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 576 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 577 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 578 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 579 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 580 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 581 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 582 /* width of bitfield rx{b}_lo_thresh[d:0] */ 583 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 584 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 585 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 586 587 /* rx rx_fc_mode[1:0] bitfield definitions 588 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 589 * port="pif_rpb_rx_fc_mode_i[1:0]" 590 */ 591 592 /* register address for bitfield rx_fc_mode[1:0] */ 593 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 594 /* bitmask for bitfield rx_fc_mode[1:0] */ 595 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 596 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 597 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 598 /* lower bit position of bitfield rx_fc_mode[1:0] */ 599 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 600 /* width of bitfield rx_fc_mode[1:0] */ 601 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 602 /* default value of bitfield rx_fc_mode[1:0] */ 603 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 604 605 /* rx rx{b}_buf_size[8:0] bitfield definitions 606 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 607 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 608 * port="pif_rpb_rx0_buf_size_i[8:0]" 609 */ 610 611 /* register address for bitfield rx{b}_buf_size[8:0] */ 612 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 613 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 614 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 615 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 616 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 617 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 618 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 619 /* width of bitfield rx{b}_buf_size[8:0] */ 620 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 621 /* default value of bitfield rx{b}_buf_size[8:0] */ 622 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 623 624 /* rx rx{b}_xoff_en bitfield definitions 625 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 626 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 627 * port="pif_rpb_rx_xoff_en_i[0]" 628 */ 629 630 /* register address for bitfield rx{b}_xoff_en */ 631 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 632 /* bitmask for bitfield rx{b}_xoff_en */ 633 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 634 /* inverted bitmask for bitfield rx{b}_xoff_en */ 635 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 636 /* lower bit position of bitfield rx{b}_xoff_en */ 637 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 638 /* width of bitfield rx{b}_xoff_en */ 639 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 640 /* default value of bitfield rx{b}_xoff_en */ 641 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 642 643 /* rx l2_bc_thresh[f:0] bitfield definitions 644 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 645 * port="pif_rpf_l2_bc_thresh_i[15:0]" 646 */ 647 648 /* register address for bitfield l2_bc_thresh[f:0] */ 649 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 650 /* bitmask for bitfield l2_bc_thresh[f:0] */ 651 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 652 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 653 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 654 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 655 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16 656 /* width of bitfield l2_bc_thresh[f:0] */ 657 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16 658 /* default value of bitfield l2_bc_thresh[f:0] */ 659 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 660 661 /* rx l2_bc_en bitfield definitions 662 * preprocessor definitions for the bitfield "l2_bc_en". 663 * port="pif_rpf_l2_bc_en_i" 664 */ 665 666 /* register address for bitfield l2_bc_en */ 667 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100 668 /* bitmask for bitfield l2_bc_en */ 669 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001 670 /* inverted bitmask for bitfield l2_bc_en */ 671 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 672 /* lower bit position of bitfield l2_bc_en */ 673 #define HW_ATL_RPFL2BC_EN_SHIFT 0 674 /* width of bitfield l2_bc_en */ 675 #define HW_ATL_RPFL2BC_EN_WIDTH 1 676 /* default value of bitfield l2_bc_en */ 677 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 678 679 /* rx l2_bc_act[2:0] bitfield definitions 680 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 681 * port="pif_rpf_l2_bc_act_i[2:0]" 682 */ 683 684 /* register address for bitfield l2_bc_act[2:0] */ 685 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 686 /* bitmask for bitfield l2_bc_act[2:0] */ 687 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 688 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 689 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 690 /* lower bit position of bitfield l2_bc_act[2:0] */ 691 #define HW_ATL_RPFL2BC_ACT_SHIFT 12 692 /* width of bitfield l2_bc_act[2:0] */ 693 #define HW_ATL_RPFL2BC_ACT_WIDTH 3 694 /* default value of bitfield l2_bc_act[2:0] */ 695 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 696 697 /* rx l2_mc_en{f} bitfield definitions 698 * preprocessor definitions for the bitfield "l2_mc_en{f}". 699 * parameter: filter {f} | stride size 0x4 | range [0, 7] 700 * port="pif_rpf_l2_mc_en_i[0]" 701 */ 702 703 /* register address for bitfield l2_mc_en{f} */ 704 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 705 /* bitmask for bitfield l2_mc_en{f} */ 706 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 707 /* inverted bitmask for bitfield l2_mc_en{f} */ 708 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 709 /* lower bit position of bitfield l2_mc_en{f} */ 710 #define HW_ATL_RPFL2MC_ENF_SHIFT 31 711 /* width of bitfield l2_mc_en{f} */ 712 #define HW_ATL_RPFL2MC_ENF_WIDTH 1 713 /* default value of bitfield l2_mc_en{f} */ 714 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 715 716 /* rx l2_promis_mode bitfield definitions 717 * preprocessor definitions for the bitfield "l2_promis_mode". 718 * port="pif_rpf_l2_promis_mode_i" 719 */ 720 721 /* register address for bitfield l2_promis_mode */ 722 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 723 /* bitmask for bitfield l2_promis_mode */ 724 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 725 /* inverted bitmask for bitfield l2_promis_mode */ 726 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 727 /* lower bit position of bitfield l2_promis_mode */ 728 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 729 /* width of bitfield l2_promis_mode */ 730 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 731 /* default value of bitfield l2_promis_mode */ 732 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 733 734 /* rx l2_uc_act{f}[2:0] bitfield definitions 735 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 736 * parameter: filter {f} | stride size 0x8 | range [0, 37] 737 * port="pif_rpf_l2_uc_act0_i[2:0]" 738 */ 739 740 /* register address for bitfield l2_uc_act{f}[2:0] */ 741 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 742 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 743 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 744 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 745 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 746 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 747 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16 748 /* width of bitfield l2_uc_act{f}[2:0] */ 749 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3 750 /* default value of bitfield l2_uc_act{f}[2:0] */ 751 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 752 753 /* rx l2_uc_en{f} bitfield definitions 754 * preprocessor definitions for the bitfield "l2_uc_en{f}". 755 * parameter: filter {f} | stride size 0x8 | range [0, 37] 756 * port="pif_rpf_l2_uc_en_i[0]" 757 */ 758 759 /* register address for bitfield l2_uc_en{f} */ 760 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 761 /* bitmask for bitfield l2_uc_en{f} */ 762 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 763 /* inverted bitmask for bitfield l2_uc_en{f} */ 764 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 765 /* lower bit position of bitfield l2_uc_en{f} */ 766 #define HW_ATL_RPFL2UC_ENF_SHIFT 31 767 /* width of bitfield l2_uc_en{f} */ 768 #define HW_ATL_RPFL2UC_ENF_WIDTH 1 769 /* default value of bitfield l2_uc_en{f} */ 770 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 771 772 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 773 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 774 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 775 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 776 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 777 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 778 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 779 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 780 781 /* rx l2_mc_accept_all bitfield definitions 782 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 783 * PORT="pif_rpf_l2_mc_all_accept_i" 784 */ 785 786 /* Register address for bitfield l2_mc_accept_all */ 787 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 788 /* Bitmask for bitfield l2_mc_accept_all */ 789 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 790 /* Inverted bitmask for bitfield l2_mc_accept_all */ 791 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 792 /* Lower bit position of bitfield l2_mc_accept_all */ 793 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 794 /* Width of bitfield l2_mc_accept_all */ 795 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 796 /* Default value of bitfield l2_mc_accept_all */ 797 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 798 799 /* width of bitfield rx_tc_up{t}[2:0] */ 800 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 801 /* default value of bitfield rx_tc_up{t}[2:0] */ 802 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 803 804 /* rx rss_key_addr[4:0] bitfield definitions 805 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 806 * port="pif_rpf_rss_key_addr_i[4:0]" 807 */ 808 809 /* register address for bitfield rss_key_addr[4:0] */ 810 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 811 /* bitmask for bitfield rss_key_addr[4:0] */ 812 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 813 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 814 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 815 /* lower bit position of bitfield rss_key_addr[4:0] */ 816 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 817 /* width of bitfield rss_key_addr[4:0] */ 818 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 819 /* default value of bitfield rss_key_addr[4:0] */ 820 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 821 822 /* rx rss_key_wr_data[1f:0] bitfield definitions 823 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 824 * port="pif_rpf_rss_key_wr_data_i[31:0]" 825 */ 826 827 /* register address for bitfield rss_key_wr_data[1f:0] */ 828 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 829 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 830 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 831 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 832 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 833 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 834 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 835 /* width of bitfield rss_key_wr_data[1f:0] */ 836 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 837 /* default value of bitfield rss_key_wr_data[1f:0] */ 838 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 839 840 /* rx rss_key_wr_en_i bitfield definitions 841 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 842 * port="pif_rpf_rss_key_wr_en_i" 843 */ 844 845 /* register address for bitfield rss_key_wr_en_i */ 846 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 847 /* bitmask for bitfield rss_key_wr_en_i */ 848 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 849 /* inverted bitmask for bitfield rss_key_wr_en_i */ 850 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 851 /* lower bit position of bitfield rss_key_wr_en_i */ 852 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 853 /* width of bitfield rss_key_wr_en_i */ 854 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 855 /* default value of bitfield rss_key_wr_en_i */ 856 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 857 858 /* rx rss_redir_addr[3:0] bitfield definitions 859 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 860 * port="pif_rpf_rss_redir_addr_i[3:0]" 861 */ 862 863 /* register address for bitfield rss_redir_addr[3:0] */ 864 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 865 /* bitmask for bitfield rss_redir_addr[3:0] */ 866 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 867 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 868 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 869 /* lower bit position of bitfield rss_redir_addr[3:0] */ 870 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 871 /* width of bitfield rss_redir_addr[3:0] */ 872 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 873 /* default value of bitfield rss_redir_addr[3:0] */ 874 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 875 876 /* rx rss_redir_wr_data[f:0] bitfield definitions 877 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 878 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 879 */ 880 881 /* register address for bitfield rss_redir_wr_data[f:0] */ 882 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 883 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 884 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 885 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 886 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 887 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 888 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 889 /* width of bitfield rss_redir_wr_data[f:0] */ 890 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 891 /* default value of bitfield rss_redir_wr_data[f:0] */ 892 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 893 894 /* rx rss_redir_wr_en_i bitfield definitions 895 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 896 * port="pif_rpf_rss_redir_wr_en_i" 897 */ 898 899 /* register address for bitfield rss_redir_wr_en_i */ 900 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 901 /* bitmask for bitfield rss_redir_wr_en_i */ 902 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 903 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 904 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 905 /* lower bit position of bitfield rss_redir_wr_en_i */ 906 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 907 /* width of bitfield rss_redir_wr_en_i */ 908 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 909 /* default value of bitfield rss_redir_wr_en_i */ 910 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 911 912 /* rx tpo_rpf_sys_loopback bitfield definitions 913 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 914 * port="pif_rpf_tpo_pkt_sys_lbk_i" 915 */ 916 917 /* register address for bitfield tpo_rpf_sys_loopback */ 918 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 919 /* bitmask for bitfield tpo_rpf_sys_loopback */ 920 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 921 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 922 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 923 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 924 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 925 /* width of bitfield tpo_rpf_sys_loopback */ 926 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 927 /* default value of bitfield tpo_rpf_sys_loopback */ 928 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 929 930 /* rx vl_inner_tpid[f:0] bitfield definitions 931 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 932 * port="pif_rpf_vl_inner_tpid_i[15:0]" 933 */ 934 935 /* register address for bitfield vl_inner_tpid[f:0] */ 936 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 937 /* bitmask for bitfield vl_inner_tpid[f:0] */ 938 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 939 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 940 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 941 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 942 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 943 /* width of bitfield vl_inner_tpid[f:0] */ 944 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 945 /* default value of bitfield vl_inner_tpid[f:0] */ 946 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 947 948 /* rx vl_outer_tpid[f:0] bitfield definitions 949 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 950 * port="pif_rpf_vl_outer_tpid_i[15:0]" 951 */ 952 953 /* register address for bitfield vl_outer_tpid[f:0] */ 954 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 955 /* bitmask for bitfield vl_outer_tpid[f:0] */ 956 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 957 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 958 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 959 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 960 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 961 /* width of bitfield vl_outer_tpid[f:0] */ 962 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 963 /* default value of bitfield vl_outer_tpid[f:0] */ 964 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 965 966 /* rx vl_promis_mode bitfield definitions 967 * preprocessor definitions for the bitfield "vl_promis_mode". 968 * port="pif_rpf_vl_promis_mode_i" 969 */ 970 971 /* register address for bitfield vl_promis_mode */ 972 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 973 /* bitmask for bitfield vl_promis_mode */ 974 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 975 /* inverted bitmask for bitfield vl_promis_mode */ 976 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 977 /* lower bit position of bitfield vl_promis_mode */ 978 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 979 /* width of bitfield vl_promis_mode */ 980 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 981 /* default value of bitfield vl_promis_mode */ 982 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 983 984 /* RX vl_accept_untagged_mode Bitfield Definitions 985 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 986 * PORT="pif_rpf_vl_accept_untagged_i" 987 */ 988 989 /* Register address for bitfield vl_accept_untagged_mode */ 990 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 991 /* Bitmask for bitfield vl_accept_untagged_mode */ 992 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 993 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 994 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 995 /* Lower bit position of bitfield vl_accept_untagged_mode */ 996 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 997 /* Width of bitfield vl_accept_untagged_mode */ 998 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 999 /* Default value of bitfield vl_accept_untagged_mode */ 1000 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 1001 1002 /* rX vl_untagged_act[2:0] Bitfield Definitions 1003 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1004 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 1005 */ 1006 1007 /* Register address for bitfield vl_untagged_act[2:0] */ 1008 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1009 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1010 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1011 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1012 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1013 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1014 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1015 /* Width of bitfield vl_untagged_act[2:0] */ 1016 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1017 /* Default value of bitfield vl_untagged_act[2:0] */ 1018 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1019 1020 /* RX vl_en{F} Bitfield Definitions 1021 * Preprocessor definitions for the bitfield "vl_en{F}". 1022 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1023 * PORT="pif_rpf_vl_en_i[0]" 1024 */ 1025 1026 /* Register address for bitfield vl_en{F} */ 1027 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1028 /* Bitmask for bitfield vl_en{F} */ 1029 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1030 /* Inverted bitmask for bitfield vl_en{F} */ 1031 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1032 /* Lower bit position of bitfield vl_en{F} */ 1033 #define HW_ATL_RPF_VL_EN_F_SHIFT 31 1034 /* Width of bitfield vl_en{F} */ 1035 #define HW_ATL_RPF_VL_EN_F_WIDTH 1 1036 /* Default value of bitfield vl_en{F} */ 1037 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1038 1039 /* RX vl_act{F}[2:0] Bitfield Definitions 1040 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1041 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1042 * PORT="pif_rpf_vl_act0_i[2:0]" 1043 */ 1044 1045 /* Register address for bitfield vl_act{F}[2:0] */ 1046 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1047 /* Bitmask for bitfield vl_act{F}[2:0] */ 1048 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1049 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1050 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1051 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1052 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1053 /* Width of bitfield vl_act{F}[2:0] */ 1054 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1055 /* Default value of bitfield vl_act{F}[2:0] */ 1056 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1057 1058 /* RX vl_id{F}[B:0] Bitfield Definitions 1059 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1060 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1061 * PORT="pif_rpf_vl_id0_i[11:0]" 1062 */ 1063 1064 /* Register address for bitfield vl_id{F}[B:0] */ 1065 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1066 /* Bitmask for bitfield vl_id{F}[B:0] */ 1067 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1068 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1069 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1070 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1071 #define HW_ATL_RPF_VL_ID_F_SHIFT 0 1072 /* Width of bitfield vl_id{F}[B:0] */ 1073 #define HW_ATL_RPF_VL_ID_F_WIDTH 12 1074 /* Default value of bitfield vl_id{F}[B:0] */ 1075 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1076 1077 /* RX et_en{F} Bitfield Definitions 1078 * Preprocessor definitions for the bitfield "et_en{F}". 1079 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1080 * PORT="pif_rpf_et_en_i[0]" 1081 */ 1082 1083 /* Register address for bitfield et_en{F} */ 1084 #define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4) 1085 /* Bitmask for bitfield et_en{F} */ 1086 #define HW_ATL_RPF_ET_EN_F_MSK 0x80000000 1087 /* Inverted bitmask for bitfield et_en{F} */ 1088 #define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF 1089 /* Lower bit position of bitfield et_en{F} */ 1090 #define HW_ATL_RPF_ET_EN_F_SHIFT 31 1091 /* Width of bitfield et_en{F} */ 1092 #define HW_ATL_RPF_ET_EN_F_WIDTH 1 1093 /* Default value of bitfield et_en{F} */ 1094 #define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0 1095 1096 /* rx et_en{f} bitfield definitions 1097 * preprocessor definitions for the bitfield "et_en{f}". 1098 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1099 * port="pif_rpf_et_en_i[0]" 1100 */ 1101 1102 /* register address for bitfield et_en{f} */ 1103 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1104 /* bitmask for bitfield et_en{f} */ 1105 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1106 /* inverted bitmask for bitfield et_en{f} */ 1107 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1108 /* lower bit position of bitfield et_en{f} */ 1109 #define HW_ATL_RPF_ET_ENF_SHIFT 31 1110 /* width of bitfield et_en{f} */ 1111 #define HW_ATL_RPF_ET_ENF_WIDTH 1 1112 /* default value of bitfield et_en{f} */ 1113 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1114 1115 /* rx et_up{f}_en bitfield definitions 1116 * preprocessor definitions for the bitfield "et_up{f}_en". 1117 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1118 * port="pif_rpf_et_up_en_i[0]" 1119 */ 1120 1121 /* register address for bitfield et_up{f}_en */ 1122 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1123 /* bitmask for bitfield et_up{f}_en */ 1124 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1125 /* inverted bitmask for bitfield et_up{f}_en */ 1126 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1127 /* lower bit position of bitfield et_up{f}_en */ 1128 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1129 /* width of bitfield et_up{f}_en */ 1130 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1131 /* default value of bitfield et_up{f}_en */ 1132 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1133 1134 /* rx et_rxq{f}_en bitfield definitions 1135 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1136 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1137 * port="pif_rpf_et_rxq_en_i[0]" 1138 */ 1139 1140 /* register address for bitfield et_rxq{f}_en */ 1141 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1142 /* bitmask for bitfield et_rxq{f}_en */ 1143 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1144 /* inverted bitmask for bitfield et_rxq{f}_en */ 1145 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1146 /* lower bit position of bitfield et_rxq{f}_en */ 1147 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1148 /* width of bitfield et_rxq{f}_en */ 1149 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1150 /* default value of bitfield et_rxq{f}_en */ 1151 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1152 1153 /* rx et_up{f}[2:0] bitfield definitions 1154 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1155 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1156 * port="pif_rpf_et_up0_i[2:0]" 1157 */ 1158 1159 /* register address for bitfield et_up{f}[2:0] */ 1160 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1161 /* bitmask for bitfield et_up{f}[2:0] */ 1162 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1163 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1164 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1165 /* lower bit position of bitfield et_up{f}[2:0] */ 1166 #define HW_ATL_RPF_ET_UPF_SHIFT 26 1167 /* width of bitfield et_up{f}[2:0] */ 1168 #define HW_ATL_RPF_ET_UPF_WIDTH 3 1169 /* default value of bitfield et_up{f}[2:0] */ 1170 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1171 1172 /* rx et_rxq{f}[4:0] bitfield definitions 1173 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1174 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1175 * port="pif_rpf_et_rxq0_i[4:0]" 1176 */ 1177 1178 /* register address for bitfield et_rxq{f}[4:0] */ 1179 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1180 /* bitmask for bitfield et_rxq{f}[4:0] */ 1181 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1182 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1183 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1184 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1185 #define HW_ATL_RPF_ET_RXQF_SHIFT 20 1186 /* width of bitfield et_rxq{f}[4:0] */ 1187 #define HW_ATL_RPF_ET_RXQF_WIDTH 5 1188 /* default value of bitfield et_rxq{f}[4:0] */ 1189 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1190 1191 /* rx et_mng_rxq{f} bitfield definitions 1192 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1193 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1194 * port="pif_rpf_et_mng_rxq_i[0]" 1195 */ 1196 1197 /* register address for bitfield et_mng_rxq{f} */ 1198 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1199 /* bitmask for bitfield et_mng_rxq{f} */ 1200 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1201 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1202 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1203 /* lower bit position of bitfield et_mng_rxq{f} */ 1204 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1205 /* width of bitfield et_mng_rxq{f} */ 1206 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1207 /* default value of bitfield et_mng_rxq{f} */ 1208 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1209 1210 /* rx et_act{f}[2:0] bitfield definitions 1211 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1212 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1213 * port="pif_rpf_et_act0_i[2:0]" 1214 */ 1215 1216 /* register address for bitfield et_act{f}[2:0] */ 1217 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1218 /* bitmask for bitfield et_act{f}[2:0] */ 1219 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1220 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1221 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1222 /* lower bit position of bitfield et_act{f}[2:0] */ 1223 #define HW_ATL_RPF_ET_ACTF_SHIFT 16 1224 /* width of bitfield et_act{f}[2:0] */ 1225 #define HW_ATL_RPF_ET_ACTF_WIDTH 3 1226 /* default value of bitfield et_act{f}[2:0] */ 1227 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1228 1229 /* rx et_val{f}[f:0] bitfield definitions 1230 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1231 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1232 * port="pif_rpf_et_val0_i[15:0]" 1233 */ 1234 1235 /* register address for bitfield et_val{f}[f:0] */ 1236 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1237 /* bitmask for bitfield et_val{f}[f:0] */ 1238 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1239 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1240 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1241 /* lower bit position of bitfield et_val{f}[f:0] */ 1242 #define HW_ATL_RPF_ET_VALF_SHIFT 0 1243 /* width of bitfield et_val{f}[f:0] */ 1244 #define HW_ATL_RPF_ET_VALF_WIDTH 16 1245 /* default value of bitfield et_val{f}[f:0] */ 1246 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1247 1248 /* rx ipv4_chk_en bitfield definitions 1249 * preprocessor definitions for the bitfield "ipv4_chk_en". 1250 * port="pif_rpo_ipv4_chk_en_i" 1251 */ 1252 1253 /* register address for bitfield ipv4_chk_en */ 1254 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1255 /* bitmask for bitfield ipv4_chk_en */ 1256 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1257 /* inverted bitmask for bitfield ipv4_chk_en */ 1258 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1259 /* lower bit position of bitfield ipv4_chk_en */ 1260 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1261 /* width of bitfield ipv4_chk_en */ 1262 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1263 /* default value of bitfield ipv4_chk_en */ 1264 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1265 1266 /* rx desc{d}_vl_strip bitfield definitions 1267 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1268 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1269 * port="pif_rpo_desc_vl_strip_i[0]" 1270 */ 1271 1272 /* register address for bitfield desc{d}_vl_strip */ 1273 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1274 (0x00005b08 + (descriptor) * 0x20) 1275 /* bitmask for bitfield desc{d}_vl_strip */ 1276 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1277 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1278 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1279 /* lower bit position of bitfield desc{d}_vl_strip */ 1280 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1281 /* width of bitfield desc{d}_vl_strip */ 1282 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1283 /* default value of bitfield desc{d}_vl_strip */ 1284 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1285 1286 /* rx l4_chk_en bitfield definitions 1287 * preprocessor definitions for the bitfield "l4_chk_en". 1288 * port="pif_rpo_l4_chk_en_i" 1289 */ 1290 1291 /* register address for bitfield l4_chk_en */ 1292 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1293 /* bitmask for bitfield l4_chk_en */ 1294 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1295 /* inverted bitmask for bitfield l4_chk_en */ 1296 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1297 /* lower bit position of bitfield l4_chk_en */ 1298 #define HW_ATL_RPOL4CHK_EN_SHIFT 0 1299 /* width of bitfield l4_chk_en */ 1300 #define HW_ATL_RPOL4CHK_EN_WIDTH 1 1301 /* default value of bitfield l4_chk_en */ 1302 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1303 1304 /* rx reg_res_dsbl bitfield definitions 1305 * preprocessor definitions for the bitfield "reg_res_dsbl". 1306 * port="pif_rx_reg_res_dsbl_i" 1307 */ 1308 1309 /* register address for bitfield reg_res_dsbl */ 1310 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1311 /* bitmask for bitfield reg_res_dsbl */ 1312 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1313 /* inverted bitmask for bitfield reg_res_dsbl */ 1314 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1315 /* lower bit position of bitfield reg_res_dsbl */ 1316 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1317 /* width of bitfield reg_res_dsbl */ 1318 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1319 /* default value of bitfield reg_res_dsbl */ 1320 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1321 1322 /* tx dca{d}_cpuid[7:0] bitfield definitions 1323 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1324 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1325 * port="pif_tdm_dca0_cpuid_i[7:0]" 1326 */ 1327 1328 /* register address for bitfield dca{d}_cpuid[7:0] */ 1329 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1330 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1331 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1332 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1333 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1334 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1335 #define HW_ATL_TDM_DCADCPUID_SHIFT 0 1336 /* width of bitfield dca{d}_cpuid[7:0] */ 1337 #define HW_ATL_TDM_DCADCPUID_WIDTH 8 1338 /* default value of bitfield dca{d}_cpuid[7:0] */ 1339 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1340 1341 /* tx lso_en[1f:0] bitfield definitions 1342 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1343 * port="pif_tdm_lso_en_i[31:0]" 1344 */ 1345 1346 /* register address for bitfield lso_en[1f:0] */ 1347 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1348 /* bitmask for bitfield lso_en[1f:0] */ 1349 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1350 /* inverted bitmask for bitfield lso_en[1f:0] */ 1351 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1352 /* lower bit position of bitfield lso_en[1f:0] */ 1353 #define HW_ATL_TDM_LSO_EN_SHIFT 0 1354 /* width of bitfield lso_en[1f:0] */ 1355 #define HW_ATL_TDM_LSO_EN_WIDTH 32 1356 /* default value of bitfield lso_en[1f:0] */ 1357 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1358 1359 /* tx dca_en bitfield definitions 1360 * preprocessor definitions for the bitfield "dca_en". 1361 * port="pif_tdm_dca_en_i" 1362 */ 1363 1364 /* register address for bitfield dca_en */ 1365 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1366 /* bitmask for bitfield dca_en */ 1367 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1368 /* inverted bitmask for bitfield dca_en */ 1369 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1370 /* lower bit position of bitfield dca_en */ 1371 #define HW_ATL_TDM_DCA_EN_SHIFT 31 1372 /* width of bitfield dca_en */ 1373 #define HW_ATL_TDM_DCA_EN_WIDTH 1 1374 /* default value of bitfield dca_en */ 1375 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1376 1377 /* tx dca_mode[3:0] bitfield definitions 1378 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1379 * port="pif_tdm_dca_mode_i[3:0]" 1380 */ 1381 1382 /* register address for bitfield dca_mode[3:0] */ 1383 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1384 /* bitmask for bitfield dca_mode[3:0] */ 1385 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1386 /* inverted bitmask for bitfield dca_mode[3:0] */ 1387 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1388 /* lower bit position of bitfield dca_mode[3:0] */ 1389 #define HW_ATL_TDM_DCA_MODE_SHIFT 0 1390 /* width of bitfield dca_mode[3:0] */ 1391 #define HW_ATL_TDM_DCA_MODE_WIDTH 4 1392 /* default value of bitfield dca_mode[3:0] */ 1393 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1394 1395 /* tx dca{d}_desc_en bitfield definitions 1396 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1397 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1398 * port="pif_tdm_dca_desc_en_i[0]" 1399 */ 1400 1401 /* register address for bitfield dca{d}_desc_en */ 1402 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1403 /* bitmask for bitfield dca{d}_desc_en */ 1404 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1405 /* inverted bitmask for bitfield dca{d}_desc_en */ 1406 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1407 /* lower bit position of bitfield dca{d}_desc_en */ 1408 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1409 /* width of bitfield dca{d}_desc_en */ 1410 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1411 /* default value of bitfield dca{d}_desc_en */ 1412 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1413 1414 /* tx desc{d}_en bitfield definitions 1415 * preprocessor definitions for the bitfield "desc{d}_en". 1416 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1417 * port="pif_tdm_desc_en_i[0]" 1418 */ 1419 1420 /* register address for bitfield desc{d}_en */ 1421 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1422 /* bitmask for bitfield desc{d}_en */ 1423 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1424 /* inverted bitmask for bitfield desc{d}_en */ 1425 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1426 /* lower bit position of bitfield desc{d}_en */ 1427 #define HW_ATL_TDM_DESCDEN_SHIFT 31 1428 /* width of bitfield desc{d}_en */ 1429 #define HW_ATL_TDM_DESCDEN_WIDTH 1 1430 /* default value of bitfield desc{d}_en */ 1431 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1432 1433 /* tx desc{d}_hd[c:0] bitfield definitions 1434 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1435 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1436 * port="tdm_pif_desc0_hd_o[12:0]" 1437 */ 1438 1439 /* register address for bitfield desc{d}_hd[c:0] */ 1440 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1441 /* bitmask for bitfield desc{d}_hd[c:0] */ 1442 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1443 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1444 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1445 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1446 #define HW_ATL_TDM_DESCDHD_SHIFT 0 1447 /* width of bitfield desc{d}_hd[c:0] */ 1448 #define HW_ATL_TDM_DESCDHD_WIDTH 13 1449 1450 /* tx desc{d}_len[9:0] bitfield definitions 1451 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1452 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1453 * port="pif_tdm_desc0_len_i[9:0]" 1454 */ 1455 1456 /* register address for bitfield desc{d}_len[9:0] */ 1457 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1458 /* bitmask for bitfield desc{d}_len[9:0] */ 1459 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1460 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1461 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1462 /* lower bit position of bitfield desc{d}_len[9:0] */ 1463 #define HW_ATL_TDM_DESCDLEN_SHIFT 3 1464 /* width of bitfield desc{d}_len[9:0] */ 1465 #define HW_ATL_TDM_DESCDLEN_WIDTH 10 1466 /* default value of bitfield desc{d}_len[9:0] */ 1467 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1468 1469 /* tx int_desc_wrb_en bitfield definitions 1470 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1471 * port="pif_tdm_int_desc_wrb_en_i" 1472 */ 1473 1474 /* register address for bitfield int_desc_wrb_en */ 1475 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1476 /* bitmask for bitfield int_desc_wrb_en */ 1477 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1478 /* inverted bitmask for bitfield int_desc_wrb_en */ 1479 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1480 /* lower bit position of bitfield int_desc_wrb_en */ 1481 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1482 /* width of bitfield int_desc_wrb_en */ 1483 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1484 /* default value of bitfield int_desc_wrb_en */ 1485 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1486 1487 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1488 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1489 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1490 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1491 */ 1492 1493 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1494 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1495 (0x00007c18 + (descriptor) * 0x40) 1496 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1497 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1498 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1499 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1500 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1501 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1502 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1503 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1504 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1505 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1506 1507 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1508 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1509 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1510 */ 1511 1512 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1513 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1514 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1515 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1516 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1517 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1518 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1519 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1520 /* width of bitfield lso_tcp_flag_first[b:0] */ 1521 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1522 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1523 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1524 1525 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1526 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1527 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1528 */ 1529 1530 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1531 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1532 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1533 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1534 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1535 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1536 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1537 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1538 /* width of bitfield lso_tcp_flag_last[b:0] */ 1539 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1540 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1541 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1542 1543 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1544 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1545 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1546 */ 1547 1548 /* Register address for bitfield lro_rsc_max[1F:0] */ 1549 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1550 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1551 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1552 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1553 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1554 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1555 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1556 /* Width of bitfield lro_rsc_max[1F:0] */ 1557 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1558 /* Default value of bitfield lro_rsc_max[1F:0] */ 1559 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1560 1561 /* RX lro_en[1F:0] Bitfield Definitions 1562 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1563 * PORT="pif_rpo_lro_en_i[31:0]" 1564 */ 1565 1566 /* Register address for bitfield lro_en[1F:0] */ 1567 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1568 /* Bitmask for bitfield lro_en[1F:0] */ 1569 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1570 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1571 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1572 /* Lower bit position of bitfield lro_en[1F:0] */ 1573 #define HW_ATL_RPO_LRO_EN_SHIFT 0 1574 /* Width of bitfield lro_en[1F:0] */ 1575 #define HW_ATL_RPO_LRO_EN_WIDTH 32 1576 /* Default value of bitfield lro_en[1F:0] */ 1577 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1578 1579 /* RX lro_ptopt_en Bitfield Definitions 1580 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1581 * PORT="pif_rpo_lro_ptopt_en_i" 1582 */ 1583 1584 /* Register address for bitfield lro_ptopt_en */ 1585 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1586 /* Bitmask for bitfield lro_ptopt_en */ 1587 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1588 /* Inverted bitmask for bitfield lro_ptopt_en */ 1589 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1590 /* Lower bit position of bitfield lro_ptopt_en */ 1591 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1592 /* Width of bitfield lro_ptopt_en */ 1593 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1594 /* Default value of bitfield lro_ptopt_en */ 1595 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1596 1597 /* RX lro_q_ses_lmt Bitfield Definitions 1598 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1599 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1600 */ 1601 1602 /* Register address for bitfield lro_q_ses_lmt */ 1603 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1604 /* Bitmask for bitfield lro_q_ses_lmt */ 1605 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1606 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1607 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1608 /* Lower bit position of bitfield lro_q_ses_lmt */ 1609 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1610 /* Width of bitfield lro_q_ses_lmt */ 1611 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1612 /* Default value of bitfield lro_q_ses_lmt */ 1613 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1614 1615 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1616 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1617 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1618 */ 1619 1620 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1621 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1622 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1623 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1624 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1625 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1626 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1627 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1628 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1629 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1630 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1631 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1632 1633 /* RX lro_pkt_min[4:0] Bitfield Definitions 1634 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1635 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1636 */ 1637 1638 /* Register address for bitfield lro_pkt_min[4:0] */ 1639 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1640 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1641 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1642 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1643 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1644 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1645 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1646 /* Width of bitfield lro_pkt_min[4:0] */ 1647 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1648 /* Default value of bitfield lro_pkt_min[4:0] */ 1649 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1650 1651 /* Width of bitfield lro{L}_des_max[1:0] */ 1652 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1653 /* Default value of bitfield lro{L}_des_max[1:0] */ 1654 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1655 1656 /* RX lro_tb_div[11:0] Bitfield Definitions 1657 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1658 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1659 */ 1660 1661 /* Register address for bitfield lro_tb_div[11:0] */ 1662 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1663 /* Bitmask for bitfield lro_tb_div[11:0] */ 1664 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1665 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1666 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1667 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1668 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1669 /* Width of bitfield lro_tb_div[11:0] */ 1670 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1671 /* Default value of bitfield lro_tb_div[11:0] */ 1672 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1673 1674 /* RX lro_ina_ival[9:0] Bitfield Definitions 1675 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1676 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1677 */ 1678 1679 /* Register address for bitfield lro_ina_ival[9:0] */ 1680 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1681 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1682 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1683 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1684 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1685 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1686 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1687 /* Width of bitfield lro_ina_ival[9:0] */ 1688 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1689 /* Default value of bitfield lro_ina_ival[9:0] */ 1690 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1691 1692 /* RX lro_max_ival[9:0] Bitfield Definitions 1693 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1694 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1695 */ 1696 1697 /* Register address for bitfield lro_max_ival[9:0] */ 1698 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1699 /* Bitmask for bitfield lro_max_ival[9:0] */ 1700 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1701 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1702 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1703 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1704 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1705 /* Width of bitfield lro_max_ival[9:0] */ 1706 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1707 /* Default value of bitfield lro_max_ival[9:0] */ 1708 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1709 1710 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1711 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1712 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1713 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1714 */ 1715 1716 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1717 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1718 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1719 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1720 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1721 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1722 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1723 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1724 /* Width of bitfield dca{D}_cpuid[7:0] */ 1725 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1726 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1727 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1728 1729 /* TX dca{D}_desc_en Bitfield Definitions 1730 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1731 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1732 * PORT="pif_tdm_dca_desc_en_i[0]" 1733 */ 1734 1735 /* Register address for bitfield dca{D}_desc_en */ 1736 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1737 /* Bitmask for bitfield dca{D}_desc_en */ 1738 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1739 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1740 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1741 /* Lower bit position of bitfield dca{D}_desc_en */ 1742 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1743 /* Width of bitfield dca{D}_desc_en */ 1744 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1745 /* Default value of bitfield dca{D}_desc_en */ 1746 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1747 1748 /* TX desc{D}_en Bitfield Definitions 1749 * Preprocessor definitions for the bitfield "desc{D}_en". 1750 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1751 * PORT="pif_tdm_desc_en_i[0]" 1752 */ 1753 1754 /* Register address for bitfield desc{D}_en */ 1755 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1756 /* Bitmask for bitfield desc{D}_en */ 1757 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 1758 /* Inverted bitmask for bitfield desc{D}_en */ 1759 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 1760 /* Lower bit position of bitfield desc{D}_en */ 1761 #define HW_ATL_TDM_DESC_DEN_SHIFT 31 1762 /* Width of bitfield desc{D}_en */ 1763 #define HW_ATL_TDM_DESC_DEN_WIDTH 1 1764 /* Default value of bitfield desc{D}_en */ 1765 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 1766 1767 /* TX desc{D}_hd[C:0] Bitfield Definitions 1768 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1769 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1770 * PORT="tdm_pif_desc0_hd_o[12:0]" 1771 */ 1772 1773 /* Register address for bitfield desc{D}_hd[C:0] */ 1774 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 1775 /* Bitmask for bitfield desc{D}_hd[C:0] */ 1776 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 1777 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1778 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 1779 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 1780 #define HW_ATL_TDM_DESC_DHD_SHIFT 0 1781 /* Width of bitfield desc{D}_hd[C:0] */ 1782 #define HW_ATL_TDM_DESC_DHD_WIDTH 13 1783 1784 /* TX desc{D}_len[9:0] Bitfield Definitions 1785 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1786 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1787 * PORT="pif_tdm_desc0_len_i[9:0]" 1788 */ 1789 1790 /* Register address for bitfield desc{D}_len[9:0] */ 1791 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1792 /* Bitmask for bitfield desc{D}_len[9:0] */ 1793 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 1794 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1795 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 1796 /* Lower bit position of bitfield desc{D}_len[9:0] */ 1797 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3 1798 /* Width of bitfield desc{D}_len[9:0] */ 1799 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10 1800 /* Default value of bitfield desc{D}_len[9:0] */ 1801 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 1802 1803 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1804 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1805 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1806 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 1807 */ 1808 1809 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1810 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 1811 (0x00007C18 + (descriptor) * 0x40) 1812 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1813 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 1814 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1815 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 1816 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 1817 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 1818 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 1819 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 1820 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 1821 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 1822 1823 /* TX tdm_int_mod_en Bitfield Definitions 1824 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 1825 * PORT="pif_tdm_int_mod_en_i" 1826 */ 1827 1828 /* Register address for bitfield tdm_int_mod_en */ 1829 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 1830 /* Bitmask for bitfield tdm_int_mod_en */ 1831 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 1832 /* Inverted bitmask for bitfield tdm_int_mod_en */ 1833 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 1834 /* Lower bit position of bitfield tdm_int_mod_en */ 1835 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 1836 /* Width of bitfield tdm_int_mod_en */ 1837 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 1838 /* Default value of bitfield tdm_int_mod_en */ 1839 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 1840 1841 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 1842 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 1843 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 1844 */ 1845 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 1846 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 1847 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1848 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 1849 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1850 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 1851 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 1852 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 1853 /* width of bitfield lso_tcp_flag_mid[b:0] */ 1854 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 1855 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 1856 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 1857 1858 /* tx tx_buf_en bitfield definitions 1859 * preprocessor definitions for the bitfield "tx_buf_en". 1860 * port="pif_tpb_tx_buf_en_i" 1861 */ 1862 1863 /* register address for bitfield tx_buf_en */ 1864 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 1865 /* bitmask for bitfield tx_buf_en */ 1866 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 1867 /* inverted bitmask for bitfield tx_buf_en */ 1868 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 1869 /* lower bit position of bitfield tx_buf_en */ 1870 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 1871 /* width of bitfield tx_buf_en */ 1872 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 1873 /* default value of bitfield tx_buf_en */ 1874 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 1875 1876 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 1877 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 1878 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1879 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 1880 */ 1881 1882 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 1883 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 1884 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1885 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 1886 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1887 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 1888 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 1889 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 1890 /* width of bitfield tx{b}_hi_thresh[c:0] */ 1891 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 1892 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 1893 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 1894 1895 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 1896 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 1897 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1898 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 1899 */ 1900 1901 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 1902 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 1903 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1904 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 1905 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1906 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 1907 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 1908 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 1909 /* width of bitfield tx{b}_lo_thresh[c:0] */ 1910 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 1911 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 1912 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 1913 1914 /* tx dma_sys_loopback bitfield definitions 1915 * preprocessor definitions for the bitfield "dma_sys_loopback". 1916 * port="pif_tpb_dma_sys_lbk_i" 1917 */ 1918 1919 /* register address for bitfield dma_sys_loopback */ 1920 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 1921 /* bitmask for bitfield dma_sys_loopback */ 1922 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 1923 /* inverted bitmask for bitfield dma_sys_loopback */ 1924 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 1925 /* lower bit position of bitfield dma_sys_loopback */ 1926 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 1927 /* width of bitfield dma_sys_loopback */ 1928 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 1929 /* default value of bitfield dma_sys_loopback */ 1930 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 1931 1932 /* tx tx{b}_buf_size[7:0] bitfield definitions 1933 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 1934 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1935 * port="pif_tpb_tx0_buf_size_i[7:0]" 1936 */ 1937 1938 /* register address for bitfield tx{b}_buf_size[7:0] */ 1939 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 1940 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 1941 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 1942 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 1943 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 1944 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 1945 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 1946 /* width of bitfield tx{b}_buf_size[7:0] */ 1947 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 1948 /* default value of bitfield tx{b}_buf_size[7:0] */ 1949 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 1950 1951 /* tx tx_scp_ins_en bitfield definitions 1952 * preprocessor definitions for the bitfield "tx_scp_ins_en". 1953 * port="pif_tpb_scp_ins_en_i" 1954 */ 1955 1956 /* register address for bitfield tx_scp_ins_en */ 1957 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 1958 /* bitmask for bitfield tx_scp_ins_en */ 1959 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 1960 /* inverted bitmask for bitfield tx_scp_ins_en */ 1961 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 1962 /* lower bit position of bitfield tx_scp_ins_en */ 1963 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 1964 /* width of bitfield tx_scp_ins_en */ 1965 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 1966 /* default value of bitfield tx_scp_ins_en */ 1967 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 1968 1969 /* tx ipv4_chk_en bitfield definitions 1970 * preprocessor definitions for the bitfield "ipv4_chk_en". 1971 * port="pif_tpo_ipv4_chk_en_i" 1972 */ 1973 1974 /* register address for bitfield ipv4_chk_en */ 1975 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 1976 /* bitmask for bitfield ipv4_chk_en */ 1977 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 1978 /* inverted bitmask for bitfield ipv4_chk_en */ 1979 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 1980 /* lower bit position of bitfield ipv4_chk_en */ 1981 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 1982 /* width of bitfield ipv4_chk_en */ 1983 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 1984 /* default value of bitfield ipv4_chk_en */ 1985 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 1986 1987 /* tx l4_chk_en bitfield definitions 1988 * preprocessor definitions for the bitfield "l4_chk_en". 1989 * port="pif_tpo_l4_chk_en_i" 1990 */ 1991 1992 /* register address for bitfield l4_chk_en */ 1993 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 1994 /* bitmask for bitfield l4_chk_en */ 1995 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 1996 /* inverted bitmask for bitfield l4_chk_en */ 1997 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 1998 /* lower bit position of bitfield l4_chk_en */ 1999 #define HW_ATL_TPOL4CHK_EN_SHIFT 0 2000 /* width of bitfield l4_chk_en */ 2001 #define HW_ATL_TPOL4CHK_EN_WIDTH 1 2002 /* default value of bitfield l4_chk_en */ 2003 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2004 2005 /* tx pkt_sys_loopback bitfield definitions 2006 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2007 * port="pif_tpo_pkt_sys_lbk_i" 2008 */ 2009 2010 /* register address for bitfield pkt_sys_loopback */ 2011 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2012 /* bitmask for bitfield pkt_sys_loopback */ 2013 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2014 /* inverted bitmask for bitfield pkt_sys_loopback */ 2015 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2016 /* lower bit position of bitfield pkt_sys_loopback */ 2017 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2018 /* width of bitfield pkt_sys_loopback */ 2019 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2020 /* default value of bitfield pkt_sys_loopback */ 2021 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2022 2023 /* tx data_tc_arb_mode bitfield definitions 2024 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2025 * port="pif_tps_data_tc_arb_mode_i" 2026 */ 2027 2028 /* register address for bitfield data_tc_arb_mode */ 2029 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2030 /* bitmask for bitfield data_tc_arb_mode */ 2031 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2032 /* inverted bitmask for bitfield data_tc_arb_mode */ 2033 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2034 /* lower bit position of bitfield data_tc_arb_mode */ 2035 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2036 /* width of bitfield data_tc_arb_mode */ 2037 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2038 /* default value of bitfield data_tc_arb_mode */ 2039 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2040 2041 /* tx desc_rate_ta_rst bitfield definitions 2042 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2043 * port="pif_tps_desc_rate_ta_rst_i" 2044 */ 2045 2046 /* register address for bitfield desc_rate_ta_rst */ 2047 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2048 /* bitmask for bitfield desc_rate_ta_rst */ 2049 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2050 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2051 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2052 /* lower bit position of bitfield desc_rate_ta_rst */ 2053 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2054 /* width of bitfield desc_rate_ta_rst */ 2055 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2056 /* default value of bitfield desc_rate_ta_rst */ 2057 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2058 2059 /* tx desc_rate_limit[a:0] bitfield definitions 2060 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2061 * port="pif_tps_desc_rate_lim_i[10:0]" 2062 */ 2063 2064 /* register address for bitfield desc_rate_limit[a:0] */ 2065 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2066 /* bitmask for bitfield desc_rate_limit[a:0] */ 2067 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2068 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2069 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2070 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2071 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2072 /* width of bitfield desc_rate_limit[a:0] */ 2073 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2074 /* default value of bitfield desc_rate_limit[a:0] */ 2075 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2076 2077 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2078 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2079 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2080 */ 2081 2082 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2083 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2084 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2085 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2086 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2087 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2088 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2089 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2090 /* width of bitfield desc_tc_arb_mode[1:0] */ 2091 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2092 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2093 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2094 2095 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2096 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2097 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2098 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2099 */ 2100 2101 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2102 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2103 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2104 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2105 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2106 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2107 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2108 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2109 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2110 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2111 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2112 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2113 2114 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2115 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2116 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2117 * port="pif_tps_desc_tc0_weight_i[8:0]" 2118 */ 2119 2120 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2121 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2122 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2123 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2124 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2125 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2126 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2127 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2128 /* width of bitfield desc_tc{t}_weight[8:0] */ 2129 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2130 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2131 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2132 2133 /* tx desc_vm_arb_mode bitfield definitions 2134 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2135 * port="pif_tps_desc_vm_arb_mode_i" 2136 */ 2137 2138 /* register address for bitfield desc_vm_arb_mode */ 2139 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2140 /* bitmask for bitfield desc_vm_arb_mode */ 2141 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2142 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2143 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2144 /* lower bit position of bitfield desc_vm_arb_mode */ 2145 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2146 /* width of bitfield desc_vm_arb_mode */ 2147 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2148 /* default value of bitfield desc_vm_arb_mode */ 2149 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2150 2151 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2152 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2153 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2154 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2155 */ 2156 2157 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2158 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2159 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2160 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2161 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2162 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2163 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2164 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2165 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2166 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2167 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2168 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2169 2170 /* tx data_tc{t}_weight[8:0] bitfield definitions 2171 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2172 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2173 * port="pif_tps_data_tc0_weight_i[8:0]" 2174 */ 2175 2176 /* register address for bitfield data_tc{t}_weight[8:0] */ 2177 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2178 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2179 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2180 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2181 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2182 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2183 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2184 /* width of bitfield data_tc{t}_weight[8:0] */ 2185 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2186 /* default value of bitfield data_tc{t}_weight[8:0] */ 2187 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2188 2189 /* tx reg_res_dsbl bitfield definitions 2190 * preprocessor definitions for the bitfield "reg_res_dsbl". 2191 * port="pif_tx_reg_res_dsbl_i" 2192 */ 2193 2194 /* register address for bitfield reg_res_dsbl */ 2195 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2196 /* bitmask for bitfield reg_res_dsbl */ 2197 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2198 /* inverted bitmask for bitfield reg_res_dsbl */ 2199 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2200 /* lower bit position of bitfield reg_res_dsbl */ 2201 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2202 /* width of bitfield reg_res_dsbl */ 2203 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2204 /* default value of bitfield reg_res_dsbl */ 2205 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2206 2207 /* mac_phy register access busy bitfield definitions 2208 * preprocessor definitions for the bitfield "register access busy". 2209 * port="msm_pif_reg_busy_o" 2210 */ 2211 2212 /* register address for bitfield register access busy */ 2213 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2214 /* bitmask for bitfield register access busy */ 2215 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2216 /* inverted bitmask for bitfield register access busy */ 2217 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2218 /* lower bit position of bitfield register access busy */ 2219 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2220 /* width of bitfield register access busy */ 2221 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2222 2223 /* mac_phy msm register address[7:0] bitfield definitions 2224 * preprocessor definitions for the bitfield "msm register address[7:0]". 2225 * port="pif_msm_reg_addr_i[7:0]" 2226 */ 2227 2228 /* register address for bitfield msm register address[7:0] */ 2229 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2230 /* bitmask for bitfield msm register address[7:0] */ 2231 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2232 /* inverted bitmask for bitfield msm register address[7:0] */ 2233 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2234 /* lower bit position of bitfield msm register address[7:0] */ 2235 #define HW_ATL_MSM_REG_ADDR_SHIFT 0 2236 /* width of bitfield msm register address[7:0] */ 2237 #define HW_ATL_MSM_REG_ADDR_WIDTH 8 2238 /* default value of bitfield msm register address[7:0] */ 2239 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2240 2241 /* mac_phy register read strobe bitfield definitions 2242 * preprocessor definitions for the bitfield "register read strobe". 2243 * port="pif_msm_reg_rden_i" 2244 */ 2245 2246 /* register address for bitfield register read strobe */ 2247 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2248 /* bitmask for bitfield register read strobe */ 2249 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2250 /* inverted bitmask for bitfield register read strobe */ 2251 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2252 /* lower bit position of bitfield register read strobe */ 2253 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2254 /* width of bitfield register read strobe */ 2255 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2256 /* default value of bitfield register read strobe */ 2257 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2258 2259 /* mac_phy msm register read data[31:0] bitfield definitions 2260 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2261 * port="msm_pif_reg_rd_data_o[31:0]" 2262 */ 2263 2264 /* register address for bitfield msm register read data[31:0] */ 2265 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2266 /* bitmask for bitfield msm register read data[31:0] */ 2267 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2268 /* inverted bitmask for bitfield msm register read data[31:0] */ 2269 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2270 /* lower bit position of bitfield msm register read data[31:0] */ 2271 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2272 /* width of bitfield msm register read data[31:0] */ 2273 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2274 2275 /* mac_phy msm register write data[31:0] bitfield definitions 2276 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2277 * port="pif_msm_reg_wr_data_i[31:0]" 2278 */ 2279 2280 /* register address for bitfield msm register write data[31:0] */ 2281 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2282 /* bitmask for bitfield msm register write data[31:0] */ 2283 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2284 /* inverted bitmask for bitfield msm register write data[31:0] */ 2285 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2286 /* lower bit position of bitfield msm register write data[31:0] */ 2287 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2288 /* width of bitfield msm register write data[31:0] */ 2289 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2290 /* default value of bitfield msm register write data[31:0] */ 2291 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2292 2293 /* mac_phy register write strobe bitfield definitions 2294 * preprocessor definitions for the bitfield "register write strobe". 2295 * port="pif_msm_reg_wren_i" 2296 */ 2297 2298 /* register address for bitfield register write strobe */ 2299 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2300 /* bitmask for bitfield register write strobe */ 2301 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2302 /* inverted bitmask for bitfield register write strobe */ 2303 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2304 /* lower bit position of bitfield register write strobe */ 2305 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2306 /* width of bitfield register write strobe */ 2307 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2308 /* default value of bitfield register write strobe */ 2309 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2310 2311 /* mif soft reset bitfield definitions 2312 * preprocessor definitions for the bitfield "soft reset". 2313 * port="pif_glb_res_i" 2314 */ 2315 2316 /* register address for bitfield soft reset */ 2317 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2318 /* bitmask for bitfield soft reset */ 2319 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2320 /* inverted bitmask for bitfield soft reset */ 2321 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2322 /* lower bit position of bitfield soft reset */ 2323 #define HW_ATL_GLB_SOFT_RES_SHIFT 15 2324 /* width of bitfield soft reset */ 2325 #define HW_ATL_GLB_SOFT_RES_WIDTH 1 2326 /* default value of bitfield soft reset */ 2327 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2328 2329 /* mif register reset disable bitfield definitions 2330 * preprocessor definitions for the bitfield "register reset disable". 2331 * port="pif_glb_reg_res_dsbl_i" 2332 */ 2333 2334 /* register address for bitfield register reset disable */ 2335 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2336 /* bitmask for bitfield register reset disable */ 2337 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2338 /* inverted bitmask for bitfield register reset disable */ 2339 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2340 /* lower bit position of bitfield register reset disable */ 2341 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2342 /* width of bitfield register reset disable */ 2343 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2344 /* default value of bitfield register reset disable */ 2345 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2346 2347 /* tx dma debug control definitions */ 2348 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2349 2350 /* tx dma descriptor base address msw definitions */ 2351 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2352 (0x00007c04u + (descriptor) * 0x40) 2353 2354 /* tx dma total request limit */ 2355 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2356 2357 /* tx interrupt moderation control register definitions 2358 * Preprocessor definitions for TX Interrupt Moderation Control Register 2359 * Base Address: 0x00008980 2360 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2361 */ 2362 2363 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2364 2365 /* pcie reg_res_dsbl bitfield definitions 2366 * preprocessor definitions for the bitfield "reg_res_dsbl". 2367 * port="pif_pci_reg_res_dsbl_i" 2368 */ 2369 2370 /* register address for bitfield reg_res_dsbl */ 2371 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2372 /* bitmask for bitfield reg_res_dsbl */ 2373 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2374 /* inverted bitmask for bitfield reg_res_dsbl */ 2375 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2376 /* lower bit position of bitfield reg_res_dsbl */ 2377 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2378 /* width of bitfield reg_res_dsbl */ 2379 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2380 /* default value of bitfield reg_res_dsbl */ 2381 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2382 2383 /* PCI core control register */ 2384 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2385 2386 /* global microprocessor scratch pad definitions */ 2387 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2388 (0x00000300u + (scratch_scp) * 0x4) 2389 2390 #endif /* HW_ATL_LLH_INTERNAL_H */ 2391
