1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 /* File hw_atl_llh.h: Declarations of bitfield and register access functions for 11 * Atlantic registers. 12 */ 13 14 #ifndef HW_ATL_LLH_H 15 #define HW_ATL_LLH_H 16 17 #include <linux/types.h> 18 19 struct aq_hw_s; 20 21 /* global */ 22 23 /* set global microprocessor semaphore */ 24 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, 25 u32 semaphore); 26 27 /* get global microprocessor semaphore */ 28 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore); 29 30 /* set global register reset disable */ 31 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis); 32 33 /* set soft reset */ 34 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res); 35 36 /* get soft reset */ 37 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw); 38 39 /* stats */ 40 41 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw); 42 43 /* get rx dma good octet counter lsw */ 44 u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); 45 46 /* get rx dma good packet counter lsw */ 47 u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); 48 49 /* get tx dma good octet counter lsw */ 50 u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); 51 52 /* get tx dma good packet counter lsw */ 53 u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); 54 55 /* get rx dma good octet counter msw */ 56 u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); 57 58 /* get rx dma good packet counter msw */ 59 u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); 60 61 /* get tx dma good octet counter msw */ 62 u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); 63 64 /* get tx dma good packet counter msw */ 65 u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); 66 67 /* get msm rx errors counter register */ 68 u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw); 69 70 /* get msm rx unicast frames counter register */ 71 u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); 72 73 /* get msm rx multicast frames counter register */ 74 u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); 75 76 /* get msm rx broadcast frames counter register */ 77 u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); 78 79 /* get msm rx broadcast octets counter register 1 */ 80 u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); 81 82 /* get msm rx unicast octets counter register 0 */ 83 u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); 84 85 /* get rx dma statistics counter 7 */ 86 u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw); 87 88 /* get msm tx errors counter register */ 89 u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw); 90 91 /* get msm tx unicast frames counter register */ 92 u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); 93 94 /* get msm tx multicast frames counter register */ 95 u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); 96 97 /* get msm tx broadcast frames counter register */ 98 u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); 99 100 /* get msm tx multicast octets counter register 1 */ 101 u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw); 102 103 /* get msm tx broadcast octets counter register 1 */ 104 u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); 105 106 /* get msm tx unicast octets counter register 0 */ 107 u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); 108 109 /* get global mif identification */ 110 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw); 111 112 /* interrupt */ 113 114 /* set interrupt auto mask lsw */ 115 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, 116 u32 irq_auto_masklsw); 117 118 /* set interrupt mapping enable rx */ 119 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, 120 u32 rx); 121 122 /* set interrupt mapping enable tx */ 123 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, 124 u32 tx); 125 126 /* set interrupt mapping rx */ 127 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx); 128 129 /* set interrupt mapping tx */ 130 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx); 131 132 /* set interrupt mask clear lsw */ 133 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, 134 u32 irq_msk_clearlsw); 135 136 /* set interrupt mask set lsw */ 137 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw); 138 139 /* set interrupt register reset disable */ 140 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis); 141 142 /* set interrupt status clear lsw */ 143 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, 144 u32 irq_status_clearlsw); 145 146 /* get interrupt status lsw */ 147 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw); 148 149 /* get reset interrupt */ 150 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw); 151 152 /* set reset interrupt */ 153 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq); 154 155 /* rdm */ 156 157 /* set cpu id */ 158 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); 159 160 /* set rx dca enable */ 161 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en); 162 163 /* set rx dca mode */ 164 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode); 165 166 /* set rx descriptor data buffer size */ 167 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, 168 u32 rx_desc_data_buff_size, 169 u32 descriptor); 170 171 /* set rx descriptor dca enable */ 172 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, 173 u32 dca); 174 175 /* set rx descriptor enable */ 176 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, 177 u32 descriptor); 178 179 /* set rx descriptor header splitting */ 180 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, 181 u32 rx_desc_head_splitting, 182 u32 descriptor); 183 184 /* get rx descriptor head pointer */ 185 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); 186 187 /* set rx descriptor length */ 188 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, 189 u32 descriptor); 190 191 /* set rx descriptor write-back interrupt enable */ 192 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 193 u32 rx_desc_wr_wb_irq_en); 194 195 /* set rx header dca enable */ 196 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, 197 u32 dca); 198 199 /* set rx payload dca enable */ 200 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, 201 u32 dca); 202 203 /* set rx descriptor header buffer size */ 204 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, 205 u32 rx_desc_head_buff_size, 206 u32 descriptor); 207 208 /* set rx descriptor reset */ 209 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, 210 u32 descriptor); 211 212 /* Set RDM Interrupt Moderation Enable */ 213 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, 214 u32 rdm_intr_moder_en); 215 216 /* reg */ 217 218 /* set general interrupt mapping register */ 219 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, 220 u32 regidx); 221 222 /* get general interrupt status register */ 223 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw); 224 225 /* set interrupt global control register */ 226 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl); 227 228 /* set interrupt throttle register */ 229 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle); 230 231 /* set rx dma descriptor base address lsw */ 232 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 233 u32 rx_dma_desc_base_addrlsw, 234 u32 descriptor); 235 236 /* set rx dma descriptor base address msw */ 237 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 238 u32 rx_dma_desc_base_addrmsw, 239 u32 descriptor); 240 241 /* get rx dma descriptor status register */ 242 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor); 243 244 /* set rx dma descriptor tail pointer register */ 245 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 246 u32 rx_dma_desc_tail_ptr, 247 u32 descriptor); 248 249 /* set rx filter multicast filter mask register */ 250 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, 251 u32 rx_flr_mcst_flr_msk); 252 253 /* set rx filter multicast filter register */ 254 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, 255 u32 filter); 256 257 /* set rx filter rss control register 1 */ 258 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, 259 u32 rx_flr_rss_control1); 260 261 /* Set RX Filter Control Register 2 */ 262 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2); 263 264 /* Set RX Interrupt Moderation Control Register */ 265 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 266 u32 rx_intr_moderation_ctl, 267 u32 queue); 268 269 /* set tx dma debug control */ 270 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, 271 u32 tx_dma_debug_ctl); 272 273 /* set tx dma descriptor base address lsw */ 274 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, 275 u32 tx_dma_desc_base_addrlsw, 276 u32 descriptor); 277 278 /* set tx dma descriptor base address msw */ 279 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, 280 u32 tx_dma_desc_base_addrmsw, 281 u32 descriptor); 282 283 /* set tx dma descriptor tail pointer register */ 284 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, 285 u32 tx_dma_desc_tail_ptr, 286 u32 descriptor); 287 288 /* Set TX Interrupt Moderation Control Register */ 289 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, 290 u32 tx_intr_moderation_ctl, 291 u32 queue); 292 293 /* set global microprocessor scratch pad */ 294 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, 295 u32 glb_cpu_scratch_scp, 296 u32 scratch_scp); 297 298 /* rpb */ 299 300 /* set dma system loopback */ 301 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk); 302 303 /* set rx traffic class mode */ 304 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, 305 u32 rx_traf_class_mode); 306 307 /* set rx buffer enable */ 308 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en); 309 310 /* set rx buffer high threshold (per tc) */ 311 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 312 u32 rx_buff_hi_threshold_per_tc, 313 u32 buffer); 314 315 /* set rx buffer low threshold (per tc) */ 316 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 317 u32 rx_buff_lo_threshold_per_tc, 318 u32 buffer); 319 320 /* set rx flow control mode */ 321 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode); 322 323 /* set rx packet buffer size (per tc) */ 324 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 325 u32 rx_pkt_buff_size_per_tc, 326 u32 buffer); 327 328 /* set rx xoff enable (per tc) */ 329 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc, 330 u32 buffer); 331 332 /* rpf */ 333 334 /* set l2 broadcast count threshold */ 335 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, 336 u32 l2broadcast_count_threshold); 337 338 /* set l2 broadcast enable */ 339 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en); 340 341 /* set l2 broadcast filter action */ 342 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, 343 u32 l2broadcast_flr_act); 344 345 /* set l2 multicast filter enable */ 346 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, 347 u32 l2multicast_flr_en, 348 u32 filter); 349 350 /* set l2 promiscuous mode enable */ 351 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, 352 u32 l2promiscuous_mode_en); 353 354 /* set l2 unicast filter action */ 355 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, 356 u32 l2unicast_flr_act, 357 u32 filter); 358 359 /* set l2 unicast filter enable */ 360 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, 361 u32 filter); 362 363 /* set l2 unicast destination address lsw */ 364 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, 365 u32 l2unicast_dest_addresslsw, 366 u32 filter); 367 368 /* set l2 unicast destination address msw */ 369 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, 370 u32 l2unicast_dest_addressmsw, 371 u32 filter); 372 373 /* Set L2 Accept all Multicast packets */ 374 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, 375 u32 l2_accept_all_mc_packets); 376 377 /* set user-priority tc mapping */ 378 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, 379 u32 user_priority_tc_map, u32 tc); 380 381 /* set rss key address */ 382 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr); 383 384 /* set rss key write data */ 385 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data); 386 387 /* get rss key write enable */ 388 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw); 389 390 /* set rss key write enable */ 391 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en); 392 393 /* set rss redirection table address */ 394 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, 395 u32 rss_redir_tbl_addr); 396 397 /* set rss redirection table write data */ 398 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, 399 u32 rss_redir_tbl_wr_data); 400 401 /* get rss redirection write enable */ 402 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw); 403 404 /* set rss redirection write enable */ 405 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en); 406 407 /* set tpo to rpf system loopback */ 408 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, 409 u32 tpo_to_rpf_sys_lbk); 410 411 /* set vlan inner ethertype */ 412 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht); 413 414 /* set vlan outer ethertype */ 415 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); 416 417 /* set vlan promiscuous mode enable */ 418 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, 419 u32 vlan_prom_mode_en); 420 421 /* Set VLAN untagged action */ 422 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, 423 u32 vlan_untagged_act); 424 425 /* Set VLAN accept untagged packets */ 426 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, 427 u32 vlan_acc_untagged_packets); 428 429 /* Set VLAN filter enable */ 430 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, 431 u32 filter); 432 433 /* Set VLAN Filter Action */ 434 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act, 435 u32 filter); 436 437 /* Set VLAN ID Filter */ 438 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, 439 u32 filter); 440 441 /* set ethertype filter enable */ 442 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, 443 u32 filter); 444 445 /* set ethertype user-priority enable */ 446 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, 447 u32 etht_user_priority_en, 448 u32 filter); 449 450 /* set ethertype rx queue enable */ 451 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, 452 u32 etht_rx_queue_en, 453 u32 filter); 454 455 /* set ethertype rx queue */ 456 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, 457 u32 filter); 458 459 /* set ethertype user-priority */ 460 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, 461 u32 etht_user_priority, 462 u32 filter); 463 464 /* set ethertype management queue */ 465 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, 466 u32 filter); 467 468 /* set ethertype filter action */ 469 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, 470 u32 filter); 471 472 /* set ethertype filter */ 473 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter); 474 475 /* rpo */ 476 477 /* set ipv4 header checksum offload enable */ 478 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 479 u32 ipv4header_crc_offload_en); 480 481 /* set rx descriptor vlan stripping */ 482 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, 483 u32 rx_desc_vlan_stripping, 484 u32 descriptor); 485 486 /* set tcp/udp checksum offload enable */ 487 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 488 u32 tcp_udp_crc_offload_en); 489 490 /* Set LRO Patch Optimization Enable. */ 491 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, 492 u32 lro_patch_optimization_en); 493 494 /* Set Large Receive Offload Enable */ 495 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en); 496 497 /* Set LRO Q Sessions Limit */ 498 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, 499 u32 lro_qsessions_lim); 500 501 /* Set LRO Total Descriptor Limit */ 502 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, 503 u32 lro_total_desc_lim); 504 505 /* Set LRO Min Payload of First Packet */ 506 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, 507 u32 lro_min_pld_of_first_pkt); 508 509 /* Set LRO Packet Limit */ 510 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim); 511 512 /* Set LRO Max Number of Descriptors */ 513 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, 514 u32 lro_max_desc_num, u32 lro); 515 516 /* Set LRO Time Base Divider */ 517 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, 518 u32 lro_time_base_divider); 519 520 /*Set LRO Inactive Interval */ 521 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, 522 u32 lro_inactive_interval); 523 524 /*Set LRO Max Coalescing Interval */ 525 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, 526 u32 lro_max_coal_interval); 527 528 /* rx */ 529 530 /* set rx register reset disable */ 531 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis); 532 533 /* tdm */ 534 535 /* set cpu id */ 536 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); 537 538 /* set large send offload enable */ 539 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, 540 u32 large_send_offload_en); 541 542 /* set tx descriptor enable */ 543 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, 544 u32 descriptor); 545 546 /* set tx dca enable */ 547 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en); 548 549 /* set tx dca mode */ 550 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode); 551 552 /* set tx descriptor dca enable */ 553 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, 554 u32 dca); 555 556 /* get tx descriptor head pointer */ 557 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); 558 559 /* set tx descriptor length */ 560 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, 561 u32 descriptor); 562 563 /* set tx descriptor write-back interrupt enable */ 564 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, 565 u32 tx_desc_wr_wb_irq_en); 566 567 /* set tx descriptor write-back threshold */ 568 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, 569 u32 tx_desc_wr_wb_threshold, 570 u32 descriptor); 571 572 /* Set TDM Interrupt Moderation Enable */ 573 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, 574 u32 tdm_irq_moderation_en); 575 /* thm */ 576 577 /* set lso tcp flag of first packet */ 578 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, 579 u32 lso_tcp_flag_of_first_pkt); 580 581 /* set lso tcp flag of last packet */ 582 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, 583 u32 lso_tcp_flag_of_last_pkt); 584 585 /* set lso tcp flag of middle packet */ 586 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, 587 u32 lso_tcp_flag_of_middle_pkt); 588 589 /* tpb */ 590 591 /* set tx buffer enable */ 592 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en); 593 594 /* set tx buffer high threshold (per tc) */ 595 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, 596 u32 tx_buff_hi_threshold_per_tc, 597 u32 buffer); 598 599 /* set tx buffer low threshold (per tc) */ 600 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, 601 u32 tx_buff_lo_threshold_per_tc, 602 u32 buffer); 603 604 /* set tx dma system loopback enable */ 605 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en); 606 607 /* set tx packet buffer size (per tc) */ 608 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, 609 u32 tx_pkt_buff_size_per_tc, u32 buffer); 610 611 /* set tx path pad insert enable */ 612 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en); 613 614 /* tpo */ 615 616 /* set ipv4 header checksum offload enable */ 617 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, 618 u32 ipv4header_crc_offload_en); 619 620 /* set tcp/udp checksum offload enable */ 621 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, 622 u32 tcp_udp_crc_offload_en); 623 624 /* set tx pkt system loopback enable */ 625 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, 626 u32 tx_pkt_sys_lbk_en); 627 628 /* tps */ 629 630 /* set tx packet scheduler data arbitration mode */ 631 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, 632 u32 tx_pkt_shed_data_arb_mode); 633 634 /* set tx packet scheduler descriptor rate current time reset */ 635 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, 636 u32 curr_time_res); 637 638 /* set tx packet scheduler descriptor rate limit */ 639 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, 640 u32 tx_pkt_shed_desc_rate_lim); 641 642 /* set tx packet scheduler descriptor tc arbitration mode */ 643 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, 644 u32 arb_mode); 645 646 /* set tx packet scheduler descriptor tc max credit */ 647 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, 648 u32 max_credit, 649 u32 tc); 650 651 /* set tx packet scheduler descriptor tc weight */ 652 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, 653 u32 tx_pkt_shed_desc_tc_weight, 654 u32 tc); 655 656 /* set tx packet scheduler descriptor vm arbitration mode */ 657 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, 658 u32 arb_mode); 659 660 /* set tx packet scheduler tc data max credit */ 661 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, 662 u32 max_credit, 663 u32 tc); 664 665 /* set tx packet scheduler tc data weight */ 666 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, 667 u32 tx_pkt_shed_tc_data_weight, 668 u32 tc); 669 670 /* tx */ 671 672 /* set tx register reset disable */ 673 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis); 674 675 /* msm */ 676 677 /* get register access status */ 678 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw); 679 680 /* set register address for indirect address */ 681 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, 682 u32 reg_addr_for_indirect_addr); 683 684 /* set register read strobe */ 685 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe); 686 687 /* get register read data */ 688 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw); 689 690 /* set register write data */ 691 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data); 692 693 /* set register write strobe */ 694 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe); 695 696 /* pci */ 697 698 /* set pci register reset disable */ 699 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis); 700 701 #endif /* HW_ATL_LLH_H */ 702
