1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _hdp_5_2_1_OFFSET_HEADER 24 #define _hdp_5_2_1_OFFSET_HEADER 25 26 27 28 // addressBlock: hdp_hdpdec 29 // base address: 0x3c80 30 #define regHDP_MMHUB_TLVL 0x0000 31 #define regHDP_MMHUB_TLVL_BASE_IDX 0 32 #define regHDP_MMHUB_UNITID 0x0001 33 #define regHDP_MMHUB_UNITID_BASE_IDX 0 34 #define regHDP_NONSURFACE_BASE 0x0040 35 #define regHDP_NONSURFACE_BASE_BASE_IDX 0 36 #define regHDP_NONSURFACE_INFO 0x0041 37 #define regHDP_NONSURFACE_INFO_BASE_IDX 0 38 #define regHDP_NONSURFACE_BASE_HI 0x0042 39 #define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0 40 #define regHDP_SURFACE_WRITE_FLAGS 0x00c4 41 #define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0 42 #define regHDP_SURFACE_READ_FLAGS 0x00c5 43 #define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0 44 #define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6 45 #define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0 46 #define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7 47 #define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0 48 #define regHDP_NONSURF_FLAGS 0x00c8 49 #define regHDP_NONSURF_FLAGS_BASE_IDX 0 50 #define regHDP_NONSURF_FLAGS_CLR 0x00c9 51 #define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 52 #define regHDP_HOST_PATH_CNTL 0x00cc 53 #define regHDP_HOST_PATH_CNTL_BASE_IDX 0 54 #define regHDP_SW_SEMAPHORE 0x00cd 55 #define regHDP_SW_SEMAPHORE_BASE_IDX 0 56 #define regHDP_DEBUG0 0x00ce 57 #define regHDP_DEBUG0_BASE_IDX 0 58 #define regHDP_LAST_SURFACE_HIT 0x00d0 59 #define regHDP_LAST_SURFACE_HIT_BASE_IDX 0 60 #define regHDP_OUTSTANDING_REQ 0x00d2 61 #define regHDP_OUTSTANDING_REQ_BASE_IDX 0 62 #define regHDP_MISC_CNTL 0x00d3 63 #define regHDP_MISC_CNTL_BASE_IDX 0 64 #define regHDP_MEM_POWER_CTRL 0x00d4 65 #define regHDP_MEM_POWER_CTRL_BASE_IDX 0 66 #define regHDP_MMHUB_CNTL 0x00d5 67 #define regHDP_MMHUB_CNTL_BASE_IDX 0 68 #define regHDP_VERSION 0x00d7 69 #define regHDP_VERSION_BASE_IDX 0 70 #define regHDP_CLK_CNTL 0x00d8 71 #define regHDP_CLK_CNTL_BASE_IDX 0 72 #define regHDP_MEMIO_CNTL 0x00f6 73 #define regHDP_MEMIO_CNTL_BASE_IDX 0 74 #define regHDP_MEMIO_ADDR 0x00f7 75 #define regHDP_MEMIO_ADDR_BASE_IDX 0 76 #define regHDP_MEMIO_STATUS 0x00f8 77 #define regHDP_MEMIO_STATUS_BASE_IDX 0 78 #define regHDP_MEMIO_WR_DATA 0x00f9 79 #define regHDP_MEMIO_WR_DATA_BASE_IDX 0 80 #define regHDP_MEMIO_RD_DATA 0x00fa 81 #define regHDP_MEMIO_RD_DATA_BASE_IDX 0 82 #define regHDP_XDP_DIRECT2HDP_FIRST 0x0100 83 #define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 84 #define regHDP_XDP_D2H_FLUSH 0x0101 85 #define regHDP_XDP_D2H_FLUSH_BASE_IDX 0 86 #define regHDP_XDP_D2H_BAR_UPDATE 0x0102 87 #define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 88 #define regHDP_XDP_D2H_RSVD_3 0x0103 89 #define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0 90 #define regHDP_XDP_D2H_RSVD_4 0x0104 91 #define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0 92 #define regHDP_XDP_D2H_RSVD_5 0x0105 93 #define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0 94 #define regHDP_XDP_D2H_RSVD_6 0x0106 95 #define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0 96 #define regHDP_XDP_D2H_RSVD_7 0x0107 97 #define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0 98 #define regHDP_XDP_D2H_RSVD_8 0x0108 99 #define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0 100 #define regHDP_XDP_D2H_RSVD_9 0x0109 101 #define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0 102 #define regHDP_XDP_D2H_RSVD_10 0x010a 103 #define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0 104 #define regHDP_XDP_D2H_RSVD_11 0x010b 105 #define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0 106 #define regHDP_XDP_D2H_RSVD_12 0x010c 107 #define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0 108 #define regHDP_XDP_D2H_RSVD_13 0x010d 109 #define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0 110 #define regHDP_XDP_D2H_RSVD_14 0x010e 111 #define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0 112 #define regHDP_XDP_D2H_RSVD_15 0x010f 113 #define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0 114 #define regHDP_XDP_D2H_RSVD_16 0x0110 115 #define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0 116 #define regHDP_XDP_D2H_RSVD_17 0x0111 117 #define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0 118 #define regHDP_XDP_D2H_RSVD_18 0x0112 119 #define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0 120 #define regHDP_XDP_D2H_RSVD_19 0x0113 121 #define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0 122 #define regHDP_XDP_D2H_RSVD_20 0x0114 123 #define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0 124 #define regHDP_XDP_D2H_RSVD_21 0x0115 125 #define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0 126 #define regHDP_XDP_D2H_RSVD_22 0x0116 127 #define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0 128 #define regHDP_XDP_D2H_RSVD_23 0x0117 129 #define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0 130 #define regHDP_XDP_D2H_RSVD_24 0x0118 131 #define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0 132 #define regHDP_XDP_D2H_RSVD_25 0x0119 133 #define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0 134 #define regHDP_XDP_D2H_RSVD_26 0x011a 135 #define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0 136 #define regHDP_XDP_D2H_RSVD_27 0x011b 137 #define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0 138 #define regHDP_XDP_D2H_RSVD_28 0x011c 139 #define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0 140 #define regHDP_XDP_D2H_RSVD_29 0x011d 141 #define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0 142 #define regHDP_XDP_D2H_RSVD_30 0x011e 143 #define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0 144 #define regHDP_XDP_D2H_RSVD_31 0x011f 145 #define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0 146 #define regHDP_XDP_D2H_RSVD_32 0x0120 147 #define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0 148 #define regHDP_XDP_D2H_RSVD_33 0x0121 149 #define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0 150 #define regHDP_XDP_D2H_RSVD_34 0x0122 151 #define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0 152 #define regHDP_XDP_DIRECT2HDP_LAST 0x0123 153 #define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 154 #define regHDP_XDP_P2P_BAR_CFG 0x0124 155 #define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 156 #define regHDP_XDP_P2P_MBX_OFFSET 0x0125 157 #define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 158 #define regHDP_XDP_P2P_MBX_ADDR0 0x0126 159 #define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 160 #define regHDP_XDP_P2P_MBX_ADDR1 0x0127 161 #define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 162 #define regHDP_XDP_P2P_MBX_ADDR2 0x0128 163 #define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 164 #define regHDP_XDP_P2P_MBX_ADDR3 0x0129 165 #define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 166 #define regHDP_XDP_P2P_MBX_ADDR4 0x012a 167 #define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 168 #define regHDP_XDP_P2P_MBX_ADDR5 0x012b 169 #define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 170 #define regHDP_XDP_P2P_MBX_ADDR6 0x012c 171 #define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 172 #define regHDP_XDP_HDP_MBX_MC_CFG 0x012d 173 #define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 174 #define regHDP_XDP_HDP_MC_CFG 0x012e 175 #define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0 176 #define regHDP_XDP_HST_CFG 0x012f 177 #define regHDP_XDP_HST_CFG_BASE_IDX 0 178 #define regHDP_XDP_HDP_IPH_CFG 0x0131 179 #define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 180 #define regHDP_XDP_P2P_BAR0 0x0134 181 #define regHDP_XDP_P2P_BAR0_BASE_IDX 0 182 #define regHDP_XDP_P2P_BAR1 0x0135 183 #define regHDP_XDP_P2P_BAR1_BASE_IDX 0 184 #define regHDP_XDP_P2P_BAR2 0x0136 185 #define regHDP_XDP_P2P_BAR2_BASE_IDX 0 186 #define regHDP_XDP_P2P_BAR3 0x0137 187 #define regHDP_XDP_P2P_BAR3_BASE_IDX 0 188 #define regHDP_XDP_P2P_BAR4 0x0138 189 #define regHDP_XDP_P2P_BAR4_BASE_IDX 0 190 #define regHDP_XDP_P2P_BAR5 0x0139 191 #define regHDP_XDP_P2P_BAR5_BASE_IDX 0 192 #define regHDP_XDP_P2P_BAR6 0x013a 193 #define regHDP_XDP_P2P_BAR6_BASE_IDX 0 194 #define regHDP_XDP_P2P_BAR7 0x013b 195 #define regHDP_XDP_P2P_BAR7_BASE_IDX 0 196 #define regHDP_XDP_FLUSH_ARMED_STS 0x013c 197 #define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 198 #define regHDP_XDP_FLUSH_CNTR0_STS 0x013d 199 #define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 200 #define regHDP_XDP_BUSY_STS 0x013e 201 #define regHDP_XDP_BUSY_STS_BASE_IDX 0 202 #define regHDP_XDP_STICKY 0x013f 203 #define regHDP_XDP_STICKY_BASE_IDX 0 204 #define regHDP_XDP_CHKN 0x0140 205 #define regHDP_XDP_CHKN_BASE_IDX 0 206 #define regHDP_XDP_BARS_ADDR_39_36 0x0144 207 #define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 208 #define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 209 #define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 210 #define regHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148 211 #define regHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 212 #define regHDP_XDP_GPU_IOV_VIOLATION_LOG2 0x0149 213 #define regHDP_XDP_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 214 #define regHDP_XDP_MMHUB_ERROR 0x014a 215 #define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0 216 217 #endif 218
