1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #ifndef __HCLGEVF_MAIN_H
5 #define __HCLGEVF_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/if_vlan.h>
8 #include <linux/types.h>
9 #include <net/devlink.h>
10 #include "hclge_mbx.h"
11 #include "hclgevf_cmd.h"
12 #include "hnae3.h"
13
14 #define HCLGEVF_MOD_VERSION "1.0"
15 #define HCLGEVF_DRIVER_NAME "hclgevf"
16
17 #define HCLGEVF_MAX_VLAN_ID 4095
18 #define HCLGEVF_MISC_VECTOR_NUM 0
19
20 #define HCLGEVF_INVALID_VPORT 0xffff
21 #define HCLGEVF_GENERAL_TASK_INTERVAL 5
22 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2
23
24 /* This number in actual depends upon the total number of VFs
25 * created by physical function. But the maximum number of
26 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
27 */
28 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1)
29
30 #define HCLGEVF_VECTOR_REG_BASE 0x20000
31 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
32 #define HCLGEVF_VECTOR_REG_OFFSET 0x4
33 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
34
35 /* bar registers for cmdq */
36 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
37 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
38 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
39 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
40 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
41 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
42 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701C
43 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
44 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
45 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
46
47 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
48 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
49
50 /* bar registers for common func */
51 #define HCLGEVF_GRO_EN_REG 0x28000
52 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008
53
54 /* bar registers for rcb */
55 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
56 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
57 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
58 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
59 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
60 #define HCLGEVF_RING_RX_TAIL_REG 0x80018
61 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C
62 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
63 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024
64 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
65 #define HCLGEVF_RING_RX_STASH_REG 0x80030
66 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
67 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
68 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
69 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
70 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
71 #define HCLGEVF_RING_TX_TC_REG 0x80050
72 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
73 #define HCLGEVF_RING_TX_TAIL_REG 0x80058
74 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C
75 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
76 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064
77 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
78 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
79 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
80 #define HCLGEVF_RING_EN_REG 0x80090
81
82 /* bar registers for tqp interrupt */
83 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
84 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100
85 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200
86 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300
87 #define HCLGEVF_TQP_INTR_RL_REG 0x20900
88
89 /* Vector0 interrupt CMDQ event source register(RW) */
90 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
91 /* Vector0 interrupt CMDQ event status register(RO) */
92 #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104
93 /* CMDQ register bits for RX event(=MBX event) */
94 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
95 /* RST register bits for RESET event */
96 #define HCLGEVF_VECTOR0_RST_INT_B 2
97
98 #define HCLGEVF_TQP_RESET_TRY_TIMES 10
99 /* Reset related Registers */
100 #define HCLGEVF_RST_ING 0x20C00
101 #define HCLGEVF_FUN_RST_ING_BIT BIT(0)
102 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5)
103 #define HCLGEVF_CORE_RST_ING_BIT BIT(6)
104 #define HCLGEVF_IMP_RST_ING_BIT BIT(7)
105 #define HCLGEVF_RST_ING_BITS \
106 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
107 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
108
109 #define HCLGEVF_VF_RST_ING 0x07008
110 #define HCLGEVF_VF_RST_ING_BIT BIT(16)
111
112 #define HCLGEVF_RSS_IND_TBL_SIZE 512
113 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff
114 #define HCLGEVF_RSS_KEY_SIZE 40
115 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0
116 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1
117 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
118 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf
119
120 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
121 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
122 #define HCLGEVF_D_PORT_BIT BIT(0)
123 #define HCLGEVF_S_PORT_BIT BIT(1)
124 #define HCLGEVF_D_IP_BIT BIT(2)
125 #define HCLGEVF_S_IP_BIT BIT(3)
126 #define HCLGEVF_V_TAG_BIT BIT(4)
127 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \
128 (HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT)
129
130 #define HCLGEVF_MAC_MAX_FRAME 9728
131
132 #define HCLGEVF_STATS_TIMER_INTERVAL 36U
133
134 enum hclgevf_evt_cause {
135 HCLGEVF_VECTOR0_EVENT_RST,
136 HCLGEVF_VECTOR0_EVENT_MBX,
137 HCLGEVF_VECTOR0_EVENT_OTHER,
138 };
139
140 /* states of hclgevf device & tasks */
141 enum hclgevf_states {
142 /* device states */
143 HCLGEVF_STATE_DOWN,
144 HCLGEVF_STATE_DISABLED,
145 HCLGEVF_STATE_IRQ_INITED,
146 HCLGEVF_STATE_REMOVING,
147 HCLGEVF_STATE_NIC_REGISTERED,
148 HCLGEVF_STATE_ROCE_REGISTERED,
149 HCLGEVF_STATE_SERVICE_INITED,
150 /* task states */
151 HCLGEVF_STATE_RST_SERVICE_SCHED,
152 HCLGEVF_STATE_RST_HANDLING,
153 HCLGEVF_STATE_MBX_SERVICE_SCHED,
154 HCLGEVF_STATE_MBX_HANDLING,
155 HCLGEVF_STATE_CMD_DISABLE,
156 HCLGEVF_STATE_LINK_UPDATING,
157 HCLGEVF_STATE_PROMISC_CHANGED,
158 HCLGEVF_STATE_RST_FAIL,
159 HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
160 };
161
162 struct hclgevf_mac {
163 u8 media_type;
164 u8 module_type;
165 u8 mac_addr[ETH_ALEN];
166 int link;
167 u8 duplex;
168 u32 speed;
169 u64 supported;
170 u64 advertising;
171 };
172
173 struct hclgevf_hw {
174 void __iomem *io_base;
175 void __iomem *mem_base;
176 int num_vec;
177 struct hclgevf_cmq cmq;
178 struct hclgevf_mac mac;
179 void *hdev; /* hchgevf device it is part of */
180 };
181
182 /* TQP stats */
183 struct hlcgevf_tqp_stats {
184 /* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */
185 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
186 /* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */
187 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
188 };
189
190 struct hclgevf_tqp {
191 struct device *dev; /* device for DMA mapping */
192 struct hnae3_queue q;
193 struct hlcgevf_tqp_stats tqp_stats;
194 u16 index; /* global index in a NIC controller */
195
196 bool alloced;
197 };
198
199 struct hclgevf_cfg {
200 u8 tc_num;
201 u16 tqp_desc_num;
202 u16 rx_buf_len;
203 u8 phy_addr;
204 u8 media_type;
205 u8 mac_addr[ETH_ALEN];
206 u32 numa_node_map;
207 };
208
209 struct hclgevf_rss_tuple_cfg {
210 u8 ipv4_tcp_en;
211 u8 ipv4_udp_en;
212 u8 ipv4_sctp_en;
213 u8 ipv4_fragment_en;
214 u8 ipv6_tcp_en;
215 u8 ipv6_udp_en;
216 u8 ipv6_sctp_en;
217 u8 ipv6_fragment_en;
218 };
219
220 struct hclgevf_rss_cfg {
221 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
222 u32 hash_algo;
223 u32 rss_size;
224 u8 hw_tc_map;
225 /* shadow table */
226 u8 *rss_indirection_tbl;
227 struct hclgevf_rss_tuple_cfg rss_tuple_sets;
228 };
229
230 struct hclgevf_misc_vector {
231 u8 __iomem *addr;
232 int vector_irq;
233 char name[HNAE3_INT_NAME_LEN];
234 };
235
236 struct hclgevf_rst_stats {
237 u32 rst_cnt; /* the number of reset */
238 u32 vf_func_rst_cnt; /* the number of VF function reset */
239 u32 flr_rst_cnt; /* the number of FLR */
240 u32 vf_rst_cnt; /* the number of VF reset */
241 u32 rst_done_cnt; /* the number of reset completed */
242 u32 hw_rst_done_cnt; /* the number of HW reset completed */
243 u32 rst_fail_cnt; /* the number of VF reset fail */
244 };
245
246 enum HCLGEVF_MAC_ADDR_TYPE {
247 HCLGEVF_MAC_ADDR_UC,
248 HCLGEVF_MAC_ADDR_MC
249 };
250
251 enum HCLGEVF_MAC_NODE_STATE {
252 HCLGEVF_MAC_TO_ADD,
253 HCLGEVF_MAC_TO_DEL,
254 HCLGEVF_MAC_ACTIVE
255 };
256
257 struct hclgevf_mac_addr_node {
258 struct list_head node;
259 enum HCLGEVF_MAC_NODE_STATE state;
260 u8 mac_addr[ETH_ALEN];
261 };
262
263 struct hclgevf_mac_table_cfg {
264 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
265 struct list_head uc_mac_list;
266 struct list_head mc_mac_list;
267 };
268
269 struct hclgevf_dev {
270 struct pci_dev *pdev;
271 struct hnae3_ae_dev *ae_dev;
272 struct hclgevf_hw hw;
273 struct hclgevf_misc_vector misc_vector;
274 struct hclgevf_rss_cfg rss_cfg;
275 unsigned long state;
276 unsigned long flr_state;
277 unsigned long default_reset_request;
278 unsigned long last_reset_time;
279 enum hnae3_reset_type reset_level;
280 unsigned long reset_pending;
281 enum hnae3_reset_type reset_type;
282
283 #define HCLGEVF_RESET_REQUESTED 0
284 #define HCLGEVF_RESET_PENDING 1
285 unsigned long reset_state; /* requested, pending */
286 struct hclgevf_rst_stats rst_stats;
287 u32 reset_attempts;
288 struct semaphore reset_sem; /* protect reset process */
289
290 u32 fw_version;
291 u16 mbx_api_version;
292 u16 num_tqps; /* num task queue pairs of this VF */
293
294 u16 alloc_rss_size; /* allocated RSS task queue */
295 u16 rss_size_max; /* HW defined max RSS task queue */
296
297 u16 num_alloc_vport; /* num vports this driver supports */
298 u32 numa_node_mask;
299 u16 rx_buf_len;
300 u16 num_tx_desc; /* desc num of per tx queue */
301 u16 num_rx_desc; /* desc num of per rx queue */
302 u8 hw_tc_map;
303 u8 has_pf_mac;
304
305 u16 num_msi;
306 u16 num_msi_left;
307 u16 num_msi_used;
308 u16 num_nic_msix; /* Num of nic vectors for this VF */
309 u16 num_roce_msix; /* Num of roce vectors for this VF */
310 u16 roce_base_msix_offset;
311 int roce_base_vector;
312 u32 base_msi_vector;
313 u16 *vector_status;
314 int *vector_irq;
315
316 bool gro_en;
317
318 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
319
320 struct hclgevf_mac_table_cfg mac_table;
321
322 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
323 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
324
325 struct delayed_work service_task;
326
327 struct hclgevf_tqp *htqp;
328
329 struct hnae3_handle nic;
330 struct hnae3_handle roce;
331
332 struct hnae3_client *nic_client;
333 struct hnae3_client *roce_client;
334 u32 flag;
335 unsigned long serv_processed_cnt;
336 unsigned long last_serv_processed;
337
338 struct devlink *devlink;
339 };
340
hclgevf_is_reset_pending(struct hclgevf_dev * hdev)341 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
342 {
343 return !!hdev->reset_pending;
344 }
345
346 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
347 struct hclge_vf_to_pf_msg *send_msg, bool need_resp,
348 u8 *resp_data, u16 resp_len);
349 void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
350 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
351
352 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
353 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
354 u8 duplex);
355 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
356 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
357 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
358 u8 *port_base_vlan_info, u8 data_size);
359 #endif
360
