1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 #ifndef _HALMAC_88XX_CFG_H_ 15 #define _HALMAC_88XX_CFG_H_ 16 17 #include "../halmac_2_platform.h" 18 #include "../halmac_type.h" 19 #include "../halmac_api.h" 20 #include "../halmac_bit2.h" 21 #include "../halmac_reg2.h" 22 #include "../halmac_pwr_seq_cmd.h" 23 #include "halmac_func_88xx.h" 24 #include "halmac_api_88xx.h" 25 #include "halmac_api_88xx_usb.h" 26 #include "halmac_api_88xx_pcie.h" 27 #include "halmac_api_88xx_sdio.h" 28 29 #define HALMAC_SVN_VER_88XX "13359M" 30 31 #define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */ 32 /* For halmac_api num change or prototype change, increment prototype version. 33 * Otherwise, increase minor version 34 */ 35 #define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* prototype version */ 36 #define HALMAC_MINOR_VER_88XX 0x0005 /* minor version */ 37 #define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */ 38 39 #define HALMAC_C2H_DATA_OFFSET_88XX 10 40 #define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8 41 #define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8 42 #define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768 43 44 #define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/ 45 #define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/ 46 #define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX \ 47 12 /*Fw config parameter cmd size, each 12 byte*/ 48 49 #define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8 50 #define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */ 51 52 #define HALMAC_NLO_INFO_SIZE_88XX 1024 53 54 /* Download FW */ 55 #define HALMAC_FW_SIZE_MAX_88XX 0x40000 56 #define HALMAC_FWHDR_SIZE_88XX 64 57 #define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8 58 #define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */ 59 /* Max dlfw size can not over 31K, because SDIO HW restriction */ 60 #define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00 61 62 #define DLFW_RESTORE_REG_NUM_88XX 9 63 #define ID_INFORM_DLEMEM_RDY 0x80 64 65 /* FW header information */ 66 #define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 67 #define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 68 #define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 69 #define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24 70 #define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28 71 #define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32 72 #define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36 73 #define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48 74 #define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52 75 #define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56 76 #define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60 77 78 /* HW memory address */ 79 #define HALMAC_OCPBASE_TXBUF_88XX 0x18780000 80 #define HALMAC_OCPBASE_DMEM_88XX 0x00200000 81 #define HALMAC_OCPBASE_IMEM_88XX 0x00000000 82 83 /* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that 84 * result from SDIO CLK sync to ana_clk fail 85 */ 86 #define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */ 87 88 /* MAC clock */ 89 #define HALMAC_MAC_CLOCK_88XX 80 /* 80M */ 90 91 /* H2C/C2H*/ 92 #define HALMAC_H2C_CMD_SIZE_88XX 32 93 #define HALMAC_H2C_CMD_HDR_SIZE_88XX 8 94 95 #define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60 96 97 /* Function enable */ 98 #define HALMAC_FUNCTION_ENABLE_88XX 0xDC 99 100 /* FIFO size & packet size */ 101 /* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */ 102 103 /* CFEND rate */ 104 #define HALMAC_BASIC_CFEND_RATE_88XX 0x5 105 #define HALMAC_STBC_CFEND_RATE_88XX 0xF 106 107 /* Response rate */ 108 #define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF 109 #define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 110 111 /* Spec SIFS */ 112 #define HALMAC_SIFS_CCK_PTCL_88XX 16 113 #define HALMAC_SIFS_OFDM_PTCL_88XX 16 114 115 /* Retry limit */ 116 #define HALMAC_LONG_RETRY_LIMIT_88XX 8 117 #define HALMAC_SHORT_RETRY_LIMIT_88XX 7 118 119 /* Slot, SIFS, PIFS time */ 120 #define HALMAC_SLOT_TIME_88XX 0x05 121 #define HALMAC_PIFS_TIME_88XX 0x19 122 #define HALMAC_SIFS_CCK_CTX_88XX 0xA 123 #define HALMAC_SIFS_OFDM_CTX_88XX 0xA 124 #define HALMAC_SIFS_CCK_TRX_88XX 0x10 125 #define HALMAC_SIFS_OFDM_TRX_88XX 0x10 126 127 /* TXOP limit */ 128 #define HALMAC_VO_TXOP_LIMIT_88XX 0x186 129 #define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC 130 131 /* NAV */ 132 #define HALMAC_RDG_NAV_88XX 0x05 133 #define HALMAC_TXOP_NAV_88XX 0x1B 134 135 /* TSF */ 136 #define HALMAC_CCK_RX_TSF_88XX 0x30 137 #define HALMAC_OFDM_RX_TSF_88XX 0x30 138 139 /* Send beacon related */ 140 #define HALMAC_TBTT_PROHIBIT_88XX 0x04 141 #define HALMAC_TBTT_HOLD_TIME_88XX 0x064 142 #define HALMAC_DRIVER_EARLY_INT_88XX 0x04 143 #define HALMAC_BEACON_DMA_TIM_88XX 0x02 144 145 /* RX filter */ 146 #define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF 147 #define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX 148 #define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF 149 #define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX 150 151 /* RCR */ 152 #define HALMAC_RCR_CONFIG_88XX 0xE400631E 153 154 /* Security config */ 155 #define HALMAC_SECURITY_CONFIG_88XX 0x01CC 156 157 /* CCK rate ACK timeout */ 158 #define HALMAC_ACK_TO_CCK_88XX 0x40 159 160 #endif 161
