1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __INC_HAL8188EPHYREG_H__ 8 #define __INC_HAL8188EPHYREG_H__ 9 /*--------------------------Define Parameters-------------------------------*/ 10 /* */ 11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 12 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 14 /* 3. RF register 0x00-2E */ 15 /* 4. Bit Mask for BB/RF register */ 16 /* 5. Other definition for BB/RF R/W */ 17 /* */ 18 19 /* 3. Page8(0x800) */ 20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ 21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 22 23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 24 #define rFPGA0_XA_HSSIParameter2 0x824 25 #define rFPGA0_XB_HSSIParameter1 0x828 26 #define rFPGA0_XB_HSSIParameter2 0x82c 27 28 #define rFPGA0_XA_LSSIParameter 0x840 29 #define rFPGA0_XB_LSSIParameter 0x844 30 31 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 32 #define rFPGA0_XCD_SwitchControl 0x85c 33 34 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 35 #define rFPGA0_XB_RFInterfaceOE 0x864 36 37 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ 38 #define rFPGA0_XCD_RFInterfaceSW 0x874 39 40 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 41 42 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 43 #define rFPGA0_XB_LSSIReadBack 0x8a4 44 45 #define TransceiverA_HSPI_Readback 0x8b8 46 #define TransceiverB_HSPI_Readback 0x8bc 47 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 48 49 /* 4. Page9(0x900) */ 50 /* RF mode & OFDM TxSC RF BW Setting?? */ 51 #define rFPGA1_RFMOD 0x900 52 53 /* 5. PageA(0xA00) */ 54 /* Set Control channel to upper or lower - required only for 40MHz */ 55 #define rCCK0_System 0xa00 56 57 /* */ 58 /* PageB(0xB00) */ 59 /* */ 60 #define rConfig_AntA 0xb68 61 #define rConfig_AntB 0xb6c 62 63 /* */ 64 /* 6. PageC(0xC00) */ 65 /* */ 66 #define rOFDM0_TRxPathEnable 0xc04 67 #define rOFDM0_TRMuxPar 0xc08 68 69 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 70 #define rOFDM0_XARxAFE 0xc10 71 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 72 #define rOFDM0_XBRxAFE 0xc18 73 #define rOFDM0_XBRxIQImbalance 0xc1c 74 75 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 76 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 77 78 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 79 #define rOFDM0_XAAGCCore2 0xc54 80 #define rOFDM0_XBAGCCore1 0xc58 81 #define rOFDM0_XBAGCCore2 0xc5c 82 83 #define rOFDM0_AGCRSSITable 0xc78 84 85 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 86 #define rOFDM0_XATxAFE 0xc84 87 #define rOFDM0_XBTxIQImbalance 0xc88 88 #define rOFDM0_XBTxAFE 0xc8c 89 #define rOFDM0_XCTxAFE 0xc94 90 #define rOFDM0_XDTxAFE 0xc9c 91 92 #define rOFDM0_RxIQExtAnta 0xca0 93 94 /* */ 95 /* 7. PageD(0xD00) */ 96 /* */ 97 #define rOFDM1_LSTF 0xd00 98 99 /* */ 100 /* 8. PageE(0xE00) */ 101 /* */ 102 #define rTxAGC_A_Rate18_06 0xe00 103 #define rTxAGC_A_Rate54_24 0xe04 104 #define rTxAGC_A_CCK1_Mcs32 0xe08 105 #define rTxAGC_A_Mcs03_Mcs00 0xe10 106 #define rTxAGC_A_Mcs07_Mcs04 0xe14 107 #define rTxAGC_A_Mcs11_Mcs08 0xe18 108 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 109 110 #define rTxAGC_B_Rate18_06 0x830 111 #define rTxAGC_B_Rate54_24 0x834 112 #define rTxAGC_B_CCK1_55_Mcs32 0x838 113 #define rTxAGC_B_Mcs03_Mcs00 0x83c 114 #define rTxAGC_B_Mcs07_Mcs04 0x848 115 #define rTxAGC_B_Mcs11_Mcs08 0x84c 116 #define rTxAGC_B_Mcs15_Mcs12 0x868 117 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 118 119 #define rFPGA0_IQK 0xe28 120 #define rTx_IQK_Tone_A 0xe30 121 #define rRx_IQK_Tone_A 0xe34 122 #define rTx_IQK_PI_A 0xe38 123 #define rRx_IQK_PI_A 0xe3c 124 125 #define rTx_IQK 0xe40 126 #define rRx_IQK 0xe44 127 #define rIQK_AGC_Pts 0xe48 128 #define rIQK_AGC_Rsp 0xe4c 129 #define rIQK_AGC_Cont 0xe60 130 131 #define rBlue_Tooth 0xe6c 132 #define rRx_Wait_CCA 0xe70 133 #define rTx_CCK_RFON 0xe74 134 #define rTx_CCK_BBON 0xe78 135 #define rTx_OFDM_RFON 0xe7c 136 #define rTx_OFDM_BBON 0xe80 137 #define rTx_To_Rx 0xe84 138 #define rTx_To_Tx 0xe88 139 #define rRx_CCK 0xe8c 140 141 #define rTx_Power_Before_IQK_A 0xe94 142 #define rTx_Power_After_IQK_A 0xe9c 143 144 #define rRx_Power_Before_IQK_A_2 0xea4 145 #define rRx_Power_After_IQK_A_2 0xeac 146 147 #define rTx_Power_Before_IQK_B 0xeb4 148 #define rTx_Power_After_IQK_B 0xebc 149 150 #define rRx_Power_Before_IQK_B_2 0xec4 151 #define rRx_Power_After_IQK_B_2 0xecc 152 153 #define rRx_OFDM 0xed0 154 #define rRx_Wait_RIFS 0xed4 155 #define rRx_TO_Rx 0xed8 156 #define rStandby 0xedc 157 #define rSleep 0xee0 158 #define rPMPD_ANAEN 0xeec 159 160 /* */ 161 /* RL6052 Register definition */ 162 /* */ 163 #define RF_AC 0x00 /* */ 164 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 165 #define RF_T_METER_88E 0x42 /* */ 166 #define RF_RCK_OS 0x30 /* RF TX PA control */ 167 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 168 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 169 #define RF_WE_LUT 0xEF 170 171 /* */ 172 /* Bit Mask */ 173 /* */ 174 175 /* 2. Page8(0x800) */ 176 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 177 #define bCCKEn 0x1000000 178 #define bOFDMEn 0x2000000 179 180 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 181 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 182 #define bLSSIReadBackData 0xfffff /* T65 RF */ 183 184 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */ 185 186 /* */ 187 /* Other Definition */ 188 /* */ 189 190 /* for PutRegsetting & GetRegSetting BitMask */ 191 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 192 #define bMaskByte1 0xff00 193 #define bMaskByte3 0xff000000 194 #define bMaskDWord 0xffffffff 195 #define bMask12Bits 0xfff 196 #define bMaskOFDM_D 0xffc00000 197 198 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 199 #define bRFRegOffsetMask 0xfffff 200 201 #endif 202
