1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __INC_HAL8188EPHYREG_H__ 8 #define __INC_HAL8188EPHYREG_H__ 9 /*--------------------------Define Parameters-------------------------------*/ 10 /* */ 11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 12 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 14 /* 3. RF register 0x00-2E */ 15 /* 4. Bit Mask for BB/RF register */ 16 /* 5. Other definition for BB/RF R/W */ 17 /* */ 18 19 20 /* */ 21 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 22 /* 1. Page1(0x100) */ 23 /* */ 24 #define rPMAC_Reset 0x100 25 #define rPMAC_TxStart 0x104 26 #define rPMAC_TxLegacySIG 0x108 27 #define rPMAC_TxHTSIG1 0x10c 28 #define rPMAC_TxHTSIG2 0x110 29 #define rPMAC_PHYDebug 0x114 30 #define rPMAC_TxPacketNum 0x118 31 #define rPMAC_TxIdle 0x11c 32 #define rPMAC_TxMACHeader0 0x120 33 #define rPMAC_TxMACHeader1 0x124 34 #define rPMAC_TxMACHeader2 0x128 35 #define rPMAC_TxMACHeader3 0x12c 36 #define rPMAC_TxMACHeader4 0x130 37 #define rPMAC_TxMACHeader5 0x134 38 #define rPMAC_TxDataType 0x138 39 #define rPMAC_TxRandomSeed 0x13c 40 #define rPMAC_CCKPLCPPreamble 0x140 41 #define rPMAC_CCKPLCPHeader 0x144 42 #define rPMAC_CCKCRC16 0x148 43 #define rPMAC_OFDMRxCRC32OK 0x170 44 #define rPMAC_OFDMRxCRC32Er 0x174 45 #define rPMAC_OFDMRxParityEr 0x178 46 #define rPMAC_OFDMRxCRC8Er 0x17c 47 #define rPMAC_CCKCRxRC16Er 0x180 48 #define rPMAC_CCKCRxRC32Er 0x184 49 #define rPMAC_CCKCRxRC32OK 0x188 50 #define rPMAC_TxStatus 0x18c 51 52 /* 2. Page2(0x200) */ 53 /* The following two definition are only used for USB interface. */ 54 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */ 55 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */ 56 57 /* 3. Page8(0x800) */ 58 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ 59 60 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 61 #define rFPGA0_PSDFunction 0x808 62 63 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 64 65 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 66 #define rFPGA0_RFTiming2 0x814 67 68 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 69 #define rFPGA0_XA_HSSIParameter2 0x824 70 #define rFPGA0_XB_HSSIParameter1 0x828 71 #define rFPGA0_XB_HSSIParameter2 0x82c 72 73 #define rFPGA0_XA_LSSIParameter 0x840 74 #define rFPGA0_XB_LSSIParameter 0x844 75 76 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 77 #define rFPGA0_RFSleepUpParameter 0x854 78 79 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 80 #define rFPGA0_XCD_SwitchControl 0x85c 81 82 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 83 #define rFPGA0_XB_RFInterfaceOE 0x864 84 85 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ 86 #define rFPGA0_XCD_RFInterfaceSW 0x874 87 88 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 89 #define rFPGA0_XCD_RFParameter 0x87c 90 91 /* Crystal cap setting RF-R/W protection for parameter4?? */ 92 #define rFPGA0_AnalogParameter1 0x880 93 #define rFPGA0_AnalogParameter2 0x884 94 #define rFPGA0_AnalogParameter3 0x888 95 /* enable ad/da clock1 for dual-phy */ 96 #define rFPGA0_AdDaClockEn 0x888 97 #define rFPGA0_AnalogParameter4 0x88c 98 99 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 100 #define rFPGA0_XB_LSSIReadBack 0x8a4 101 #define rFPGA0_XC_LSSIReadBack 0x8a8 102 #define rFPGA0_XD_LSSIReadBack 0x8ac 103 104 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 105 /* Transceiver A HSPI Readback */ 106 #define TransceiverA_HSPI_Readback 0x8b8 107 /* Transceiver B HSPI Readback */ 108 #define TransceiverB_HSPI_Readback 0x8bc 109 /* Useless now RF Interface Readback Value */ 110 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 111 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 112 113 /* 4. Page9(0x900) */ 114 /* RF mode & OFDM TxSC RF BW Setting?? */ 115 #define rFPGA1_RFMOD 0x900 116 117 #define rFPGA1_TxBlock 0x904 /* Useless now */ 118 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 119 #define rFPGA1_TxInfo 0x90c /* Useless now Status report */ 120 121 /* 5. PageA(0xA00) */ 122 /* Set Control channel to upper or lower - required only for 40MHz */ 123 #define rCCK0_System 0xa00 124 125 /* Disable init gain now Select RX path by RSSI */ 126 #define rCCK0_AFESetting 0xa04 127 /* Disable init gain now Init gain */ 128 #define rCCK0_CCA 0xa08 129 130 /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, 131 * RX LNA Threshold useless now. Not the same as 90 series 132 */ 133 #define rCCK0_RxAGC1 0xa0c 134 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 135 136 #define rCCK0_RxHP 0xa14 137 138 /* Timing recovery & Channel estimation threshold */ 139 #define rCCK0_DSPParameter1 0xa18 140 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 141 142 #define rCCK0_TxFilter1 0xa20 143 #define rCCK0_TxFilter2 0xa24 144 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 145 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */ 146 #define rCCK0_TRSSIReport 0xa50 147 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 148 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 149 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 150 151 /* */ 152 /* PageB(0xB00) */ 153 /* */ 154 #define rPdp_AntA 0xb00 155 #define rPdp_AntA_4 0xb04 156 #define rConfig_Pmpd_AntA 0xb28 157 #define rConfig_AntA 0xb68 158 #define rConfig_AntB 0xb6c 159 #define rPdp_AntB 0xb70 160 #define rPdp_AntB_4 0xb74 161 #define rConfig_Pmpd_AntB 0xb98 162 #define rAPK 0xbd8 163 164 /* */ 165 /* 6. PageC(0xC00) */ 166 /* */ 167 #define rOFDM0_LSTF 0xc00 168 169 #define rOFDM0_TRxPathEnable 0xc04 170 #define rOFDM0_TRMuxPar 0xc08 171 #define rOFDM0_TRSWIsolation 0xc0c 172 173 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 174 #define rOFDM0_XARxAFE 0xc10 175 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 176 #define rOFDM0_XBRxAFE 0xc18 177 #define rOFDM0_XBRxIQImbalance 0xc1c 178 #define rOFDM0_XCRxAFE 0xc20 179 #define rOFDM0_XCRxIQImbalance 0xc24 180 #define rOFDM0_XDRxAFE 0xc28 181 #define rOFDM0_XDRxIQImbalance 0xc2c 182 183 #define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/ 184 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 185 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 186 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 187 188 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 189 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 190 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 191 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 192 193 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 194 #define rOFDM0_XAAGCCore2 0xc54 195 #define rOFDM0_XBAGCCore1 0xc58 196 #define rOFDM0_XBAGCCore2 0xc5c 197 #define rOFDM0_XCAGCCore1 0xc60 198 #define rOFDM0_XCAGCCore2 0xc64 199 #define rOFDM0_XDAGCCore1 0xc68 200 #define rOFDM0_XDAGCCore2 0xc6c 201 202 #define rOFDM0_AGCParameter1 0xc70 203 #define rOFDM0_AGCParameter2 0xc74 204 #define rOFDM0_AGCRSSITable 0xc78 205 #define rOFDM0_HTSTFAGC 0xc7c 206 207 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 208 #define rOFDM0_XATxAFE 0xc84 209 #define rOFDM0_XBTxIQImbalance 0xc88 210 #define rOFDM0_XBTxAFE 0xc8c 211 #define rOFDM0_XCTxIQImbalance 0xc90 212 #define rOFDM0_XCTxAFE 0xc94 213 #define rOFDM0_XDTxIQImbalance 0xc98 214 #define rOFDM0_XDTxAFE 0xc9c 215 216 #define rOFDM0_RxIQExtAnta 0xca0 217 #define rOFDM0_TxCoeff1 0xca4 218 #define rOFDM0_TxCoeff2 0xca8 219 #define rOFDM0_TxCoeff3 0xcac 220 #define rOFDM0_TxCoeff4 0xcb0 221 #define rOFDM0_TxCoeff5 0xcb4 222 #define rOFDM0_TxCoeff6 0xcb8 223 #define rOFDM0_RxHPParameter 0xce0 224 #define rOFDM0_TxPseudoNoiseWgt 0xce4 225 #define rOFDM0_FrameSync 0xcf0 226 #define rOFDM0_DFSReport 0xcf4 227 228 229 /* */ 230 /* 7. PageD(0xD00) */ 231 /* */ 232 #define rOFDM1_LSTF 0xd00 233 #define rOFDM1_TRxPathEnable 0xd04 234 235 #define rOFDM1_CFO 0xd08 /* No setting now */ 236 #define rOFDM1_CSI1 0xd10 237 #define rOFDM1_SBD 0xd14 238 #define rOFDM1_CSI2 0xd18 239 #define rOFDM1_CFOTracking 0xd2c 240 #define rOFDM1_TRxMesaure1 0xd34 241 #define rOFDM1_IntfDet 0xd3c 242 #define rOFDM1_PseudoNoiseStateAB 0xd50 243 #define rOFDM1_PseudoNoiseStateCD 0xd54 244 #define rOFDM1_RxPseudoNoiseWgt 0xd58 245 246 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 247 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 248 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 249 250 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 251 #define rOFDM_ShortCFOCD 0xdb0 252 #define rOFDM_LongCFOAB 0xdb4 253 #define rOFDM_LongCFOCD 0xdb8 254 #define rOFDM_TailCFOAB 0xdbc 255 #define rOFDM_TailCFOCD 0xdc0 256 #define rOFDM_PWMeasure1 0xdc4 257 #define rOFDM_PWMeasure2 0xdc8 258 #define rOFDM_BWReport 0xdcc 259 #define rOFDM_AGCReport 0xdd0 260 #define rOFDM_RxSNR 0xdd4 261 #define rOFDM_RxEVMCSI 0xdd8 262 #define rOFDM_SIGReport 0xddc 263 264 265 /* */ 266 /* 8. PageE(0xE00) */ 267 /* */ 268 #define rTxAGC_A_Rate18_06 0xe00 269 #define rTxAGC_A_Rate54_24 0xe04 270 #define rTxAGC_A_CCK1_Mcs32 0xe08 271 #define rTxAGC_A_Mcs03_Mcs00 0xe10 272 #define rTxAGC_A_Mcs07_Mcs04 0xe14 273 #define rTxAGC_A_Mcs11_Mcs08 0xe18 274 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 275 276 #define rTxAGC_B_Rate18_06 0x830 277 #define rTxAGC_B_Rate54_24 0x834 278 #define rTxAGC_B_CCK1_55_Mcs32 0x838 279 #define rTxAGC_B_Mcs03_Mcs00 0x83c 280 #define rTxAGC_B_Mcs07_Mcs04 0x848 281 #define rTxAGC_B_Mcs11_Mcs08 0x84c 282 #define rTxAGC_B_Mcs15_Mcs12 0x868 283 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 284 285 #define rFPGA0_IQK 0xe28 286 #define rTx_IQK_Tone_A 0xe30 287 #define rRx_IQK_Tone_A 0xe34 288 #define rTx_IQK_PI_A 0xe38 289 #define rRx_IQK_PI_A 0xe3c 290 291 #define rTx_IQK 0xe40 292 #define rRx_IQK 0xe44 293 #define rIQK_AGC_Pts 0xe48 294 #define rIQK_AGC_Rsp 0xe4c 295 #define rTx_IQK_Tone_B 0xe50 296 #define rRx_IQK_Tone_B 0xe54 297 #define rTx_IQK_PI_B 0xe58 298 #define rRx_IQK_PI_B 0xe5c 299 #define rIQK_AGC_Cont 0xe60 300 301 #define rBlue_Tooth 0xe6c 302 #define rRx_Wait_CCA 0xe70 303 #define rTx_CCK_RFON 0xe74 304 #define rTx_CCK_BBON 0xe78 305 #define rTx_OFDM_RFON 0xe7c 306 #define rTx_OFDM_BBON 0xe80 307 #define rTx_To_Rx 0xe84 308 #define rTx_To_Tx 0xe88 309 #define rRx_CCK 0xe8c 310 311 #define rTx_Power_Before_IQK_A 0xe94 312 #define rTx_Power_After_IQK_A 0xe9c 313 314 #define rRx_Power_Before_IQK_A 0xea0 315 #define rRx_Power_Before_IQK_A_2 0xea4 316 #define rRx_Power_After_IQK_A 0xea8 317 #define rRx_Power_After_IQK_A_2 0xeac 318 319 #define rTx_Power_Before_IQK_B 0xeb4 320 #define rTx_Power_After_IQK_B 0xebc 321 322 #define rRx_Power_Before_IQK_B 0xec0 323 #define rRx_Power_Before_IQK_B_2 0xec4 324 #define rRx_Power_After_IQK_B 0xec8 325 #define rRx_Power_After_IQK_B_2 0xecc 326 327 #define rRx_OFDM 0xed0 328 #define rRx_Wait_RIFS 0xed4 329 #define rRx_TO_Rx 0xed8 330 #define rStandby 0xedc 331 #define rSleep 0xee0 332 #define rPMPD_ANAEN 0xeec 333 334 /* */ 335 /* 7. RF Register 0x00-0x2E (RF 8256) */ 336 /* RF-0222D 0x00-3F */ 337 /* */ 338 /* Zebra1 */ 339 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 340 #define rZebra1_TRxEnable1 0x1 341 #define rZebra1_TRxEnable2 0x2 342 #define rZebra1_AGC 0x4 343 #define rZebra1_ChargePump 0x5 344 #define rZebra1_Channel 0x7 /* RF channel switch */ 345 346 /* endif */ 347 #define rZebra1_TxGain 0x8 /* Useless now */ 348 #define rZebra1_TxLPF 0x9 349 #define rZebra1_RxLPF 0xb 350 #define rZebra1_RxHPFCorner 0xc 351 352 /* Zebra4 */ 353 #define rGlobalCtrl 0 /* Useless now */ 354 #define rRTL8256_TxLPF 19 355 #define rRTL8256_RxLPF 11 356 357 /* RTL8258 */ 358 #define rRTL8258_TxLPF 0x11 /* Useless now */ 359 #define rRTL8258_RxLPF 0x13 360 #define rRTL8258_RSSILPF 0xa 361 362 /* */ 363 /* RL6052 Register definition */ 364 /* */ 365 #define RF_AC 0x00 /* */ 366 367 #define RF_IQADJ_G1 0x01 /* */ 368 #define RF_IQADJ_G2 0x02 /* */ 369 370 #define RF_POW_TRSW 0x05 /* */ 371 372 #define RF_GAIN_RX 0x06 /* */ 373 #define RF_GAIN_TX 0x07 /* */ 374 375 #define RF_TXM_IDAC 0x08 /* */ 376 #define RF_IPA_G 0x09 /* */ 377 #define RF_TXBIAS_G 0x0A 378 #define RF_TXPA_AG 0x0B 379 #define RF_IPA_A 0x0C /* */ 380 #define RF_TXBIAS_A 0x0D 381 #define RF_BS_PA_APSET_G9_G11 0x0E 382 #define RF_BS_IQGEN 0x0F /* */ 383 384 #define RF_MODE1 0x10 /* */ 385 #define RF_MODE2 0x11 /* */ 386 387 #define RF_RX_AGC_HP 0x12 /* */ 388 #define RF_TX_AGC 0x13 /* */ 389 #define RF_BIAS 0x14 /* */ 390 #define RF_IPA 0x15 /* */ 391 #define RF_TXBIAS 0x16 392 #define RF_POW_ABILITY 0x17 /* */ 393 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 394 #define RF_TOP 0x19 /* */ 395 396 #define RF_RX_G1 0x1A /* */ 397 #define RF_RX_G2 0x1B /* */ 398 399 #define RF_RX_BB2 0x1C /* */ 400 #define RF_RX_BB1 0x1D /* */ 401 402 #define RF_RCK1 0x1E /* */ 403 #define RF_RCK2 0x1F /* */ 404 405 #define RF_TX_G1 0x20 /* */ 406 #define RF_TX_G2 0x21 /* */ 407 #define RF_TX_G3 0x22 /* */ 408 409 #define RF_TX_BB1 0x23 /* */ 410 411 #define RF_T_METER_92D 0x42 /* */ 412 #define RF_T_METER_88E 0x42 /* */ 413 #define RF_T_METER 0x24 /* */ 414 415 #define RF_SYN_G1 0x25 /* RF TX Power control */ 416 #define RF_SYN_G2 0x26 /* RF TX Power control */ 417 #define RF_SYN_G3 0x27 /* RF TX Power control */ 418 #define RF_SYN_G4 0x28 /* RF TX Power control */ 419 #define RF_SYN_G5 0x29 /* RF TX Power control */ 420 #define RF_SYN_G6 0x2A /* RF TX Power control */ 421 #define RF_SYN_G7 0x2B /* RF TX Power control */ 422 #define RF_SYN_G8 0x2C /* RF TX Power control */ 423 424 #define RF_RCK_OS 0x30 /* RF TX PA control */ 425 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 426 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 427 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 428 #define RF_TX_BIAS_A 0x35 429 #define RF_TX_BIAS_D 0x36 430 #define RF_LOBF_9 0x38 431 #define RF_RXRF_A3 0x3C /* */ 432 #define RF_TRSW 0x3F 433 434 #define RF_TXRF_A2 0x41 435 #define RF_TXPA_G4 0x46 436 #define RF_TXPA_A4 0x4B 437 #define RF_0x52 0x52 438 #define RF_WE_LUT 0xEF 439 440 441 /* */ 442 /* Bit Mask */ 443 /* */ 444 /* 1. Page1(0x100) */ 445 #define bBBResetB 0x100 /* Useless now? */ 446 #define bGlobalResetB 0x200 447 #define bOFDMTxStart 0x4 448 #define bCCKTxStart 0x8 449 #define bCRC32Debug 0x100 450 #define bPMACLoopback 0x10 451 #define bTxLSIG 0xffffff 452 #define bOFDMTxRate 0xf 453 #define bOFDMTxReserved 0x10 454 #define bOFDMTxLength 0x1ffe0 455 #define bOFDMTxParity 0x20000 456 #define bTxHTSIG1 0xffffff 457 #define bTxHTMCSRate 0x7f 458 #define bTxHTBW 0x80 459 #define bTxHTLength 0xffff00 460 #define bTxHTSIG2 0xffffff 461 #define bTxHTSmoothing 0x1 462 #define bTxHTSounding 0x2 463 #define bTxHTReserved 0x4 464 #define bTxHTAggreation 0x8 465 #define bTxHTSTBC 0x30 466 #define bTxHTAdvanceCoding 0x40 467 #define bTxHTShortGI 0x80 468 #define bTxHTNumberHT_LTF 0x300 469 #define bTxHTCRC8 0x3fc00 470 #define bCounterReset 0x10000 471 #define bNumOfOFDMTx 0xffff 472 #define bNumOfCCKTx 0xffff0000 473 #define bTxIdleInterval 0xffff 474 #define bOFDMService 0xffff0000 475 #define bTxMACHeader 0xffffffff 476 #define bTxDataInit 0xff 477 #define bTxHTMode 0x100 478 #define bTxDataType 0x30000 479 #define bTxRandomSeed 0xffffffff 480 #define bCCKTxPreamble 0x1 481 #define bCCKTxSFD 0xffff0000 482 #define bCCKTxSIG 0xff 483 #define bCCKTxService 0xff00 484 #define bCCKLengthExt 0x8000 485 #define bCCKTxLength 0xffff0000 486 #define bCCKTxCRC16 0xffff 487 #define bCCKTxStatus 0x1 488 #define bOFDMTxStatus 0x2 489 490 #define IS_BB_REG_OFFSET_92S(_Offset) \ 491 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 492 493 /* 2. Page8(0x800) */ 494 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 495 #define bJapanMode 0x2 496 #define bCCKTxSC 0x30 497 #define bCCKEn 0x1000000 498 #define bOFDMEn 0x2000000 499 500 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 501 #define bOFDMTxDACPhase 0x40000 502 #define bXATxAGC 0x3f 503 504 #define bAntennaSelect 0x0300 505 506 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 507 #define bXCTxAGC 0xf000 508 #define bXDTxAGC 0xf0000 509 510 #define bPAStart 0xf0000000 /* Useless now */ 511 #define bTRStart 0x00f00000 512 #define bRFStart 0x0000f000 513 #define bBBStart 0x000000f0 514 #define bBBCCKStart 0x0000000f 515 #define bPAEnd 0xf /* Reg0x814 */ 516 #define bTREnd 0x0f000000 517 #define bRFEnd 0x000f0000 518 #define bCCAMask 0x000000f0 /* T2R */ 519 #define bR2RCCAMask 0x00000f00 520 #define bHSSI_R2TDelay 0xf8000000 521 #define bHSSI_T2RDelay 0xf80000 522 #define bContTxHSSI 0x400 /* change gain at continue Tx */ 523 #define bIGFromCCK 0x200 524 #define bAGCAddress 0x3f 525 #define bRxHPTx 0x7000 526 #define bRxHPT2R 0x38000 527 #define bRxHPCCKIni 0xc0000 528 #define bAGCTxCode 0xc00000 529 #define bAGCRxCode 0x300000 530 531 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 532 #define b3WireDataLength 0x800 533 #define b3WireAddressLength 0x400 534 535 #define b3WireRFPowerDown 0x1 /* Useless now */ 536 #define b5GPAPEPolarity 0x40000000 537 #define b2GPAPEPolarity 0x80000000 538 #define bRFSW_TxDefaultAnt 0x3 539 #define bRFSW_TxOptionAnt 0x30 540 #define bRFSW_RxDefaultAnt 0x300 541 #define bRFSW_RxOptionAnt 0x3000 542 #define bRFSI_3WireData 0x1 543 #define bRFSI_3WireClock 0x2 544 #define bRFSI_3WireLoad 0x4 545 #define bRFSI_3WireRW 0x8 546 #define bRFSI_3Wire 0xf 547 548 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 549 550 #define bRFSI_TRSW 0x20 /* Useless now */ 551 #define bRFSI_TRSWB 0x40 552 #define bRFSI_ANTSW 0x100 553 #define bRFSI_ANTSWB 0x200 554 #define bRFSI_PAPE 0x400 555 #define bRFSI_PAPE5G 0x800 556 #define bBandSelect 0x1 557 #define bHTSIG2_GI 0x80 558 #define bHTSIG2_Smoothing 0x01 559 #define bHTSIG2_Sounding 0x02 560 #define bHTSIG2_Aggreaton 0x08 561 #define bHTSIG2_STBC 0x30 562 #define bHTSIG2_AdvCoding 0x40 563 #define bHTSIG2_NumOfHTLTF 0x300 564 #define bHTSIG2_CRC8 0x3fc 565 #define bHTSIG1_MCS 0x7f 566 #define bHTSIG1_BandWidth 0x80 567 #define bHTSIG1_HTLength 0xffff 568 #define bLSIG_Rate 0xf 569 #define bLSIG_Reserved 0x10 570 #define bLSIG_Length 0x1fffe 571 #define bLSIG_Parity 0x20 572 #define bCCKRxPhase 0x4 573 574 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 575 576 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 577 578 #define bLSSIReadBackData 0xfffff /* T65 RF */ 579 580 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 581 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 582 #define bRegulator0Standby 0x1 583 #define bRegulatorPLLStandby 0x2 584 #define bRegulator1Standby 0x4 585 #define bPLLPowerUp 0x8 586 #define bDPLLPowerUp 0x10 587 #define bDA10PowerUp 0x20 588 #define bAD7PowerUp 0x200 589 #define bDA6PowerUp 0x2000 590 #define bXtalPowerUp 0x4000 591 #define b40MDClkPowerUP 0x8000 592 #define bDA6DebugMode 0x20000 593 #define bDA6Swing 0x380000 594 595 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 596 #define bADClkPhase 0x4000000 597 598 #define b80MClkDelay 0x18000000 /* Useless */ 599 #define bAFEWatchDogEnable 0x20000000 600 601 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 602 #define bXtalCap01 0xc0000000 603 #define bXtalCap23 0x3 604 #define bXtalCap92x 0x0f000000 605 #define bXtalCap 0x0f000000 606 607 #define bIntDifClkEnable 0x400 /* Useless */ 608 #define bExtSigClkEnable 0x800 609 #define bBandgapMbiasPowerUp 0x10000 610 #define bAD11SHGain 0xc0000 611 #define bAD11InputRange 0x700000 612 #define bAD11OPCurrent 0x3800000 613 #define bIPathLoopback 0x4000000 614 #define bQPathLoopback 0x8000000 615 #define bAFELoopback 0x10000000 616 #define bDA10Swing 0x7e0 617 #define bDA10Reverse 0x800 618 #define bDAClkSource 0x1000 619 #define bAD7InputRange 0x6000 620 #define bAD7Gain 0x38000 621 #define bAD7OutputCMMode 0x40000 622 #define bAD7InputCMMode 0x380000 623 #define bAD7Current 0xc00000 624 #define bRegulatorAdjust 0x7000000 625 #define bAD11PowerUpAtTx 0x1 626 #define bDA10PSAtTx 0x10 627 #define bAD11PowerUpAtRx 0x100 628 #define bDA10PSAtRx 0x1000 629 #define bCCKRxAGCFormat 0x200 630 #define bPSDFFTSamplepPoint 0xc000 631 #define bPSDAverageNum 0x3000 632 #define bIQPathControl 0xc00 633 #define bPSDFreq 0x3ff 634 #define bPSDAntennaPath 0x30 635 #define bPSDIQSwitch 0x40 636 #define bPSDRxTrigger 0x400000 637 #define bPSDTxTrigger 0x80000000 638 #define bPSDSineToneScale 0x7f000000 639 #define bPSDReport 0xffff 640 641 /* 3. Page9(0x900) */ 642 #define bOFDMTxSC 0x30000000 /* Useless */ 643 #define bCCKTxOn 0x1 644 #define bOFDMTxOn 0x2 645 #define bDebugPage 0xfff /* reset debug page and HWord, LWord */ 646 #define bDebugItem 0xff /* reset debug page and LWord */ 647 #define bAntL 0x10 648 #define bAntNonHT 0x100 649 #define bAntHT1 0x1000 650 #define bAntHT2 0x10000 651 #define bAntHT1S1 0x100000 652 #define bAntNonHTS1 0x1000000 653 654 /* 4. PageA(0xA00) */ 655 #define bCCKBBMode 0x3 /* Useless */ 656 #define bCCKTxPowerSaving 0x80 657 #define bCCKRxPowerSaving 0x40 658 659 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */ 660 661 #define bCCKScramble 0x8 /* Useless */ 662 #define bCCKAntDiversity 0x8000 663 #define bCCKCarrierRecovery 0x4000 664 #define bCCKTxRate 0x3000 665 #define bCCKDCCancel 0x0800 666 #define bCCKISICancel 0x0400 667 #define bCCKMatchFilter 0x0200 668 #define bCCKEqualizer 0x0100 669 #define bCCKPreambleDetect 0x800000 670 #define bCCKFastFalseCCA 0x400000 671 #define bCCKChEstStart 0x300000 672 #define bCCKCCACount 0x080000 673 #define bCCKcs_lim 0x070000 674 #define bCCKBistMode 0x80000000 675 #define bCCKCCAMask 0x40000000 676 #define bCCKTxDACPhase 0x4 677 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 678 #define bCCKr_cp_mode0 0x0100 679 #define bCCKTxDCOffset 0xf0 680 #define bCCKRxDCOffset 0xf 681 #define bCCKCCAMode 0xc000 682 #define bCCKFalseCS_lim 0x3f00 683 #define bCCKCS_ratio 0xc00000 684 #define bCCKCorgBit_sel 0x300000 685 #define bCCKPD_lim 0x0f0000 686 #define bCCKNewCCA 0x80000000 687 #define bCCKRxHPofIG 0x8000 688 #define bCCKRxIG 0x7f00 689 #define bCCKLNAPolarity 0x800000 690 #define bCCKRx1stGain 0x7f0000 691 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 692 #define bCCKRxAGCSatLevel 0x1f000000 693 #define bCCKRxAGCSatCount 0xe0 694 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 695 #define bCCKFixedRxAGC 0x8000 696 #define bCCKAntennaPolarity 0x2000 697 #define bCCKTxFilterType 0x0c00 698 #define bCCKRxAGCReportType 0x0300 699 #define bCCKRxDAGCEn 0x80000000 700 #define bCCKRxDAGCPeriod 0x20000000 701 #define bCCKRxDAGCSatLevel 0x1f000000 702 #define bCCKTimingRecovery 0x800000 703 #define bCCKTxC0 0x3f0000 704 #define bCCKTxC1 0x3f000000 705 #define bCCKTxC2 0x3f 706 #define bCCKTxC3 0x3f00 707 #define bCCKTxC4 0x3f0000 708 #define bCCKTxC5 0x3f000000 709 #define bCCKTxC6 0x3f 710 #define bCCKTxC7 0x3f00 711 #define bCCKDebugPort 0xff0000 712 #define bCCKDACDebug 0x0f000000 713 #define bCCKFalseAlarmEnable 0x8000 714 #define bCCKFalseAlarmRead 0x4000 715 #define bCCKTRSSI 0x7f 716 #define bCCKRxAGCReport 0xfe 717 #define bCCKRxReport_AntSel 0x80000000 718 #define bCCKRxReport_MFOff 0x40000000 719 #define bCCKRxRxReport_SQLoss 0x20000000 720 #define bCCKRxReport_Pktloss 0x10000000 721 #define bCCKRxReport_Lockedbit 0x08000000 722 #define bCCKRxReport_RateError 0x04000000 723 #define bCCKRxReport_RxRate 0x03000000 724 #define bCCKRxFACounterLower 0xff 725 #define bCCKRxFACounterUpper 0xff000000 726 #define bCCKRxHPAGCStart 0xe000 727 #define bCCKRxHPAGCFinal 0x1c00 728 #define bCCKRxFalseAlarmEnable 0x8000 729 #define bCCKFACounterFreeze 0x4000 730 #define bCCKTxPathSel 0x10000000 731 #define bCCKDefaultRxPath 0xc000000 732 #define bCCKOptionRxPath 0x3000000 733 734 /* 5. PageC(0xC00) */ 735 #define bNumOfSTF 0x3 /* Useless */ 736 #define bShift_L 0xc0 737 #define bGI_TH 0xc 738 #define bRxPathA 0x1 739 #define bRxPathB 0x2 740 #define bRxPathC 0x4 741 #define bRxPathD 0x8 742 #define bTxPathA 0x1 743 #define bTxPathB 0x2 744 #define bTxPathC 0x4 745 #define bTxPathD 0x8 746 #define bTRSSIFreq 0x200 747 #define bADCBackoff 0x3000 748 #define bDFIRBackoff 0xc000 749 #define bTRSSILatchPhase 0x10000 750 #define bRxIDCOffset 0xff 751 #define bRxQDCOffset 0xff00 752 #define bRxDFIRMode 0x1800000 753 #define bRxDCNFType 0xe000000 754 #define bRXIQImb_A 0x3ff 755 #define bRXIQImb_B 0xfc00 756 #define bRXIQImb_C 0x3f0000 757 #define bRXIQImb_D 0xffc00000 758 #define bDC_dc_Notch 0x60000 759 #define bRxNBINotch 0x1f000000 760 #define bPD_TH 0xf 761 #define bPD_TH_Opt2 0xc000 762 #define bPWED_TH 0x700 763 #define bIfMF_Win_L 0x800 764 #define bPD_Option 0x1000 765 #define bMF_Win_L 0xe000 766 #define bBW_Search_L 0x30000 767 #define bwin_enh_L 0xc0000 768 #define bBW_TH 0x700000 769 #define bED_TH2 0x3800000 770 #define bBW_option 0x4000000 771 #define bRatio_TH 0x18000000 772 #define bWindow_L 0xe0000000 773 #define bSBD_Option 0x1 774 #define bFrame_TH 0x1c 775 #define bFS_Option 0x60 776 #define bDC_Slope_check 0x80 777 #define bFGuard_Counter_DC_L 0xe00 778 #define bFrame_Weight_Short 0x7000 779 #define bSub_Tune 0xe00000 780 #define bFrame_DC_Length 0xe000000 781 #define bSBD_start_offset 0x30000000 782 #define bFrame_TH_2 0x7 783 #define bFrame_GI2_TH 0x38 784 #define bGI2_Sync_en 0x40 785 #define bSarch_Short_Early 0x300 786 #define bSarch_Short_Late 0xc00 787 #define bSarch_GI2_Late 0x70000 788 #define bCFOAntSum 0x1 789 #define bCFOAcc 0x2 790 #define bCFOStartOffset 0xc 791 #define bCFOLookBack 0x70 792 #define bCFOSumWeight 0x80 793 #define bDAGCEnable 0x10000 794 #define bTXIQImb_A 0x3ff 795 #define bTXIQImb_B 0xfc00 796 #define bTXIQImb_C 0x3f0000 797 #define bTXIQImb_D 0xffc00000 798 #define bTxIDCOffset 0xff 799 #define bTxQDCOffset 0xff00 800 #define bTxDFIRMode 0x10000 801 #define bTxPesudoNoiseOn 0x4000000 802 #define bTxPesudoNoise_A 0xff 803 #define bTxPesudoNoise_B 0xff00 804 #define bTxPesudoNoise_C 0xff0000 805 #define bTxPesudoNoise_D 0xff000000 806 #define bCCADropOption 0x20000 807 #define bCCADropThres 0xfff00000 808 #define bEDCCA_H 0xf 809 #define bEDCCA_L 0xf0 810 #define bLambda_ED 0x300 811 #define bRxInitialGain 0x7f 812 #define bRxAntDivEn 0x80 813 #define bRxAGCAddressForLNA 0x7f00 814 #define bRxHighPowerFlow 0x8000 815 #define bRxAGCFreezeThres 0xc0000 816 #define bRxFreezeStep_AGC1 0x300000 817 #define bRxFreezeStep_AGC2 0xc00000 818 #define bRxFreezeStep_AGC3 0x3000000 819 #define bRxFreezeStep_AGC0 0xc000000 820 #define bRxRssi_Cmp_En 0x10000000 821 #define bRxQuickAGCEn 0x20000000 822 #define bRxAGCFreezeThresMode 0x40000000 823 #define bRxOverFlowCheckType 0x80000000 824 #define bRxAGCShift 0x7f 825 #define bTRSW_Tri_Only 0x80 826 #define bPowerThres 0x300 827 #define bRxAGCEn 0x1 828 #define bRxAGCTogetherEn 0x2 829 #define bRxAGCMin 0x4 830 #define bRxHP_Ini 0x7 831 #define bRxHP_TRLNA 0x70 832 #define bRxHP_RSSI 0x700 833 #define bRxHP_BBP1 0x7000 834 #define bRxHP_BBP2 0x70000 835 #define bRxHP_BBP3 0x700000 836 #define bRSSI_H 0x7f0000 /* threshold for high power */ 837 #define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */ 838 #define bRxSettle_TRSW 0x7 839 #define bRxSettle_LNA 0x38 840 #define bRxSettle_RSSI 0x1c0 841 #define bRxSettle_BBP 0xe00 842 #define bRxSettle_RxHP 0x7000 843 #define bRxSettle_AntSW_RSSI 0x38000 844 #define bRxSettle_AntSW 0xc0000 845 #define bRxProcessTime_DAGC 0x300000 846 #define bRxSettle_HSSI 0x400000 847 #define bRxProcessTime_BBPPW 0x800000 848 #define bRxAntennaPowerShift 0x3000000 849 #define bRSSITableSelect 0xc000000 850 #define bRxHP_Final 0x7000000 851 #define bRxHTSettle_BBP 0x7 852 #define bRxHTSettle_HSSI 0x8 853 #define bRxHTSettle_RxHP 0x70 854 #define bRxHTSettle_BBPPW 0x80 855 #define bRxHTSettle_Idle 0x300 856 #define bRxHTSettle_Reserved 0x1c00 857 #define bRxHTRxHPEn 0x8000 858 #define bRxHTAGCFreezeThres 0x30000 859 #define bRxHTAGCTogetherEn 0x40000 860 #define bRxHTAGCMin 0x80000 861 #define bRxHTAGCEn 0x100000 862 #define bRxHTDAGCEn 0x200000 863 #define bRxHTRxHP_BBP 0x1c00000 864 #define bRxHTRxHP_Final 0xe0000000 865 #define bRxPWRatioTH 0x3 866 #define bRxPWRatioEn 0x4 867 #define bRxMFHold 0x3800 868 #define bRxPD_Delay_TH1 0x38 869 #define bRxPD_Delay_TH2 0x1c0 870 #define bRxPD_DC_COUNT_MAX 0x600 871 #define bRxPD_Delay_TH 0x8000 872 #define bRxProcess_Delay 0xf0000 873 #define bRxSearchrange_GI2_Early 0x700000 874 #define bRxFrame_Guard_Counter_L 0x3800000 875 #define bRxSGI_Guard_L 0xc000000 876 #define bRxSGI_Search_L 0x30000000 877 #define bRxSGI_TH 0xc0000000 878 #define bDFSCnt0 0xff 879 #define bDFSCnt1 0xff00 880 #define bDFSFlag 0xf0000 881 #define bMFWeightSum 0x300000 882 #define bMinIdxTH 0x7f000000 883 #define bDAFormat 0x40000 884 #define bTxChEmuEnable 0x01000000 885 #define bTRSWIsolation_A 0x7f 886 #define bTRSWIsolation_B 0x7f00 887 #define bTRSWIsolation_C 0x7f0000 888 #define bTRSWIsolation_D 0x7f000000 889 #define bExtLNAGain 0x7c00 890 891 /* 6. PageE(0xE00) */ 892 #define bSTBCEn 0x4 /* Useless */ 893 #define bAntennaMapping 0x10 894 #define bNss 0x20 895 #define bCFOAntSumD 0x200 896 #define bPHYCounterReset 0x8000000 897 #define bCFOReportGet 0x4000000 898 #define bOFDMContinueTx 0x10000000 899 #define bOFDMSingleCarrier 0x20000000 900 #define bOFDMSingleTone 0x40000000 901 #define bHTDetect 0x100 902 #define bCFOEn 0x10000 903 #define bCFOValue 0xfff00000 904 #define bSigTone_Re 0x3f 905 #define bSigTone_Im 0x7f00 906 #define bCounter_CCA 0xffff 907 #define bCounter_ParityFail 0xffff0000 908 #define bCounter_RateIllegal 0xffff 909 #define bCounter_CRC8Fail 0xffff0000 910 #define bCounter_MCSNoSupport 0xffff 911 #define bCounter_FastSync 0xffff 912 #define bShortCFO 0xfff 913 #define bShortCFOTLength 12 /* total */ 914 #define bShortCFOFLength 11 /* fraction */ 915 #define bLongCFO 0x7ff 916 #define bLongCFOTLength 11 917 #define bLongCFOFLength 11 918 #define bTailCFO 0x1fff 919 #define bTailCFOTLength 13 920 #define bTailCFOFLength 12 921 #define bmax_en_pwdB 0xffff 922 #define bCC_power_dB 0xffff0000 923 #define bnoise_pwdB 0xffff 924 #define bPowerMeasTLength 10 925 #define bPowerMeasFLength 3 926 #define bRx_HT_BW 0x1 927 #define bRxSC 0x6 928 #define bRx_HT 0x8 929 #define bNB_intf_det_on 0x1 930 #define bIntf_win_len_cfg 0x30 931 #define bNB_Intf_TH_cfg 0x1c0 932 #define bRFGain 0x3f 933 #define bTableSel 0x40 934 #define bTRSW 0x80 935 #define bRxSNR_A 0xff 936 #define bRxSNR_B 0xff00 937 #define bRxSNR_C 0xff0000 938 #define bRxSNR_D 0xff000000 939 #define bSNREVMTLength 8 940 #define bSNREVMFLength 1 941 #define bCSI1st 0xff 942 #define bCSI2nd 0xff00 943 #define bRxEVM1st 0xff0000 944 #define bRxEVM2nd 0xff000000 945 #define bSIGEVM 0xff 946 #define bPWDB 0xff00 947 #define bSGIEN 0x10000 948 949 #define bSFactorQAM1 0xf /* Useless */ 950 #define bSFactorQAM2 0xf0 951 #define bSFactorQAM3 0xf00 952 #define bSFactorQAM4 0xf000 953 #define bSFactorQAM5 0xf0000 954 #define bSFactorQAM6 0xf0000 955 #define bSFactorQAM7 0xf00000 956 #define bSFactorQAM8 0xf000000 957 #define bSFactorQAM9 0xf0000000 958 #define bCSIScheme 0x100000 959 960 #define bNoiseLvlTopSet 0x3 /* Useless */ 961 #define bChSmooth 0x4 962 #define bChSmoothCfg1 0x38 963 #define bChSmoothCfg2 0x1c0 964 #define bChSmoothCfg3 0xe00 965 #define bChSmoothCfg4 0x7000 966 #define bMRCMode 0x800000 967 #define bTHEVMCfg 0x7000000 968 969 #define bLoopFitType 0x1 /* Useless */ 970 #define bUpdCFO 0x40 971 #define bUpdCFOOffData 0x80 972 #define bAdvUpdCFO 0x100 973 #define bAdvTimeCtrl 0x800 974 #define bUpdClko 0x1000 975 #define bFC 0x6000 976 #define bTrackingMode 0x8000 977 #define bPhCmpEnable 0x10000 978 #define bUpdClkoLTF 0x20000 979 #define bComChCFO 0x40000 980 #define bCSIEstiMode 0x80000 981 #define bAdvUpdEqz 0x100000 982 #define bUChCfg 0x7000000 983 #define bUpdEqz 0x8000000 984 985 /* Rx Pseduo noise */ 986 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 987 #define bRxPesudoNoise_A 0xff 988 #define bRxPesudoNoise_B 0xff00 989 #define bRxPesudoNoise_C 0xff0000 990 #define bRxPesudoNoise_D 0xff000000 991 #define bPesudoNoiseState_A 0xffff 992 #define bPesudoNoiseState_B 0xffff0000 993 #define bPesudoNoiseState_C 0xffff 994 #define bPesudoNoiseState_D 0xffff0000 995 996 /* 7. RF Register */ 997 /* Zebra1 */ 998 #define bZebra1_HSSIEnable 0x8 /* Useless */ 999 #define bZebra1_TRxControl 0xc00 1000 #define bZebra1_TRxGainSetting 0x07f 1001 #define bZebra1_RxCorner 0xc00 1002 #define bZebra1_TxChargePump 0x38 1003 #define bZebra1_RxChargePump 0x7 1004 #define bZebra1_ChannelNum 0xf80 1005 #define bZebra1_TxLPFBW 0x400 1006 #define bZebra1_RxLPFBW 0x600 1007 1008 /* Zebra4 */ 1009 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1010 #define bRTL8256RegModeCtrl0 0x40 1011 #define bRTL8256_TxLPFBW 0x18 1012 #define bRTL8256_RxLPFBW 0x600 1013 1014 /* RTL8258 */ 1015 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1016 #define bRTL8258_RxLPFBW 0xc00 1017 #define bRTL8258_RSSILPFBW 0xc0 1018 1019 1020 /* */ 1021 /* Other Definition */ 1022 /* */ 1023 1024 /* byte endable for sb_write */ 1025 #define bByte0 0x1 /* Useless */ 1026 #define bByte1 0x2 1027 #define bByte2 0x4 1028 #define bByte3 0x8 1029 #define bWord0 0x3 1030 #define bWord1 0xc 1031 #define bDWord 0xf 1032 1033 /* for PutRegsetting & GetRegSetting BitMask */ 1034 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1035 #define bMaskByte1 0xff00 1036 #define bMaskByte2 0xff0000 1037 #define bMaskByte3 0xff000000 1038 #define bMaskHWord 0xffff0000 1039 #define bMaskLWord 0x0000ffff 1040 #define bMaskDWord 0xffffffff 1041 #define bMask12Bits 0xfff 1042 #define bMaskH4Bits 0xf0000000 1043 #define bMaskOFDM_D 0xffc00000 1044 #define bMaskCCK 0x3f3f3f3f 1045 1046 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 1047 #define bRFRegOffsetMask 0xfffff 1048 1049 #define bEnable 0x1 /* Useless */ 1050 #define bDisable 0x0 1051 1052 #define LeftAntenna 0x0 /* Useless */ 1053 #define RightAntenna 0x1 1054 1055 #define tCheckTxStatus 500 /* 500ms Useless */ 1056 #define tUpdateRxCounter 100 /* 100ms */ 1057 1058 #define rateCCK 0 /* Useless */ 1059 #define rateOFDM 1 1060 #define rateHT 2 1061 1062 /* define Register-End */ 1063 #define bPMAC_End 0x1ff /* Useless */ 1064 #define bFPGAPHY0_End 0x8ff 1065 #define bFPGAPHY1_End 0x9ff 1066 #define bCCKPHY0_End 0xaff 1067 #define bOFDMPHY0_End 0xcff 1068 #define bOFDMPHY1_End 0xdff 1069 1070 #define bPMACControl 0x0 /* Useless */ 1071 #define bWMACControl 0x1 1072 #define bWNICControl 0x2 1073 1074 #define PathA 0x0 /* Useless */ 1075 #define PathB 0x1 1076 #define PathC 0x2 1077 #define PathD 0x3 1078 1079 /*--------------------------Define Parameters-------------------------------*/ 1080 1081 1082 #endif 1083
