1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 *
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/spinlock.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/property.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/slab.h>
19 #include <linux/irq.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/bitops.h>
22 #include <linux/interrupt.h>
23
24 #define MPC8XXX_GPIO_PINS 32
25
26 #define GPIO_DIR 0x00
27 #define GPIO_ODR 0x04
28 #define GPIO_DAT 0x08
29 #define GPIO_IER 0x0c
30 #define GPIO_IMR 0x10
31 #define GPIO_ICR 0x14
32 #define GPIO_ICR2 0x18
33 #define GPIO_IBE 0x18
34
35 struct mpc8xxx_gpio_chip {
36 struct gpio_chip gc;
37 void __iomem *regs;
38 raw_spinlock_t lock;
39
40 int (*direction_output)(struct gpio_chip *chip,
41 unsigned offset, int value);
42
43 struct irq_domain *irq;
44 int irqn;
45 };
46
47 /*
48 * This hardware has a big endian bit assignment such that GPIO line 0 is
49 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
50 * This inline helper give the right bitmask for a certain line.
51 */
mpc_pin2mask(unsigned int offset)52 static inline u32 mpc_pin2mask(unsigned int offset)
53 {
54 return BIT(31 - offset);
55 }
56
57 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
58 * defined as output cannot be determined by reading GPDAT register,
59 * so we use shadow data register instead. The status of input pins
60 * is determined by reading GPDAT register.
61 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)62 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
63 {
64 u32 val;
65 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
66 u32 out_mask, out_shadow;
67
68 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
69 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
70 out_shadow = gc->bgpio_data & out_mask;
71
72 return !!((val | out_shadow) & mpc_pin2mask(gpio));
73 }
74
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)75 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
76 unsigned int gpio, int val)
77 {
78 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
79 /* GPIO 28..31 are input only on MPC5121 */
80 if (gpio >= 28)
81 return -EINVAL;
82
83 return mpc8xxx_gc->direction_output(gc, gpio, val);
84 }
85
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)86 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
87 unsigned int gpio, int val)
88 {
89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
90 /* GPIO 0..3 are input only on MPC5125 */
91 if (gpio <= 3)
92 return -EINVAL;
93
94 return mpc8xxx_gc->direction_output(gc, gpio, val);
95 }
96
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)97 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
98 {
99 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
100
101 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
102 return irq_create_mapping(mpc8xxx_gc->irq, offset);
103 else
104 return -ENXIO;
105 }
106
mpc8xxx_gpio_irq_cascade(int irq,void * data)107 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
108 {
109 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
110 struct gpio_chip *gc = &mpc8xxx_gc->gc;
111 unsigned long mask;
112 int i;
113
114 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
115 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
116 for_each_set_bit(i, &mask, 32)
117 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
118
119 return IRQ_HANDLED;
120 }
121
mpc8xxx_irq_unmask(struct irq_data * d)122 static void mpc8xxx_irq_unmask(struct irq_data *d)
123 {
124 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
125 struct gpio_chip *gc = &mpc8xxx_gc->gc;
126 unsigned long flags;
127
128 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
129
130 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
131 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
132 | mpc_pin2mask(irqd_to_hwirq(d)));
133
134 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
135 }
136
mpc8xxx_irq_mask(struct irq_data * d)137 static void mpc8xxx_irq_mask(struct irq_data *d)
138 {
139 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
140 struct gpio_chip *gc = &mpc8xxx_gc->gc;
141 unsigned long flags;
142
143 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
144
145 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
146 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
147 & ~mpc_pin2mask(irqd_to_hwirq(d)));
148
149 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
150 }
151
mpc8xxx_irq_ack(struct irq_data * d)152 static void mpc8xxx_irq_ack(struct irq_data *d)
153 {
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
155 struct gpio_chip *gc = &mpc8xxx_gc->gc;
156
157 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
158 mpc_pin2mask(irqd_to_hwirq(d)));
159 }
160
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)161 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
162 {
163 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
164 struct gpio_chip *gc = &mpc8xxx_gc->gc;
165 unsigned long flags;
166
167 switch (flow_type) {
168 case IRQ_TYPE_EDGE_FALLING:
169 case IRQ_TYPE_LEVEL_LOW:
170 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
171 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
172 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
173 | mpc_pin2mask(irqd_to_hwirq(d)));
174 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
175 break;
176
177 case IRQ_TYPE_EDGE_BOTH:
178 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
179 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
180 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
181 & ~mpc_pin2mask(irqd_to_hwirq(d)));
182 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
183 break;
184
185 default:
186 return -EINVAL;
187 }
188
189 return 0;
190 }
191
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)192 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
193 {
194 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
195 struct gpio_chip *gc = &mpc8xxx_gc->gc;
196 unsigned long gpio = irqd_to_hwirq(d);
197 void __iomem *reg;
198 unsigned int shift;
199 unsigned long flags;
200
201 if (gpio < 16) {
202 reg = mpc8xxx_gc->regs + GPIO_ICR;
203 shift = (15 - gpio) * 2;
204 } else {
205 reg = mpc8xxx_gc->regs + GPIO_ICR2;
206 shift = (15 - (gpio % 16)) * 2;
207 }
208
209 switch (flow_type) {
210 case IRQ_TYPE_EDGE_FALLING:
211 case IRQ_TYPE_LEVEL_LOW:
212 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
213 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
214 | (2 << shift));
215 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
216 break;
217
218 case IRQ_TYPE_EDGE_RISING:
219 case IRQ_TYPE_LEVEL_HIGH:
220 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
221 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
222 | (1 << shift));
223 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
224 break;
225
226 case IRQ_TYPE_EDGE_BOTH:
227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
228 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
229 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
230 break;
231
232 default:
233 return -EINVAL;
234 }
235
236 return 0;
237 }
238
239 static struct irq_chip mpc8xxx_irq_chip = {
240 .name = "mpc8xxx-gpio",
241 .irq_unmask = mpc8xxx_irq_unmask,
242 .irq_mask = mpc8xxx_irq_mask,
243 .irq_ack = mpc8xxx_irq_ack,
244 /* this might get overwritten in mpc8xxx_probe() */
245 .irq_set_type = mpc8xxx_irq_set_type,
246 };
247
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)248 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
249 irq_hw_number_t hwirq)
250 {
251 irq_set_chip_data(irq, h->host_data);
252 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
253
254 return 0;
255 }
256
257 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
258 .map = mpc8xxx_gpio_irq_map,
259 .xlate = irq_domain_xlate_twocell,
260 };
261
262 struct mpc8xxx_gpio_devtype {
263 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
264 int (*gpio_get)(struct gpio_chip *, unsigned int);
265 int (*irq_set_type)(struct irq_data *, unsigned int);
266 };
267
268 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
269 .gpio_dir_out = mpc5121_gpio_dir_out,
270 .irq_set_type = mpc512x_irq_set_type,
271 };
272
273 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
274 .gpio_dir_out = mpc5125_gpio_dir_out,
275 .irq_set_type = mpc512x_irq_set_type,
276 };
277
278 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
279 .gpio_get = mpc8572_gpio_get,
280 };
281
282 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
283 .irq_set_type = mpc8xxx_irq_set_type,
284 };
285
286 static const struct of_device_id mpc8xxx_gpio_ids[] = {
287 { .compatible = "fsl,mpc8349-gpio", },
288 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
289 { .compatible = "fsl,mpc8610-gpio", },
290 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
291 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
292 { .compatible = "fsl,pq3-gpio", },
293 { .compatible = "fsl,ls1028a-gpio", },
294 { .compatible = "fsl,ls1088a-gpio", },
295 { .compatible = "fsl,qoriq-gpio", },
296 {}
297 };
298
mpc8xxx_probe(struct platform_device * pdev)299 static int mpc8xxx_probe(struct platform_device *pdev)
300 {
301 struct device_node *np = pdev->dev.of_node;
302 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
303 struct gpio_chip *gc;
304 const struct mpc8xxx_gpio_devtype *devtype = NULL;
305 struct fwnode_handle *fwnode;
306 int ret;
307
308 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
309 if (!mpc8xxx_gc)
310 return -ENOMEM;
311
312 platform_set_drvdata(pdev, mpc8xxx_gc);
313
314 raw_spin_lock_init(&mpc8xxx_gc->lock);
315
316 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
317 if (IS_ERR(mpc8xxx_gc->regs))
318 return PTR_ERR(mpc8xxx_gc->regs);
319
320 gc = &mpc8xxx_gc->gc;
321 gc->parent = &pdev->dev;
322
323 if (device_property_read_bool(&pdev->dev, "little-endian")) {
324 ret = bgpio_init(gc, &pdev->dev, 4,
325 mpc8xxx_gc->regs + GPIO_DAT,
326 NULL, NULL,
327 mpc8xxx_gc->regs + GPIO_DIR, NULL,
328 BGPIOF_BIG_ENDIAN);
329 if (ret)
330 return ret;
331 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
332 } else {
333 ret = bgpio_init(gc, &pdev->dev, 4,
334 mpc8xxx_gc->regs + GPIO_DAT,
335 NULL, NULL,
336 mpc8xxx_gc->regs + GPIO_DIR, NULL,
337 BGPIOF_BIG_ENDIAN
338 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
339 if (ret)
340 return ret;
341 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
342 }
343
344 mpc8xxx_gc->direction_output = gc->direction_output;
345
346 devtype = device_get_match_data(&pdev->dev);
347 if (!devtype)
348 devtype = &mpc8xxx_gpio_devtype_default;
349
350 /*
351 * It's assumed that only a single type of gpio controller is available
352 * on the current machine, so overwriting global data is fine.
353 */
354 if (devtype->irq_set_type)
355 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
356
357 if (devtype->gpio_dir_out)
358 gc->direction_output = devtype->gpio_dir_out;
359 if (devtype->gpio_get)
360 gc->get = devtype->gpio_get;
361
362 gc->to_irq = mpc8xxx_gpio_to_irq;
363
364 /*
365 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
366 * the input enable of each individual GPIO port. When an individual
367 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
368 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
369 * the port value to the GPIO Data Register.
370 */
371 fwnode = dev_fwnode(&pdev->dev);
372 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
373 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
374 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
375 is_acpi_node(fwnode)) {
376 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
377 /* Also, latch state of GPIOs configured as output by bootloader. */
378 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) &
379 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
380 }
381
382 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
383 if (ret) {
384 dev_err(&pdev->dev,
385 "GPIO chip registration failed with status %d\n", ret);
386 return ret;
387 }
388
389 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
390 if (mpc8xxx_gc->irqn < 0)
391 return mpc8xxx_gc->irqn;
392
393 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
394 MPC8XXX_GPIO_PINS,
395 &mpc8xxx_gpio_irq_ops,
396 mpc8xxx_gc);
397
398 if (!mpc8xxx_gc->irq)
399 return 0;
400
401 /* ack and mask all irqs */
402 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
403 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
404
405 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
406 mpc8xxx_gpio_irq_cascade,
407 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
408 mpc8xxx_gc);
409 if (ret) {
410 dev_err(&pdev->dev,
411 "failed to devm_request_irq(%d), ret = %d\n",
412 mpc8xxx_gc->irqn, ret);
413 goto err;
414 }
415
416 return 0;
417 err:
418 irq_domain_remove(mpc8xxx_gc->irq);
419 return ret;
420 }
421
mpc8xxx_remove(struct platform_device * pdev)422 static int mpc8xxx_remove(struct platform_device *pdev)
423 {
424 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
425
426 if (mpc8xxx_gc->irq) {
427 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
428 irq_domain_remove(mpc8xxx_gc->irq);
429 }
430
431 return 0;
432 }
433
434 #ifdef CONFIG_ACPI
435 static const struct acpi_device_id gpio_acpi_ids[] = {
436 {"NXP0031",},
437 { }
438 };
439 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
440 #endif
441
442 static struct platform_driver mpc8xxx_plat_driver = {
443 .probe = mpc8xxx_probe,
444 .remove = mpc8xxx_remove,
445 .driver = {
446 .name = "gpio-mpc8xxx",
447 .of_match_table = mpc8xxx_gpio_ids,
448 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
449 },
450 };
451
mpc8xxx_init(void)452 static int __init mpc8xxx_init(void)
453 {
454 return platform_driver_register(&mpc8xxx_plat_driver);
455 }
456
457 arch_initcall(mpc8xxx_init);
458
