1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/kernel.h>
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include "soc15.h"
29 #include "soc15d.h"
30 #include "amdgpu_atomfirmware.h"
31
32 #include "gc/gc_9_0_offset.h"
33 #include "gc/gc_9_0_sh_mask.h"
34 #include "vega10_enum.h"
35 #include "hdp/hdp_4_0_offset.h"
36
37 #include "soc15_common.h"
38 #include "clearstate_gfx9.h"
39 #include "v9_structs.h"
40
41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
42
43 #define GFX9_NUM_GFX_RINGS 1
44 #define GFX9_MEC_HPD_SIZE 2048
45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
47
48 #define mmPWR_MISC_CNTL_STATUS 0x0183
49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
54
55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
61
62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
68
69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
75
76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
82
83 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
84 {
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
101 };
102
103 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
104 {
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
123 };
124
125 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
126 {
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
138 };
139
140 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
141 {
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
163 };
164
165 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
166 {
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
174 };
175
176 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
177 {
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
180 };
181
182 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
183 {
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
200 };
201
202 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
203 {
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
214 };
215
216 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
217 {
218 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
219 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
220 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
221 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
222 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
223 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
224 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
225 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
226 };
227
228 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
229 {
230 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
231 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
232 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
233 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
234 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
235 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
236 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
237 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
238 };
239
240 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
241 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
242 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
243
244 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
245 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
246 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
247 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
248 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
249 struct amdgpu_cu_info *cu_info);
250 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
251 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
252 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
253
gfx_v9_0_init_golden_registers(struct amdgpu_device * adev)254 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
255 {
256 switch (adev->asic_type) {
257 case CHIP_VEGA10:
258 soc15_program_register_sequence(adev,
259 golden_settings_gc_9_0,
260 ARRAY_SIZE(golden_settings_gc_9_0));
261 soc15_program_register_sequence(adev,
262 golden_settings_gc_9_0_vg10,
263 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
264 break;
265 case CHIP_VEGA12:
266 soc15_program_register_sequence(adev,
267 golden_settings_gc_9_2_1,
268 ARRAY_SIZE(golden_settings_gc_9_2_1));
269 soc15_program_register_sequence(adev,
270 golden_settings_gc_9_2_1_vg12,
271 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
272 break;
273 case CHIP_VEGA20:
274 soc15_program_register_sequence(adev,
275 golden_settings_gc_9_0,
276 ARRAY_SIZE(golden_settings_gc_9_0));
277 soc15_program_register_sequence(adev,
278 golden_settings_gc_9_0_vg20,
279 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
280 break;
281 case CHIP_RAVEN:
282 soc15_program_register_sequence(adev,
283 golden_settings_gc_9_1,
284 ARRAY_SIZE(golden_settings_gc_9_1));
285 soc15_program_register_sequence(adev,
286 golden_settings_gc_9_1_rv1,
287 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
288 break;
289 default:
290 break;
291 }
292
293 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
294 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
295 }
296
gfx_v9_0_scratch_init(struct amdgpu_device * adev)297 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
298 {
299 adev->gfx.scratch.num_reg = 8;
300 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
301 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
302 }
303
gfx_v9_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)304 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
305 bool wc, uint32_t reg, uint32_t val)
306 {
307 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
308 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
309 WRITE_DATA_DST_SEL(0) |
310 (wc ? WR_CONFIRM : 0));
311 amdgpu_ring_write(ring, reg);
312 amdgpu_ring_write(ring, 0);
313 amdgpu_ring_write(ring, val);
314 }
315
gfx_v9_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)316 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
317 int mem_space, int opt, uint32_t addr0,
318 uint32_t addr1, uint32_t ref, uint32_t mask,
319 uint32_t inv)
320 {
321 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
322 amdgpu_ring_write(ring,
323 /* memory (1) or register (0) */
324 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
325 WAIT_REG_MEM_OPERATION(opt) | /* wait */
326 WAIT_REG_MEM_FUNCTION(3) | /* equal */
327 WAIT_REG_MEM_ENGINE(eng_sel)));
328
329 if (mem_space)
330 BUG_ON(addr0 & 0x3); /* Dword align */
331 amdgpu_ring_write(ring, addr0);
332 amdgpu_ring_write(ring, addr1);
333 amdgpu_ring_write(ring, ref);
334 amdgpu_ring_write(ring, mask);
335 amdgpu_ring_write(ring, inv); /* poll interval */
336 }
337
gfx_v9_0_ring_test_ring(struct amdgpu_ring * ring)338 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
339 {
340 struct amdgpu_device *adev = ring->adev;
341 uint32_t scratch;
342 uint32_t tmp = 0;
343 unsigned i;
344 int r;
345
346 r = amdgpu_gfx_scratch_get(adev, &scratch);
347 if (r) {
348 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
349 return r;
350 }
351 WREG32(scratch, 0xCAFEDEAD);
352 r = amdgpu_ring_alloc(ring, 3);
353 if (r) {
354 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
355 ring->idx, r);
356 amdgpu_gfx_scratch_free(adev, scratch);
357 return r;
358 }
359 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
360 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
361 amdgpu_ring_write(ring, 0xDEADBEEF);
362 amdgpu_ring_commit(ring);
363
364 for (i = 0; i < adev->usec_timeout; i++) {
365 tmp = RREG32(scratch);
366 if (tmp == 0xDEADBEEF)
367 break;
368 DRM_UDELAY(1);
369 }
370 if (i < adev->usec_timeout) {
371 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
372 ring->idx, i);
373 } else {
374 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
375 ring->idx, scratch, tmp);
376 r = -EINVAL;
377 }
378 amdgpu_gfx_scratch_free(adev, scratch);
379 return r;
380 }
381
gfx_v9_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)382 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
383 {
384 struct amdgpu_device *adev = ring->adev;
385 struct amdgpu_ib ib;
386 struct dma_fence *f = NULL;
387
388 unsigned index;
389 uint64_t gpu_addr;
390 uint32_t tmp;
391 long r;
392
393 r = amdgpu_device_wb_get(adev, &index);
394 if (r) {
395 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
396 return r;
397 }
398
399 gpu_addr = adev->wb.gpu_addr + (index * 4);
400 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
401 memset(&ib, 0, sizeof(ib));
402 r = amdgpu_ib_get(adev, NULL, 16, &ib);
403 if (r) {
404 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
405 goto err1;
406 }
407 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
408 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
409 ib.ptr[2] = lower_32_bits(gpu_addr);
410 ib.ptr[3] = upper_32_bits(gpu_addr);
411 ib.ptr[4] = 0xDEADBEEF;
412 ib.length_dw = 5;
413
414 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
415 if (r)
416 goto err2;
417
418 r = dma_fence_wait_timeout(f, false, timeout);
419 if (r == 0) {
420 DRM_ERROR("amdgpu: IB test timed out.\n");
421 r = -ETIMEDOUT;
422 goto err2;
423 } else if (r < 0) {
424 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
425 goto err2;
426 }
427
428 tmp = adev->wb.wb[index];
429 if (tmp == 0xDEADBEEF) {
430 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
431 r = 0;
432 } else {
433 DRM_ERROR("ib test on ring %d failed\n", ring->idx);
434 r = -EINVAL;
435 }
436
437 err2:
438 amdgpu_ib_free(adev, &ib, NULL);
439 dma_fence_put(f);
440 err1:
441 amdgpu_device_wb_free(adev, index);
442 return r;
443 }
444
445
gfx_v9_0_free_microcode(struct amdgpu_device * adev)446 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
447 {
448 release_firmware(adev->gfx.pfp_fw);
449 adev->gfx.pfp_fw = NULL;
450 release_firmware(adev->gfx.me_fw);
451 adev->gfx.me_fw = NULL;
452 release_firmware(adev->gfx.ce_fw);
453 adev->gfx.ce_fw = NULL;
454 release_firmware(adev->gfx.rlc_fw);
455 adev->gfx.rlc_fw = NULL;
456 release_firmware(adev->gfx.mec_fw);
457 adev->gfx.mec_fw = NULL;
458 release_firmware(adev->gfx.mec2_fw);
459 adev->gfx.mec2_fw = NULL;
460
461 kfree(adev->gfx.rlc.register_list_format);
462 }
463
gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device * adev)464 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
465 {
466 const struct rlc_firmware_header_v2_1 *rlc_hdr;
467
468 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
469 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
470 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
471 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
472 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
473 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
474 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
475 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
476 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
477 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
478 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
479 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
480 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
481 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
482 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
483 }
484
gfx_v9_0_init_microcode(struct amdgpu_device * adev)485 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
486 {
487 const char *chip_name;
488 char fw_name[30];
489 int err;
490 struct amdgpu_firmware_info *info = NULL;
491 const struct common_firmware_header *header = NULL;
492 const struct gfx_firmware_header_v1_0 *cp_hdr;
493 const struct rlc_firmware_header_v2_0 *rlc_hdr;
494 unsigned int *tmp = NULL;
495 unsigned int i = 0;
496 uint16_t version_major;
497 uint16_t version_minor;
498
499 DRM_DEBUG("\n");
500
501 switch (adev->asic_type) {
502 case CHIP_VEGA10:
503 chip_name = "vega10";
504 break;
505 case CHIP_VEGA12:
506 chip_name = "vega12";
507 break;
508 case CHIP_VEGA20:
509 chip_name = "vega20";
510 break;
511 case CHIP_RAVEN:
512 chip_name = "raven";
513 break;
514 default:
515 BUG();
516 }
517
518 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
519 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
520 if (err)
521 goto out;
522 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
523 if (err)
524 goto out;
525 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
526 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
527 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
528
529 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
530 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
531 if (err)
532 goto out;
533 err = amdgpu_ucode_validate(adev->gfx.me_fw);
534 if (err)
535 goto out;
536 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
537 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
538 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
539
540 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
541 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
542 if (err)
543 goto out;
544 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
545 if (err)
546 goto out;
547 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
548 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
549 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
550
551 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
552 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
553 if (err)
554 goto out;
555 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
556 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
557
558 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
559 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
560 if (version_major == 2 && version_minor == 1)
561 adev->gfx.rlc.is_rlc_v2_1 = true;
562
563 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
564 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
565 adev->gfx.rlc.save_and_restore_offset =
566 le32_to_cpu(rlc_hdr->save_and_restore_offset);
567 adev->gfx.rlc.clear_state_descriptor_offset =
568 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
569 adev->gfx.rlc.avail_scratch_ram_locations =
570 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
571 adev->gfx.rlc.reg_restore_list_size =
572 le32_to_cpu(rlc_hdr->reg_restore_list_size);
573 adev->gfx.rlc.reg_list_format_start =
574 le32_to_cpu(rlc_hdr->reg_list_format_start);
575 adev->gfx.rlc.reg_list_format_separate_start =
576 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
577 adev->gfx.rlc.starting_offsets_start =
578 le32_to_cpu(rlc_hdr->starting_offsets_start);
579 adev->gfx.rlc.reg_list_format_size_bytes =
580 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
581 adev->gfx.rlc.reg_list_size_bytes =
582 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
583 adev->gfx.rlc.register_list_format =
584 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
585 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
586 if (!adev->gfx.rlc.register_list_format) {
587 err = -ENOMEM;
588 goto out;
589 }
590
591 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
592 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
593 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
594 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
595
596 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
597
598 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
599 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
600 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
601 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
602
603 if (adev->gfx.rlc.is_rlc_v2_1)
604 gfx_v9_0_init_rlc_ext_microcode(adev);
605
606 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
607 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
608 if (err)
609 goto out;
610 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
611 if (err)
612 goto out;
613 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
614 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
615 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
616
617
618 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
619 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
620 if (!err) {
621 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
622 if (err)
623 goto out;
624 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
625 adev->gfx.mec2_fw->data;
626 adev->gfx.mec2_fw_version =
627 le32_to_cpu(cp_hdr->header.ucode_version);
628 adev->gfx.mec2_feature_version =
629 le32_to_cpu(cp_hdr->ucode_feature_version);
630 } else {
631 err = 0;
632 adev->gfx.mec2_fw = NULL;
633 }
634
635 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
636 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
637 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
638 info->fw = adev->gfx.pfp_fw;
639 header = (const struct common_firmware_header *)info->fw->data;
640 adev->firmware.fw_size +=
641 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
642
643 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
644 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
645 info->fw = adev->gfx.me_fw;
646 header = (const struct common_firmware_header *)info->fw->data;
647 adev->firmware.fw_size +=
648 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
649
650 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
651 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
652 info->fw = adev->gfx.ce_fw;
653 header = (const struct common_firmware_header *)info->fw->data;
654 adev->firmware.fw_size +=
655 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
656
657 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
658 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
659 info->fw = adev->gfx.rlc_fw;
660 header = (const struct common_firmware_header *)info->fw->data;
661 adev->firmware.fw_size +=
662 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
663
664 if (adev->gfx.rlc.is_rlc_v2_1 &&
665 adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
666 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
667 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
668 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
669 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
670 info->fw = adev->gfx.rlc_fw;
671 adev->firmware.fw_size +=
672 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
673
674 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
675 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
676 info->fw = adev->gfx.rlc_fw;
677 adev->firmware.fw_size +=
678 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
679
680 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
681 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
682 info->fw = adev->gfx.rlc_fw;
683 adev->firmware.fw_size +=
684 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
685 }
686
687 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
688 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
689 info->fw = adev->gfx.mec_fw;
690 header = (const struct common_firmware_header *)info->fw->data;
691 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
692 adev->firmware.fw_size +=
693 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
694
695 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
696 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
697 info->fw = adev->gfx.mec_fw;
698 adev->firmware.fw_size +=
699 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
700
701 if (adev->gfx.mec2_fw) {
702 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
703 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
704 info->fw = adev->gfx.mec2_fw;
705 header = (const struct common_firmware_header *)info->fw->data;
706 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
707 adev->firmware.fw_size +=
708 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
709 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
710 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
711 info->fw = adev->gfx.mec2_fw;
712 adev->firmware.fw_size +=
713 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
714 }
715
716 }
717
718 out:
719 if (err) {
720 dev_err(adev->dev,
721 "gfx9: Failed to load firmware \"%s\"\n",
722 fw_name);
723 release_firmware(adev->gfx.pfp_fw);
724 adev->gfx.pfp_fw = NULL;
725 release_firmware(adev->gfx.me_fw);
726 adev->gfx.me_fw = NULL;
727 release_firmware(adev->gfx.ce_fw);
728 adev->gfx.ce_fw = NULL;
729 release_firmware(adev->gfx.rlc_fw);
730 adev->gfx.rlc_fw = NULL;
731 release_firmware(adev->gfx.mec_fw);
732 adev->gfx.mec_fw = NULL;
733 release_firmware(adev->gfx.mec2_fw);
734 adev->gfx.mec2_fw = NULL;
735 }
736 return err;
737 }
738
gfx_v9_0_get_csb_size(struct amdgpu_device * adev)739 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
740 {
741 u32 count = 0;
742 const struct cs_section_def *sect = NULL;
743 const struct cs_extent_def *ext = NULL;
744
745 /* begin clear state */
746 count += 2;
747 /* context control state */
748 count += 3;
749
750 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
751 for (ext = sect->section; ext->extent != NULL; ++ext) {
752 if (sect->id == SECT_CONTEXT)
753 count += 2 + ext->reg_count;
754 else
755 return 0;
756 }
757 }
758
759 /* end clear state */
760 count += 2;
761 /* clear state */
762 count += 2;
763
764 return count;
765 }
766
gfx_v9_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)767 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
768 volatile u32 *buffer)
769 {
770 u32 count = 0, i;
771 const struct cs_section_def *sect = NULL;
772 const struct cs_extent_def *ext = NULL;
773
774 if (adev->gfx.rlc.cs_data == NULL)
775 return;
776 if (buffer == NULL)
777 return;
778
779 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
780 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
781
782 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
783 buffer[count++] = cpu_to_le32(0x80000000);
784 buffer[count++] = cpu_to_le32(0x80000000);
785
786 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
787 for (ext = sect->section; ext->extent != NULL; ++ext) {
788 if (sect->id == SECT_CONTEXT) {
789 buffer[count++] =
790 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
791 buffer[count++] = cpu_to_le32(ext->reg_index -
792 PACKET3_SET_CONTEXT_REG_START);
793 for (i = 0; i < ext->reg_count; i++)
794 buffer[count++] = cpu_to_le32(ext->extent[i]);
795 } else {
796 return;
797 }
798 }
799 }
800
801 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
802 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
803
804 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
805 buffer[count++] = cpu_to_le32(0);
806 }
807
gfx_v9_0_init_lbpw(struct amdgpu_device * adev)808 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
809 {
810 uint32_t data;
811
812 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
813 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
814 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
815 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
816 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
817
818 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
819 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
820
821 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
822 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
823
824 mutex_lock(&adev->grbm_idx_mutex);
825 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
826 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
827 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
828
829 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
830 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
831 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
832 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
833 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
834
835 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
836 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
837 data &= 0x0000FFFF;
838 data |= 0x00C00000;
839 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
840
841 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
842 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
843
844 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
845 * but used for RLC_LB_CNTL configuration */
846 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
847 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
848 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
849 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
850 mutex_unlock(&adev->grbm_idx_mutex);
851 }
852
gfx_v9_0_enable_lbpw(struct amdgpu_device * adev,bool enable)853 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
854 {
855 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
856 }
857
rv_init_cp_jump_table(struct amdgpu_device * adev)858 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
859 {
860 const __le32 *fw_data;
861 volatile u32 *dst_ptr;
862 int me, i, max_me = 5;
863 u32 bo_offset = 0;
864 u32 table_offset, table_size;
865
866 /* write the cp table buffer */
867 dst_ptr = adev->gfx.rlc.cp_table_ptr;
868 for (me = 0; me < max_me; me++) {
869 if (me == 0) {
870 const struct gfx_firmware_header_v1_0 *hdr =
871 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
872 fw_data = (const __le32 *)
873 (adev->gfx.ce_fw->data +
874 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
875 table_offset = le32_to_cpu(hdr->jt_offset);
876 table_size = le32_to_cpu(hdr->jt_size);
877 } else if (me == 1) {
878 const struct gfx_firmware_header_v1_0 *hdr =
879 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
880 fw_data = (const __le32 *)
881 (adev->gfx.pfp_fw->data +
882 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
883 table_offset = le32_to_cpu(hdr->jt_offset);
884 table_size = le32_to_cpu(hdr->jt_size);
885 } else if (me == 2) {
886 const struct gfx_firmware_header_v1_0 *hdr =
887 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
888 fw_data = (const __le32 *)
889 (adev->gfx.me_fw->data +
890 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
891 table_offset = le32_to_cpu(hdr->jt_offset);
892 table_size = le32_to_cpu(hdr->jt_size);
893 } else if (me == 3) {
894 const struct gfx_firmware_header_v1_0 *hdr =
895 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
896 fw_data = (const __le32 *)
897 (adev->gfx.mec_fw->data +
898 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
899 table_offset = le32_to_cpu(hdr->jt_offset);
900 table_size = le32_to_cpu(hdr->jt_size);
901 } else if (me == 4) {
902 const struct gfx_firmware_header_v1_0 *hdr =
903 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
904 fw_data = (const __le32 *)
905 (adev->gfx.mec2_fw->data +
906 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
907 table_offset = le32_to_cpu(hdr->jt_offset);
908 table_size = le32_to_cpu(hdr->jt_size);
909 }
910
911 for (i = 0; i < table_size; i ++) {
912 dst_ptr[bo_offset + i] =
913 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
914 }
915
916 bo_offset += table_size;
917 }
918 }
919
gfx_v9_0_rlc_fini(struct amdgpu_device * adev)920 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
921 {
922 /* clear state block */
923 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
924 &adev->gfx.rlc.clear_state_gpu_addr,
925 (void **)&adev->gfx.rlc.cs_ptr);
926
927 /* jump table block */
928 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
929 &adev->gfx.rlc.cp_table_gpu_addr,
930 (void **)&adev->gfx.rlc.cp_table_ptr);
931 }
932
gfx_v9_0_rlc_init(struct amdgpu_device * adev)933 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
934 {
935 volatile u32 *dst_ptr;
936 u32 dws;
937 const struct cs_section_def *cs_data;
938 int r;
939
940 adev->gfx.rlc.cs_data = gfx9_cs_data;
941
942 cs_data = adev->gfx.rlc.cs_data;
943
944 if (cs_data) {
945 /* clear state block */
946 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
947 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
948 AMDGPU_GEM_DOMAIN_VRAM,
949 &adev->gfx.rlc.clear_state_obj,
950 &adev->gfx.rlc.clear_state_gpu_addr,
951 (void **)&adev->gfx.rlc.cs_ptr);
952 if (r) {
953 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
954 r);
955 gfx_v9_0_rlc_fini(adev);
956 return r;
957 }
958 /* set up the cs buffer */
959 dst_ptr = adev->gfx.rlc.cs_ptr;
960 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
961 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
962 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
963 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
964 }
965
966 if (adev->asic_type == CHIP_RAVEN) {
967 /* TODO: double check the cp_table_size for RV */
968 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
969 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
970 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
971 &adev->gfx.rlc.cp_table_obj,
972 &adev->gfx.rlc.cp_table_gpu_addr,
973 (void **)&adev->gfx.rlc.cp_table_ptr);
974 if (r) {
975 dev_err(adev->dev,
976 "(%d) failed to create cp table bo\n", r);
977 gfx_v9_0_rlc_fini(adev);
978 return r;
979 }
980
981 rv_init_cp_jump_table(adev);
982 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
983 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
984
985 gfx_v9_0_init_lbpw(adev);
986 }
987
988 return 0;
989 }
990
gfx_v9_0_csb_vram_pin(struct amdgpu_device * adev)991 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
992 {
993 int r;
994
995 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
996 if (unlikely(r != 0))
997 return r;
998
999 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1000 AMDGPU_GEM_DOMAIN_VRAM);
1001 if (!r)
1002 adev->gfx.rlc.clear_state_gpu_addr =
1003 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1004
1005 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1006
1007 return r;
1008 }
1009
gfx_v9_0_csb_vram_unpin(struct amdgpu_device * adev)1010 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1011 {
1012 int r;
1013
1014 if (!adev->gfx.rlc.clear_state_obj)
1015 return;
1016
1017 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1018 if (likely(r == 0)) {
1019 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1020 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1021 }
1022 }
1023
gfx_v9_0_mec_fini(struct amdgpu_device * adev)1024 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1025 {
1026 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1027 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1028 }
1029
gfx_v9_0_mec_init(struct amdgpu_device * adev)1030 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1031 {
1032 int r;
1033 u32 *hpd;
1034 const __le32 *fw_data;
1035 unsigned fw_size;
1036 u32 *fw;
1037 size_t mec_hpd_size;
1038
1039 const struct gfx_firmware_header_v1_0 *mec_hdr;
1040
1041 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1042
1043 /* take ownership of the relevant compute queues */
1044 amdgpu_gfx_compute_queue_acquire(adev);
1045 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1046
1047 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1048 AMDGPU_GEM_DOMAIN_GTT,
1049 &adev->gfx.mec.hpd_eop_obj,
1050 &adev->gfx.mec.hpd_eop_gpu_addr,
1051 (void **)&hpd);
1052 if (r) {
1053 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1054 gfx_v9_0_mec_fini(adev);
1055 return r;
1056 }
1057
1058 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1059
1060 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1061 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1062
1063 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1064
1065 fw_data = (const __le32 *)
1066 (adev->gfx.mec_fw->data +
1067 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1068 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1069
1070 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1071 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1072 &adev->gfx.mec.mec_fw_obj,
1073 &adev->gfx.mec.mec_fw_gpu_addr,
1074 (void **)&fw);
1075 if (r) {
1076 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1077 gfx_v9_0_mec_fini(adev);
1078 return r;
1079 }
1080
1081 memcpy(fw, fw_data, fw_size);
1082
1083 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1084 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1085
1086 return 0;
1087 }
1088
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)1089 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1090 {
1091 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1092 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1093 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1094 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1095 (SQ_IND_INDEX__FORCE_READ_MASK));
1096 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1097 }
1098
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)1099 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1100 uint32_t wave, uint32_t thread,
1101 uint32_t regno, uint32_t num, uint32_t *out)
1102 {
1103 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1104 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1105 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1106 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1107 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1108 (SQ_IND_INDEX__FORCE_READ_MASK) |
1109 (SQ_IND_INDEX__AUTO_INCR_MASK));
1110 while (num--)
1111 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1112 }
1113
gfx_v9_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)1114 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1115 {
1116 /* type 1 wave data */
1117 dst[(*no_fields)++] = 1;
1118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1121 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1122 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1123 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1124 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1125 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1126 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1127 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1128 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1129 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1130 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1131 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1132 }
1133
gfx_v9_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)1134 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1135 uint32_t wave, uint32_t start,
1136 uint32_t size, uint32_t *dst)
1137 {
1138 wave_read_regs(
1139 adev, simd, wave, 0,
1140 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1141 }
1142
gfx_v9_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)1143 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1144 uint32_t wave, uint32_t thread,
1145 uint32_t start, uint32_t size,
1146 uint32_t *dst)
1147 {
1148 wave_read_regs(
1149 adev, simd, wave, thread,
1150 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1151 }
1152
gfx_v9_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q)1153 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1154 u32 me, u32 pipe, u32 q)
1155 {
1156 soc15_grbm_select(adev, me, pipe, q, 0);
1157 }
1158
1159 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1160 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1161 .select_se_sh = &gfx_v9_0_select_se_sh,
1162 .read_wave_data = &gfx_v9_0_read_wave_data,
1163 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1164 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1165 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1166 };
1167
gfx_v9_0_gpu_early_init(struct amdgpu_device * adev)1168 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1169 {
1170 u32 gb_addr_config;
1171 int err;
1172
1173 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1174
1175 switch (adev->asic_type) {
1176 case CHIP_VEGA10:
1177 adev->gfx.config.max_hw_contexts = 8;
1178 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1179 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1180 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1181 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1182 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1183 break;
1184 case CHIP_VEGA12:
1185 adev->gfx.config.max_hw_contexts = 8;
1186 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1187 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1188 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1189 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1190 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1191 DRM_INFO("fix gfx.config for vega12\n");
1192 break;
1193 case CHIP_VEGA20:
1194 adev->gfx.config.max_hw_contexts = 8;
1195 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1196 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1197 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1198 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1199 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1200 gb_addr_config &= ~0xf3e777ff;
1201 gb_addr_config |= 0x22014042;
1202 /* check vbios table if gpu info is not available */
1203 err = amdgpu_atomfirmware_get_gfx_info(adev);
1204 if (err)
1205 return err;
1206 break;
1207 case CHIP_RAVEN:
1208 adev->gfx.config.max_hw_contexts = 8;
1209 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1210 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1211 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1212 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1213 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1214 break;
1215 default:
1216 BUG();
1217 break;
1218 }
1219
1220 adev->gfx.config.gb_addr_config = gb_addr_config;
1221
1222 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1223 REG_GET_FIELD(
1224 adev->gfx.config.gb_addr_config,
1225 GB_ADDR_CONFIG,
1226 NUM_PIPES);
1227
1228 adev->gfx.config.max_tile_pipes =
1229 adev->gfx.config.gb_addr_config_fields.num_pipes;
1230
1231 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1232 REG_GET_FIELD(
1233 adev->gfx.config.gb_addr_config,
1234 GB_ADDR_CONFIG,
1235 NUM_BANKS);
1236 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1237 REG_GET_FIELD(
1238 adev->gfx.config.gb_addr_config,
1239 GB_ADDR_CONFIG,
1240 MAX_COMPRESSED_FRAGS);
1241 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1242 REG_GET_FIELD(
1243 adev->gfx.config.gb_addr_config,
1244 GB_ADDR_CONFIG,
1245 NUM_RB_PER_SE);
1246 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1247 REG_GET_FIELD(
1248 adev->gfx.config.gb_addr_config,
1249 GB_ADDR_CONFIG,
1250 NUM_SHADER_ENGINES);
1251 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1252 REG_GET_FIELD(
1253 adev->gfx.config.gb_addr_config,
1254 GB_ADDR_CONFIG,
1255 PIPE_INTERLEAVE_SIZE));
1256
1257 return 0;
1258 }
1259
gfx_v9_0_ngg_create_buf(struct amdgpu_device * adev,struct amdgpu_ngg_buf * ngg_buf,int size_se,int default_size_se)1260 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1261 struct amdgpu_ngg_buf *ngg_buf,
1262 int size_se,
1263 int default_size_se)
1264 {
1265 int r;
1266
1267 if (size_se < 0) {
1268 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1269 return -EINVAL;
1270 }
1271 size_se = size_se ? size_se : default_size_se;
1272
1273 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1274 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1275 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1276 &ngg_buf->bo,
1277 &ngg_buf->gpu_addr,
1278 NULL);
1279 if (r) {
1280 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1281 return r;
1282 }
1283 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1284
1285 return r;
1286 }
1287
gfx_v9_0_ngg_fini(struct amdgpu_device * adev)1288 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1289 {
1290 int i;
1291
1292 for (i = 0; i < NGG_BUF_MAX; i++)
1293 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1294 &adev->gfx.ngg.buf[i].gpu_addr,
1295 NULL);
1296
1297 memset(&adev->gfx.ngg.buf[0], 0,
1298 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1299
1300 adev->gfx.ngg.init = false;
1301
1302 return 0;
1303 }
1304
gfx_v9_0_ngg_init(struct amdgpu_device * adev)1305 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1306 {
1307 int r;
1308
1309 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1310 return 0;
1311
1312 /* GDS reserve memory: 64 bytes alignment */
1313 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1314 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1315 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1316 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1317 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1318
1319 /* Primitive Buffer */
1320 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1321 amdgpu_prim_buf_per_se,
1322 64 * 1024);
1323 if (r) {
1324 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1325 goto err;
1326 }
1327
1328 /* Position Buffer */
1329 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1330 amdgpu_pos_buf_per_se,
1331 256 * 1024);
1332 if (r) {
1333 dev_err(adev->dev, "Failed to create Position Buffer\n");
1334 goto err;
1335 }
1336
1337 /* Control Sideband */
1338 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1339 amdgpu_cntl_sb_buf_per_se,
1340 256);
1341 if (r) {
1342 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1343 goto err;
1344 }
1345
1346 /* Parameter Cache, not created by default */
1347 if (amdgpu_param_buf_per_se <= 0)
1348 goto out;
1349
1350 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1351 amdgpu_param_buf_per_se,
1352 512 * 1024);
1353 if (r) {
1354 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1355 goto err;
1356 }
1357
1358 out:
1359 adev->gfx.ngg.init = true;
1360 return 0;
1361 err:
1362 gfx_v9_0_ngg_fini(adev);
1363 return r;
1364 }
1365
gfx_v9_0_ngg_en(struct amdgpu_device * adev)1366 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1367 {
1368 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1369 int r;
1370 u32 data, base;
1371
1372 if (!amdgpu_ngg)
1373 return 0;
1374
1375 /* Program buffer size */
1376 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1377 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1378 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1379 adev->gfx.ngg.buf[NGG_POS].size >> 8);
1380 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1381
1382 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1383 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1384 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1385 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1386 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1387
1388 /* Program buffer base address */
1389 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1390 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1391 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1392
1393 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1394 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1395 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1396
1397 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1398 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1399 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1400
1401 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1402 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1403 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1404
1405 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1406 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1407 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1408
1409 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1410 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1411 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1412
1413 /* Clear GDS reserved memory */
1414 r = amdgpu_ring_alloc(ring, 17);
1415 if (r) {
1416 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1417 ring->idx, r);
1418 return r;
1419 }
1420
1421 gfx_v9_0_write_data_to_reg(ring, 0, false,
1422 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1423 (adev->gds.mem.total_size +
1424 adev->gfx.ngg.gds_reserve_size) >>
1425 AMDGPU_GDS_SHIFT);
1426
1427 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1428 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1429 PACKET3_DMA_DATA_DST_SEL(1) |
1430 PACKET3_DMA_DATA_SRC_SEL(2)));
1431 amdgpu_ring_write(ring, 0);
1432 amdgpu_ring_write(ring, 0);
1433 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1434 amdgpu_ring_write(ring, 0);
1435 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1436 adev->gfx.ngg.gds_reserve_size);
1437
1438 gfx_v9_0_write_data_to_reg(ring, 0, false,
1439 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1440
1441 amdgpu_ring_commit(ring);
1442
1443 return 0;
1444 }
1445
gfx_v9_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)1446 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1447 int mec, int pipe, int queue)
1448 {
1449 int r;
1450 unsigned irq_type;
1451 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1452
1453 ring = &adev->gfx.compute_ring[ring_id];
1454
1455 /* mec0 is me1 */
1456 ring->me = mec + 1;
1457 ring->pipe = pipe;
1458 ring->queue = queue;
1459
1460 ring->ring_obj = NULL;
1461 ring->use_doorbell = true;
1462 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1463 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1464 + (ring_id * GFX9_MEC_HPD_SIZE);
1465 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1466
1467 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1468 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1469 + ring->pipe;
1470
1471 /* type-2 packets are deprecated on MEC, use type-3 instead */
1472 r = amdgpu_ring_init(adev, ring, 1024,
1473 &adev->gfx.eop_irq, irq_type);
1474 if (r)
1475 return r;
1476
1477
1478 return 0;
1479 }
1480
gfx_v9_0_sw_init(void * handle)1481 static int gfx_v9_0_sw_init(void *handle)
1482 {
1483 int i, j, k, r, ring_id;
1484 struct amdgpu_ring *ring;
1485 struct amdgpu_kiq *kiq;
1486 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1487
1488 switch (adev->asic_type) {
1489 case CHIP_VEGA10:
1490 case CHIP_VEGA12:
1491 case CHIP_VEGA20:
1492 case CHIP_RAVEN:
1493 adev->gfx.mec.num_mec = 2;
1494 break;
1495 default:
1496 adev->gfx.mec.num_mec = 1;
1497 break;
1498 }
1499
1500 adev->gfx.mec.num_pipe_per_mec = 4;
1501 adev->gfx.mec.num_queue_per_pipe = 8;
1502
1503 /* KIQ event */
1504 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq);
1505 if (r)
1506 return r;
1507
1508 /* EOP Event */
1509 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1510 if (r)
1511 return r;
1512
1513 /* Privileged reg */
1514 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1515 &adev->gfx.priv_reg_irq);
1516 if (r)
1517 return r;
1518
1519 /* Privileged inst */
1520 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1521 &adev->gfx.priv_inst_irq);
1522 if (r)
1523 return r;
1524
1525 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1526
1527 gfx_v9_0_scratch_init(adev);
1528
1529 r = gfx_v9_0_init_microcode(adev);
1530 if (r) {
1531 DRM_ERROR("Failed to load gfx firmware!\n");
1532 return r;
1533 }
1534
1535 r = gfx_v9_0_rlc_init(adev);
1536 if (r) {
1537 DRM_ERROR("Failed to init rlc BOs!\n");
1538 return r;
1539 }
1540
1541 r = gfx_v9_0_mec_init(adev);
1542 if (r) {
1543 DRM_ERROR("Failed to init MEC BOs!\n");
1544 return r;
1545 }
1546
1547 /* set up the gfx ring */
1548 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1549 ring = &adev->gfx.gfx_ring[i];
1550 ring->ring_obj = NULL;
1551 if (!i)
1552 sprintf(ring->name, "gfx");
1553 else
1554 sprintf(ring->name, "gfx_%d", i);
1555 ring->use_doorbell = true;
1556 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1557 r = amdgpu_ring_init(adev, ring, 1024,
1558 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1559 if (r)
1560 return r;
1561 }
1562
1563 /* set up the compute queues - allocate horizontally across pipes */
1564 ring_id = 0;
1565 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1566 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1567 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1568 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1569 continue;
1570
1571 r = gfx_v9_0_compute_ring_init(adev,
1572 ring_id,
1573 i, k, j);
1574 if (r)
1575 return r;
1576
1577 ring_id++;
1578 }
1579 }
1580 }
1581
1582 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1583 if (r) {
1584 DRM_ERROR("Failed to init KIQ BOs!\n");
1585 return r;
1586 }
1587
1588 kiq = &adev->gfx.kiq;
1589 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1590 if (r)
1591 return r;
1592
1593 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1594 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1595 if (r)
1596 return r;
1597
1598 /* reserve GDS, GWS and OA resource for gfx */
1599 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1600 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1601 &adev->gds.gds_gfx_bo, NULL, NULL);
1602 if (r)
1603 return r;
1604
1605 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1606 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1607 &adev->gds.gws_gfx_bo, NULL, NULL);
1608 if (r)
1609 return r;
1610
1611 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1612 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1613 &adev->gds.oa_gfx_bo, NULL, NULL);
1614 if (r)
1615 return r;
1616
1617 adev->gfx.ce_ram_size = 0x8000;
1618
1619 r = gfx_v9_0_gpu_early_init(adev);
1620 if (r)
1621 return r;
1622
1623 r = gfx_v9_0_ngg_init(adev);
1624 if (r)
1625 return r;
1626
1627 return 0;
1628 }
1629
1630
gfx_v9_0_sw_fini(void * handle)1631 static int gfx_v9_0_sw_fini(void *handle)
1632 {
1633 int i;
1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1635
1636 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1637 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1638 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1639
1640 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1641 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1642 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1643 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1644
1645 amdgpu_gfx_compute_mqd_sw_fini(adev);
1646 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1647 amdgpu_gfx_kiq_fini(adev);
1648
1649 gfx_v9_0_mec_fini(adev);
1650 gfx_v9_0_ngg_fini(adev);
1651 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1652 &adev->gfx.rlc.clear_state_gpu_addr,
1653 (void **)&adev->gfx.rlc.cs_ptr);
1654 if (adev->asic_type == CHIP_RAVEN) {
1655 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1656 &adev->gfx.rlc.cp_table_gpu_addr,
1657 (void **)&adev->gfx.rlc.cp_table_ptr);
1658 }
1659 gfx_v9_0_free_microcode(adev);
1660
1661 return 0;
1662 }
1663
1664
gfx_v9_0_tiling_mode_table_init(struct amdgpu_device * adev)1665 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1666 {
1667 /* TODO */
1668 }
1669
gfx_v9_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)1670 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1671 {
1672 u32 data;
1673
1674 if (instance == 0xffffffff)
1675 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1676 else
1677 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1678
1679 if (se_num == 0xffffffff)
1680 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1681 else
1682 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1683
1684 if (sh_num == 0xffffffff)
1685 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1686 else
1687 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1688
1689 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1690 }
1691
gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device * adev)1692 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1693 {
1694 u32 data, mask;
1695
1696 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1697 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1698
1699 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1700 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1701
1702 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1703 adev->gfx.config.max_sh_per_se);
1704
1705 return (~data) & mask;
1706 }
1707
gfx_v9_0_setup_rb(struct amdgpu_device * adev)1708 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1709 {
1710 int i, j;
1711 u32 data;
1712 u32 active_rbs = 0;
1713 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1714 adev->gfx.config.max_sh_per_se;
1715
1716 mutex_lock(&adev->grbm_idx_mutex);
1717 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1718 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1719 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1720 data = gfx_v9_0_get_rb_active_bitmap(adev);
1721 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1722 rb_bitmap_width_per_sh);
1723 }
1724 }
1725 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1726 mutex_unlock(&adev->grbm_idx_mutex);
1727
1728 adev->gfx.config.backend_enable_mask = active_rbs;
1729 adev->gfx.config.num_rbs = hweight32(active_rbs);
1730 }
1731
1732 #define DEFAULT_SH_MEM_BASES (0x6000)
1733 #define FIRST_COMPUTE_VMID (8)
1734 #define LAST_COMPUTE_VMID (16)
gfx_v9_0_init_compute_vmid(struct amdgpu_device * adev)1735 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1736 {
1737 int i;
1738 uint32_t sh_mem_config;
1739 uint32_t sh_mem_bases;
1740
1741 /*
1742 * Configure apertures:
1743 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1744 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1745 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1746 */
1747 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1748
1749 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1750 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1751 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1752
1753 mutex_lock(&adev->srbm_mutex);
1754 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1755 soc15_grbm_select(adev, 0, 0, 0, i);
1756 /* CP and shaders */
1757 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1758 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1759 }
1760 soc15_grbm_select(adev, 0, 0, 0, 0);
1761 mutex_unlock(&adev->srbm_mutex);
1762 }
1763
gfx_v9_0_gpu_init(struct amdgpu_device * adev)1764 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1765 {
1766 u32 tmp;
1767 int i;
1768
1769 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1770
1771 gfx_v9_0_tiling_mode_table_init(adev);
1772
1773 gfx_v9_0_setup_rb(adev);
1774 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1775 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1776
1777 /* XXX SH_MEM regs */
1778 /* where to put LDS, scratch, GPUVM in FSA64 space */
1779 mutex_lock(&adev->srbm_mutex);
1780 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1781 soc15_grbm_select(adev, 0, 0, 0, i);
1782 /* CP and shaders */
1783 if (i == 0) {
1784 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1785 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1786 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1787 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1788 } else {
1789 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1790 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1791 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1792 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1793 (adev->gmc.private_aperture_start >> 48));
1794 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1795 (adev->gmc.shared_aperture_start >> 48));
1796 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1797 }
1798 }
1799 soc15_grbm_select(adev, 0, 0, 0, 0);
1800
1801 mutex_unlock(&adev->srbm_mutex);
1802
1803 gfx_v9_0_init_compute_vmid(adev);
1804
1805 mutex_lock(&adev->grbm_idx_mutex);
1806 /*
1807 * making sure that the following register writes will be broadcasted
1808 * to all the shaders
1809 */
1810 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1811
1812 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1813 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1814 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1815 (adev->gfx.config.sc_prim_fifo_size_backend <<
1816 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1817 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1818 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1819 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1820 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1821 mutex_unlock(&adev->grbm_idx_mutex);
1822
1823 }
1824
gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device * adev)1825 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1826 {
1827 u32 i, j, k;
1828 u32 mask;
1829
1830 mutex_lock(&adev->grbm_idx_mutex);
1831 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1832 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1833 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1834 for (k = 0; k < adev->usec_timeout; k++) {
1835 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1836 break;
1837 udelay(1);
1838 }
1839 if (k == adev->usec_timeout) {
1840 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1841 0xffffffff, 0xffffffff);
1842 mutex_unlock(&adev->grbm_idx_mutex);
1843 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1844 i, j);
1845 return;
1846 }
1847 }
1848 }
1849 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1850 mutex_unlock(&adev->grbm_idx_mutex);
1851
1852 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1853 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1854 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1855 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1856 for (k = 0; k < adev->usec_timeout; k++) {
1857 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1858 break;
1859 udelay(1);
1860 }
1861 }
1862
gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1863 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1864 bool enable)
1865 {
1866 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1867
1868 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1869 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1870 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1871 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1872
1873 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1874 }
1875
gfx_v9_0_init_csb(struct amdgpu_device * adev)1876 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1877 {
1878 /* csib */
1879 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1880 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1881 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1882 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1883 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1884 adev->gfx.rlc.clear_state_size);
1885 }
1886
gfx_v9_1_parse_ind_reg_list(int * register_list_format,int indirect_offset,int list_size,int * unique_indirect_regs,int unique_indirect_reg_count,int * indirect_start_offsets,int * indirect_start_offsets_count,int max_start_offsets_count)1887 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1888 int indirect_offset,
1889 int list_size,
1890 int *unique_indirect_regs,
1891 int unique_indirect_reg_count,
1892 int *indirect_start_offsets,
1893 int *indirect_start_offsets_count,
1894 int max_start_offsets_count)
1895 {
1896 int idx;
1897
1898 for (; indirect_offset < list_size; indirect_offset++) {
1899 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1900 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1901 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1902
1903 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1904 indirect_offset += 2;
1905
1906 /* look for the matching indice */
1907 for (idx = 0; idx < unique_indirect_reg_count; idx++) {
1908 if (unique_indirect_regs[idx] ==
1909 register_list_format[indirect_offset] ||
1910 !unique_indirect_regs[idx])
1911 break;
1912 }
1913
1914 BUG_ON(idx >= unique_indirect_reg_count);
1915
1916 if (!unique_indirect_regs[idx])
1917 unique_indirect_regs[idx] = register_list_format[indirect_offset];
1918
1919 indirect_offset++;
1920 }
1921 }
1922 }
1923
gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device * adev)1924 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1925 {
1926 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1927 int unique_indirect_reg_count = 0;
1928
1929 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1930 int indirect_start_offsets_count = 0;
1931
1932 int list_size = 0;
1933 int i = 0, j = 0;
1934 u32 tmp = 0;
1935
1936 u32 *register_list_format =
1937 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1938 if (!register_list_format)
1939 return -ENOMEM;
1940 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1941 adev->gfx.rlc.reg_list_format_size_bytes);
1942
1943 /* setup unique_indirect_regs array and indirect_start_offsets array */
1944 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1945 gfx_v9_1_parse_ind_reg_list(register_list_format,
1946 adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1947 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1948 unique_indirect_regs,
1949 unique_indirect_reg_count,
1950 indirect_start_offsets,
1951 &indirect_start_offsets_count,
1952 ARRAY_SIZE(indirect_start_offsets));
1953
1954 /* enable auto inc in case it is disabled */
1955 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1956 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1957 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1958
1959 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1960 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1961 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1962 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1963 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1964 adev->gfx.rlc.register_restore[i]);
1965
1966 /* load indirect register */
1967 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1968 adev->gfx.rlc.reg_list_format_start);
1969
1970 /* direct register portion */
1971 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1972 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1973 register_list_format[i]);
1974
1975 /* indirect register portion */
1976 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1977 if (register_list_format[i] == 0xFFFFFFFF) {
1978 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1979 continue;
1980 }
1981
1982 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1983 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1984
1985 for (j = 0; j < unique_indirect_reg_count; j++) {
1986 if (register_list_format[i] == unique_indirect_regs[j]) {
1987 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1988 break;
1989 }
1990 }
1991
1992 BUG_ON(j >= unique_indirect_reg_count);
1993
1994 i++;
1995 }
1996
1997 /* set save/restore list size */
1998 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1999 list_size = list_size >> 1;
2000 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2001 adev->gfx.rlc.reg_restore_list_size);
2002 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2003
2004 /* write the starting offsets to RLC scratch ram */
2005 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2006 adev->gfx.rlc.starting_offsets_start);
2007 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2008 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2009 indirect_start_offsets[i]);
2010
2011 /* load unique indirect regs*/
2012 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2013 if (unique_indirect_regs[i] != 0) {
2014 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2015 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2016 unique_indirect_regs[i] & 0x3FFFF);
2017
2018 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2019 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2020 unique_indirect_regs[i] >> 20);
2021 }
2022 }
2023
2024 kfree(register_list_format);
2025 return 0;
2026 }
2027
gfx_v9_0_enable_save_restore_machine(struct amdgpu_device * adev)2028 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2029 {
2030 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2031 }
2032
pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device * adev,bool enable)2033 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2034 bool enable)
2035 {
2036 uint32_t data = 0;
2037 uint32_t default_data = 0;
2038
2039 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2040 if (enable == true) {
2041 /* enable GFXIP control over CGPG */
2042 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2043 if(default_data != data)
2044 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2045
2046 /* update status */
2047 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2048 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2049 if(default_data != data)
2050 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2051 } else {
2052 /* restore GFXIP control over GCPG */
2053 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2054 if(default_data != data)
2055 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2056 }
2057 }
2058
gfx_v9_0_init_gfx_power_gating(struct amdgpu_device * adev)2059 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2060 {
2061 uint32_t data = 0;
2062
2063 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2064 AMD_PG_SUPPORT_GFX_SMG |
2065 AMD_PG_SUPPORT_GFX_DMG)) {
2066 /* init IDLE_POLL_COUNT = 60 */
2067 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2068 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2069 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2070 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2071
2072 /* init RLC PG Delay */
2073 data = 0;
2074 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2075 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2076 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2077 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2078 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2079
2080 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2081 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2082 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2083 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2084
2085 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2086 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2087 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2088 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2089
2090 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2091 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2092
2093 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2094 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2095 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2096
2097 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2098 }
2099 }
2100
gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device * adev,bool enable)2101 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2102 bool enable)
2103 {
2104 uint32_t data = 0;
2105 uint32_t default_data = 0;
2106
2107 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2108 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2109 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2110 enable ? 1 : 0);
2111 if (default_data != data)
2112 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2113 }
2114
gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device * adev,bool enable)2115 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2116 bool enable)
2117 {
2118 uint32_t data = 0;
2119 uint32_t default_data = 0;
2120
2121 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2122 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2123 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2124 enable ? 1 : 0);
2125 if(default_data != data)
2126 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2127 }
2128
gfx_v9_0_enable_cp_power_gating(struct amdgpu_device * adev,bool enable)2129 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2130 bool enable)
2131 {
2132 uint32_t data = 0;
2133 uint32_t default_data = 0;
2134
2135 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2136 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2137 CP_PG_DISABLE,
2138 enable ? 0 : 1);
2139 if(default_data != data)
2140 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2141 }
2142
gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)2143 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2144 bool enable)
2145 {
2146 uint32_t data, default_data;
2147
2148 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2149 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2150 GFX_POWER_GATING_ENABLE,
2151 enable ? 1 : 0);
2152 if(default_data != data)
2153 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2154 }
2155
gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device * adev,bool enable)2156 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2157 bool enable)
2158 {
2159 uint32_t data, default_data;
2160
2161 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2162 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2163 GFX_PIPELINE_PG_ENABLE,
2164 enable ? 1 : 0);
2165 if(default_data != data)
2166 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2167
2168 if (!enable)
2169 /* read any GFX register to wake up GFX */
2170 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2171 }
2172
gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device * adev,bool enable)2173 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2174 bool enable)
2175 {
2176 uint32_t data, default_data;
2177
2178 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2179 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2180 STATIC_PER_CU_PG_ENABLE,
2181 enable ? 1 : 0);
2182 if(default_data != data)
2183 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2184 }
2185
gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device * adev,bool enable)2186 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2187 bool enable)
2188 {
2189 uint32_t data, default_data;
2190
2191 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2192 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2193 DYN_PER_CU_PG_ENABLE,
2194 enable ? 1 : 0);
2195 if(default_data != data)
2196 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2197 }
2198
gfx_v9_0_init_pg(struct amdgpu_device * adev)2199 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2200 {
2201 gfx_v9_0_init_csb(adev);
2202
2203 /*
2204 * Rlc save restore list is workable since v2_1.
2205 * And it's needed by gfxoff feature.
2206 */
2207 if (adev->gfx.rlc.is_rlc_v2_1) {
2208 gfx_v9_1_init_rlc_save_restore_list(adev);
2209 gfx_v9_0_enable_save_restore_machine(adev);
2210 }
2211
2212 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2213 AMD_PG_SUPPORT_GFX_SMG |
2214 AMD_PG_SUPPORT_GFX_DMG |
2215 AMD_PG_SUPPORT_CP |
2216 AMD_PG_SUPPORT_GDS |
2217 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2218 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2219 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2220 gfx_v9_0_init_gfx_power_gating(adev);
2221 }
2222 }
2223
gfx_v9_0_rlc_stop(struct amdgpu_device * adev)2224 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2225 {
2226 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2227 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2228 gfx_v9_0_wait_for_rlc_serdes(adev);
2229 }
2230
gfx_v9_0_rlc_reset(struct amdgpu_device * adev)2231 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2232 {
2233 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2234 udelay(50);
2235 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2236 udelay(50);
2237 }
2238
gfx_v9_0_rlc_start(struct amdgpu_device * adev)2239 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2240 {
2241 #ifdef AMDGPU_RLC_DEBUG_RETRY
2242 u32 rlc_ucode_ver;
2243 #endif
2244
2245 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2246
2247 /* carrizo do enable cp interrupt after cp inited */
2248 if (!(adev->flags & AMD_IS_APU))
2249 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2250
2251 udelay(50);
2252
2253 #ifdef AMDGPU_RLC_DEBUG_RETRY
2254 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2255 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2256 if(rlc_ucode_ver == 0x108) {
2257 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2258 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2259 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2260 * default is 0x9C4 to create a 100us interval */
2261 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2262 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2263 * to disable the page fault retry interrupts, default is
2264 * 0x100 (256) */
2265 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2266 }
2267 #endif
2268 }
2269
gfx_v9_0_rlc_load_microcode(struct amdgpu_device * adev)2270 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2271 {
2272 const struct rlc_firmware_header_v2_0 *hdr;
2273 const __le32 *fw_data;
2274 unsigned i, fw_size;
2275
2276 if (!adev->gfx.rlc_fw)
2277 return -EINVAL;
2278
2279 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2280 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2281
2282 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2283 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2284 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2285
2286 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2287 RLCG_UCODE_LOADING_START_ADDRESS);
2288 for (i = 0; i < fw_size; i++)
2289 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2290 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2291
2292 return 0;
2293 }
2294
gfx_v9_0_rlc_resume(struct amdgpu_device * adev)2295 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2296 {
2297 int r;
2298
2299 if (amdgpu_sriov_vf(adev)) {
2300 gfx_v9_0_init_csb(adev);
2301 return 0;
2302 }
2303
2304 gfx_v9_0_rlc_stop(adev);
2305
2306 /* disable CG */
2307 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2308
2309 gfx_v9_0_rlc_reset(adev);
2310
2311 gfx_v9_0_init_pg(adev);
2312
2313 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2314 /* legacy rlc firmware loading */
2315 r = gfx_v9_0_rlc_load_microcode(adev);
2316 if (r)
2317 return r;
2318 }
2319
2320 if (adev->asic_type == CHIP_RAVEN) {
2321 if (amdgpu_lbpw != 0)
2322 gfx_v9_0_enable_lbpw(adev, true);
2323 else
2324 gfx_v9_0_enable_lbpw(adev, false);
2325 }
2326
2327 gfx_v9_0_rlc_start(adev);
2328
2329 return 0;
2330 }
2331
gfx_v9_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2332 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2333 {
2334 int i;
2335 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2336
2337 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2338 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2339 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2340 if (!enable) {
2341 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2342 adev->gfx.gfx_ring[i].ready = false;
2343 }
2344 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2345 udelay(50);
2346 }
2347
gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2348 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2349 {
2350 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2351 const struct gfx_firmware_header_v1_0 *ce_hdr;
2352 const struct gfx_firmware_header_v1_0 *me_hdr;
2353 const __le32 *fw_data;
2354 unsigned i, fw_size;
2355
2356 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2357 return -EINVAL;
2358
2359 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2360 adev->gfx.pfp_fw->data;
2361 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2362 adev->gfx.ce_fw->data;
2363 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2364 adev->gfx.me_fw->data;
2365
2366 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2367 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2368 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2369
2370 gfx_v9_0_cp_gfx_enable(adev, false);
2371
2372 /* PFP */
2373 fw_data = (const __le32 *)
2374 (adev->gfx.pfp_fw->data +
2375 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2376 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2377 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2378 for (i = 0; i < fw_size; i++)
2379 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2380 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2381
2382 /* CE */
2383 fw_data = (const __le32 *)
2384 (adev->gfx.ce_fw->data +
2385 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2386 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2387 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2388 for (i = 0; i < fw_size; i++)
2389 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2390 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2391
2392 /* ME */
2393 fw_data = (const __le32 *)
2394 (adev->gfx.me_fw->data +
2395 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2396 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2397 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2398 for (i = 0; i < fw_size; i++)
2399 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2400 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2401
2402 return 0;
2403 }
2404
gfx_v9_0_cp_gfx_start(struct amdgpu_device * adev)2405 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2406 {
2407 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2408 const struct cs_section_def *sect = NULL;
2409 const struct cs_extent_def *ext = NULL;
2410 int r, i, tmp;
2411
2412 /* init the CP */
2413 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2414 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2415
2416 gfx_v9_0_cp_gfx_enable(adev, true);
2417
2418 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2419 if (r) {
2420 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2421 return r;
2422 }
2423
2424 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2425 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2426
2427 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2428 amdgpu_ring_write(ring, 0x80000000);
2429 amdgpu_ring_write(ring, 0x80000000);
2430
2431 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2432 for (ext = sect->section; ext->extent != NULL; ++ext) {
2433 if (sect->id == SECT_CONTEXT) {
2434 amdgpu_ring_write(ring,
2435 PACKET3(PACKET3_SET_CONTEXT_REG,
2436 ext->reg_count));
2437 amdgpu_ring_write(ring,
2438 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2439 for (i = 0; i < ext->reg_count; i++)
2440 amdgpu_ring_write(ring, ext->extent[i]);
2441 }
2442 }
2443 }
2444
2445 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2446 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2447
2448 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2449 amdgpu_ring_write(ring, 0);
2450
2451 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2452 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2453 amdgpu_ring_write(ring, 0x8000);
2454 amdgpu_ring_write(ring, 0x8000);
2455
2456 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2457 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2458 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2459 amdgpu_ring_write(ring, tmp);
2460 amdgpu_ring_write(ring, 0);
2461
2462 amdgpu_ring_commit(ring);
2463
2464 return 0;
2465 }
2466
gfx_v9_0_cp_gfx_resume(struct amdgpu_device * adev)2467 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2468 {
2469 struct amdgpu_ring *ring;
2470 u32 tmp;
2471 u32 rb_bufsz;
2472 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2473
2474 /* Set the write pointer delay */
2475 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2476
2477 /* set the RB to use vmid 0 */
2478 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2479
2480 /* Set ring buffer size */
2481 ring = &adev->gfx.gfx_ring[0];
2482 rb_bufsz = order_base_2(ring->ring_size / 8);
2483 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2484 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2485 #ifdef __BIG_ENDIAN
2486 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2487 #endif
2488 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2489
2490 /* Initialize the ring buffer's write pointers */
2491 ring->wptr = 0;
2492 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2493 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2494
2495 /* set the wb address wether it's enabled or not */
2496 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2497 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2498 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2499
2500 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2501 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2502 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2503
2504 mdelay(1);
2505 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2506
2507 rb_addr = ring->gpu_addr >> 8;
2508 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2509 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2510
2511 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2512 if (ring->use_doorbell) {
2513 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2514 DOORBELL_OFFSET, ring->doorbell_index);
2515 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2516 DOORBELL_EN, 1);
2517 } else {
2518 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2519 }
2520 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2521
2522 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2523 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2524 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2525
2526 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2527 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2528
2529
2530 /* start the ring */
2531 gfx_v9_0_cp_gfx_start(adev);
2532 ring->ready = true;
2533
2534 return 0;
2535 }
2536
gfx_v9_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2537 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2538 {
2539 int i;
2540
2541 if (enable) {
2542 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2543 } else {
2544 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2545 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2546 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2547 adev->gfx.compute_ring[i].ready = false;
2548 adev->gfx.kiq.ring.ready = false;
2549 }
2550 udelay(50);
2551 }
2552
gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device * adev)2553 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2554 {
2555 const struct gfx_firmware_header_v1_0 *mec_hdr;
2556 const __le32 *fw_data;
2557 unsigned i;
2558 u32 tmp;
2559
2560 if (!adev->gfx.mec_fw)
2561 return -EINVAL;
2562
2563 gfx_v9_0_cp_compute_enable(adev, false);
2564
2565 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2566 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2567
2568 fw_data = (const __le32 *)
2569 (adev->gfx.mec_fw->data +
2570 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2571 tmp = 0;
2572 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2573 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2574 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2575
2576 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2577 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2578 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2579 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2580
2581 /* MEC1 */
2582 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2583 mec_hdr->jt_offset);
2584 for (i = 0; i < mec_hdr->jt_size; i++)
2585 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2586 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2587
2588 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2589 adev->gfx.mec_fw_version);
2590 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2591
2592 return 0;
2593 }
2594
2595 /* KIQ functions */
gfx_v9_0_kiq_setting(struct amdgpu_ring * ring)2596 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2597 {
2598 uint32_t tmp;
2599 struct amdgpu_device *adev = ring->adev;
2600
2601 /* tell RLC which is KIQ queue */
2602 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2603 tmp &= 0xffffff00;
2604 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2605 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2606 tmp |= 0x80;
2607 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2608 }
2609
gfx_v9_0_kiq_kcq_enable(struct amdgpu_device * adev)2610 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2611 {
2612 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2613 uint32_t scratch, tmp = 0;
2614 uint64_t queue_mask = 0;
2615 int r, i;
2616
2617 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2618 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2619 continue;
2620
2621 /* This situation may be hit in the future if a new HW
2622 * generation exposes more than 64 queues. If so, the
2623 * definition of queue_mask needs updating */
2624 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2625 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2626 break;
2627 }
2628
2629 queue_mask |= (1ull << i);
2630 }
2631
2632 r = amdgpu_gfx_scratch_get(adev, &scratch);
2633 if (r) {
2634 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2635 return r;
2636 }
2637 WREG32(scratch, 0xCAFEDEAD);
2638
2639 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2640 if (r) {
2641 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2642 amdgpu_gfx_scratch_free(adev, scratch);
2643 return r;
2644 }
2645
2646 /* set resources */
2647 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2648 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2649 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2650 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2651 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2652 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2653 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2654 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2655 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2656 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2657 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2658 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2659 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2660
2661 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2662 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2663 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2664 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2665 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2666 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2667 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2668 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2669 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2670 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2671 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2672 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2673 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2674 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2675 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2676 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2677 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2678 }
2679 /* write to scratch for completion */
2680 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2681 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2682 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2683 amdgpu_ring_commit(kiq_ring);
2684
2685 for (i = 0; i < adev->usec_timeout; i++) {
2686 tmp = RREG32(scratch);
2687 if (tmp == 0xDEADBEEF)
2688 break;
2689 DRM_UDELAY(1);
2690 }
2691 if (i >= adev->usec_timeout) {
2692 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2693 scratch, tmp);
2694 r = -EINVAL;
2695 }
2696 amdgpu_gfx_scratch_free(adev, scratch);
2697
2698 return r;
2699 }
2700
gfx_v9_0_mqd_init(struct amdgpu_ring * ring)2701 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2702 {
2703 struct amdgpu_device *adev = ring->adev;
2704 struct v9_mqd *mqd = ring->mqd_ptr;
2705 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2706 uint32_t tmp;
2707
2708 mqd->header = 0xC0310800;
2709 mqd->compute_pipelinestat_enable = 0x00000001;
2710 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2711 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2712 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2713 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2714 mqd->compute_misc_reserved = 0x00000003;
2715
2716 mqd->dynamic_cu_mask_addr_lo =
2717 lower_32_bits(ring->mqd_gpu_addr
2718 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2719 mqd->dynamic_cu_mask_addr_hi =
2720 upper_32_bits(ring->mqd_gpu_addr
2721 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2722
2723 eop_base_addr = ring->eop_gpu_addr >> 8;
2724 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2725 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2726
2727 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2728 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2729 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2730 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2731
2732 mqd->cp_hqd_eop_control = tmp;
2733
2734 /* enable doorbell? */
2735 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2736
2737 if (ring->use_doorbell) {
2738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2739 DOORBELL_OFFSET, ring->doorbell_index);
2740 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2741 DOORBELL_EN, 1);
2742 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2743 DOORBELL_SOURCE, 0);
2744 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2745 DOORBELL_HIT, 0);
2746 } else {
2747 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2748 DOORBELL_EN, 0);
2749 }
2750
2751 mqd->cp_hqd_pq_doorbell_control = tmp;
2752
2753 /* disable the queue if it's active */
2754 ring->wptr = 0;
2755 mqd->cp_hqd_dequeue_request = 0;
2756 mqd->cp_hqd_pq_rptr = 0;
2757 mqd->cp_hqd_pq_wptr_lo = 0;
2758 mqd->cp_hqd_pq_wptr_hi = 0;
2759
2760 /* set the pointer to the MQD */
2761 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2762 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2763
2764 /* set MQD vmid to 0 */
2765 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2766 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2767 mqd->cp_mqd_control = tmp;
2768
2769 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2770 hqd_gpu_addr = ring->gpu_addr >> 8;
2771 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2772 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2773
2774 /* set up the HQD, this is similar to CP_RB0_CNTL */
2775 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2777 (order_base_2(ring->ring_size / 4) - 1));
2778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2779 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2780 #ifdef __BIG_ENDIAN
2781 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2782 #endif
2783 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2784 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2786 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2787 mqd->cp_hqd_pq_control = tmp;
2788
2789 /* set the wb address whether it's enabled or not */
2790 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2791 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2792 mqd->cp_hqd_pq_rptr_report_addr_hi =
2793 upper_32_bits(wb_gpu_addr) & 0xffff;
2794
2795 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2796 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2797 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2798 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2799
2800 tmp = 0;
2801 /* enable the doorbell if requested */
2802 if (ring->use_doorbell) {
2803 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2805 DOORBELL_OFFSET, ring->doorbell_index);
2806
2807 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2808 DOORBELL_EN, 1);
2809 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2810 DOORBELL_SOURCE, 0);
2811 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2812 DOORBELL_HIT, 0);
2813 }
2814
2815 mqd->cp_hqd_pq_doorbell_control = tmp;
2816
2817 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2818 ring->wptr = 0;
2819 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2820
2821 /* set the vmid for the queue */
2822 mqd->cp_hqd_vmid = 0;
2823
2824 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2825 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2826 mqd->cp_hqd_persistent_state = tmp;
2827
2828 /* set MIN_IB_AVAIL_SIZE */
2829 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2830 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2831 mqd->cp_hqd_ib_control = tmp;
2832
2833 /* activate the queue */
2834 mqd->cp_hqd_active = 1;
2835
2836 return 0;
2837 }
2838
gfx_v9_0_kiq_init_register(struct amdgpu_ring * ring)2839 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2840 {
2841 struct amdgpu_device *adev = ring->adev;
2842 struct v9_mqd *mqd = ring->mqd_ptr;
2843 int j;
2844
2845 /* disable wptr polling */
2846 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2847
2848 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2849 mqd->cp_hqd_eop_base_addr_lo);
2850 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2851 mqd->cp_hqd_eop_base_addr_hi);
2852
2853 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2854 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2855 mqd->cp_hqd_eop_control);
2856
2857 /* enable doorbell? */
2858 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2859 mqd->cp_hqd_pq_doorbell_control);
2860
2861 /* disable the queue if it's active */
2862 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2863 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2864 for (j = 0; j < adev->usec_timeout; j++) {
2865 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2866 break;
2867 udelay(1);
2868 }
2869 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2870 mqd->cp_hqd_dequeue_request);
2871 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2872 mqd->cp_hqd_pq_rptr);
2873 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2874 mqd->cp_hqd_pq_wptr_lo);
2875 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2876 mqd->cp_hqd_pq_wptr_hi);
2877 }
2878
2879 /* set the pointer to the MQD */
2880 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2881 mqd->cp_mqd_base_addr_lo);
2882 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2883 mqd->cp_mqd_base_addr_hi);
2884
2885 /* set MQD vmid to 0 */
2886 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2887 mqd->cp_mqd_control);
2888
2889 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2890 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2891 mqd->cp_hqd_pq_base_lo);
2892 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2893 mqd->cp_hqd_pq_base_hi);
2894
2895 /* set up the HQD, this is similar to CP_RB0_CNTL */
2896 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2897 mqd->cp_hqd_pq_control);
2898
2899 /* set the wb address whether it's enabled or not */
2900 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2901 mqd->cp_hqd_pq_rptr_report_addr_lo);
2902 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2903 mqd->cp_hqd_pq_rptr_report_addr_hi);
2904
2905 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2906 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2907 mqd->cp_hqd_pq_wptr_poll_addr_lo);
2908 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2909 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2910
2911 /* enable the doorbell if requested */
2912 if (ring->use_doorbell) {
2913 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2914 (AMDGPU_DOORBELL64_KIQ *2) << 2);
2915 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2916 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2917 }
2918
2919 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2920 mqd->cp_hqd_pq_doorbell_control);
2921
2922 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2923 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2924 mqd->cp_hqd_pq_wptr_lo);
2925 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2926 mqd->cp_hqd_pq_wptr_hi);
2927
2928 /* set the vmid for the queue */
2929 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2930
2931 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2932 mqd->cp_hqd_persistent_state);
2933
2934 /* activate the queue */
2935 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2936 mqd->cp_hqd_active);
2937
2938 if (ring->use_doorbell)
2939 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2940
2941 return 0;
2942 }
2943
gfx_v9_0_kiq_fini_register(struct amdgpu_ring * ring)2944 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
2945 {
2946 struct amdgpu_device *adev = ring->adev;
2947 int j;
2948
2949 /* disable the queue if it's active */
2950 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2951
2952 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2953
2954 for (j = 0; j < adev->usec_timeout; j++) {
2955 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2956 break;
2957 udelay(1);
2958 }
2959
2960 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
2961 DRM_DEBUG("KIQ dequeue request failed.\n");
2962
2963 /* Manual disable if dequeue request times out */
2964 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
2965 }
2966
2967 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2968 0);
2969 }
2970
2971 WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
2972 WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
2973 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
2974 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
2975 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
2976 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
2977 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
2978 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
2979
2980 return 0;
2981 }
2982
gfx_v9_0_kiq_init_queue(struct amdgpu_ring * ring)2983 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2984 {
2985 struct amdgpu_device *adev = ring->adev;
2986 struct v9_mqd *mqd = ring->mqd_ptr;
2987 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2988
2989 gfx_v9_0_kiq_setting(ring);
2990
2991 if (adev->in_gpu_reset) { /* for GPU_RESET case */
2992 /* reset MQD to a clean status */
2993 if (adev->gfx.mec.mqd_backup[mqd_idx])
2994 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2995
2996 /* reset ring buffer */
2997 ring->wptr = 0;
2998 amdgpu_ring_clear_ring(ring);
2999
3000 mutex_lock(&adev->srbm_mutex);
3001 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3002 gfx_v9_0_kiq_init_register(ring);
3003 soc15_grbm_select(adev, 0, 0, 0, 0);
3004 mutex_unlock(&adev->srbm_mutex);
3005 } else {
3006 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3007 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3008 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3009 mutex_lock(&adev->srbm_mutex);
3010 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3011 gfx_v9_0_mqd_init(ring);
3012 gfx_v9_0_kiq_init_register(ring);
3013 soc15_grbm_select(adev, 0, 0, 0, 0);
3014 mutex_unlock(&adev->srbm_mutex);
3015
3016 if (adev->gfx.mec.mqd_backup[mqd_idx])
3017 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3018 }
3019
3020 return 0;
3021 }
3022
gfx_v9_0_kcq_init_queue(struct amdgpu_ring * ring)3023 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3024 {
3025 struct amdgpu_device *adev = ring->adev;
3026 struct v9_mqd *mqd = ring->mqd_ptr;
3027 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3028
3029 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3030 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3031 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3032 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3033 mutex_lock(&adev->srbm_mutex);
3034 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3035 gfx_v9_0_mqd_init(ring);
3036 soc15_grbm_select(adev, 0, 0, 0, 0);
3037 mutex_unlock(&adev->srbm_mutex);
3038
3039 if (adev->gfx.mec.mqd_backup[mqd_idx])
3040 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3041 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3042 /* reset MQD to a clean status */
3043 if (adev->gfx.mec.mqd_backup[mqd_idx])
3044 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3045
3046 /* reset ring buffer */
3047 ring->wptr = 0;
3048 amdgpu_ring_clear_ring(ring);
3049 } else {
3050 amdgpu_ring_clear_ring(ring);
3051 }
3052
3053 return 0;
3054 }
3055
gfx_v9_0_kiq_resume(struct amdgpu_device * adev)3056 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3057 {
3058 struct amdgpu_ring *ring = NULL;
3059 int r = 0, i;
3060
3061 gfx_v9_0_cp_compute_enable(adev, true);
3062
3063 ring = &adev->gfx.kiq.ring;
3064
3065 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3066 if (unlikely(r != 0))
3067 goto done;
3068
3069 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3070 if (!r) {
3071 r = gfx_v9_0_kiq_init_queue(ring);
3072 amdgpu_bo_kunmap(ring->mqd_obj);
3073 ring->mqd_ptr = NULL;
3074 }
3075 amdgpu_bo_unreserve(ring->mqd_obj);
3076 if (r)
3077 goto done;
3078
3079 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3080 ring = &adev->gfx.compute_ring[i];
3081
3082 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3083 if (unlikely(r != 0))
3084 goto done;
3085 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3086 if (!r) {
3087 r = gfx_v9_0_kcq_init_queue(ring);
3088 amdgpu_bo_kunmap(ring->mqd_obj);
3089 ring->mqd_ptr = NULL;
3090 }
3091 amdgpu_bo_unreserve(ring->mqd_obj);
3092 if (r)
3093 goto done;
3094 }
3095
3096 r = gfx_v9_0_kiq_kcq_enable(adev);
3097 done:
3098 return r;
3099 }
3100
gfx_v9_0_cp_resume(struct amdgpu_device * adev)3101 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3102 {
3103 int r, i;
3104 struct amdgpu_ring *ring;
3105
3106 if (!(adev->flags & AMD_IS_APU))
3107 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3108
3109 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3110 /* legacy firmware loading */
3111 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3112 if (r)
3113 return r;
3114
3115 r = gfx_v9_0_cp_compute_load_microcode(adev);
3116 if (r)
3117 return r;
3118 }
3119
3120 r = gfx_v9_0_cp_gfx_resume(adev);
3121 if (r)
3122 return r;
3123
3124 r = gfx_v9_0_kiq_resume(adev);
3125 if (r)
3126 return r;
3127
3128 ring = &adev->gfx.gfx_ring[0];
3129 r = amdgpu_ring_test_ring(ring);
3130 if (r) {
3131 ring->ready = false;
3132 return r;
3133 }
3134
3135 ring = &adev->gfx.kiq.ring;
3136 ring->ready = true;
3137 r = amdgpu_ring_test_ring(ring);
3138 if (r)
3139 ring->ready = false;
3140
3141 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3142 ring = &adev->gfx.compute_ring[i];
3143
3144 ring->ready = true;
3145 r = amdgpu_ring_test_ring(ring);
3146 if (r)
3147 ring->ready = false;
3148 }
3149
3150 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3151
3152 return 0;
3153 }
3154
gfx_v9_0_cp_enable(struct amdgpu_device * adev,bool enable)3155 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3156 {
3157 gfx_v9_0_cp_gfx_enable(adev, enable);
3158 gfx_v9_0_cp_compute_enable(adev, enable);
3159 }
3160
gfx_v9_0_hw_init(void * handle)3161 static int gfx_v9_0_hw_init(void *handle)
3162 {
3163 int r;
3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3165
3166 gfx_v9_0_init_golden_registers(adev);
3167
3168 gfx_v9_0_gpu_init(adev);
3169
3170 r = gfx_v9_0_csb_vram_pin(adev);
3171 if (r)
3172 return r;
3173
3174 r = gfx_v9_0_rlc_resume(adev);
3175 if (r)
3176 return r;
3177
3178 r = gfx_v9_0_cp_resume(adev);
3179 if (r)
3180 return r;
3181
3182 r = gfx_v9_0_ngg_en(adev);
3183 if (r)
3184 return r;
3185
3186 return r;
3187 }
3188
gfx_v9_0_kcq_disable(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3189 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
3190 {
3191 struct amdgpu_device *adev = kiq_ring->adev;
3192 uint32_t scratch, tmp = 0;
3193 int r, i;
3194
3195 r = amdgpu_gfx_scratch_get(adev, &scratch);
3196 if (r) {
3197 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
3198 return r;
3199 }
3200 WREG32(scratch, 0xCAFEDEAD);
3201
3202 r = amdgpu_ring_alloc(kiq_ring, 10);
3203 if (r) {
3204 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3205 amdgpu_gfx_scratch_free(adev, scratch);
3206 return r;
3207 }
3208
3209 /* unmap queues */
3210 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3211 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3212 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3213 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3214 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3215 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3216 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3217 amdgpu_ring_write(kiq_ring, 0);
3218 amdgpu_ring_write(kiq_ring, 0);
3219 amdgpu_ring_write(kiq_ring, 0);
3220 /* write to scratch for completion */
3221 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3222 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3223 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
3224 amdgpu_ring_commit(kiq_ring);
3225
3226 for (i = 0; i < adev->usec_timeout; i++) {
3227 tmp = RREG32(scratch);
3228 if (tmp == 0xDEADBEEF)
3229 break;
3230 DRM_UDELAY(1);
3231 }
3232 if (i >= adev->usec_timeout) {
3233 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
3234 r = -EINVAL;
3235 }
3236 amdgpu_gfx_scratch_free(adev, scratch);
3237 return r;
3238 }
3239
gfx_v9_0_hw_fini(void * handle)3240 static int gfx_v9_0_hw_fini(void *handle)
3241 {
3242 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3243 int i;
3244
3245 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3246 AMD_PG_STATE_UNGATE);
3247
3248 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3249 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3250
3251 /* disable KCQ to avoid CPC touch memory not valid anymore */
3252 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3253 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3254
3255 if (amdgpu_sriov_vf(adev)) {
3256 gfx_v9_0_cp_gfx_enable(adev, false);
3257 /* must disable polling for SRIOV when hw finished, otherwise
3258 * CPC engine may still keep fetching WB address which is already
3259 * invalid after sw finished and trigger DMAR reading error in
3260 * hypervisor side.
3261 */
3262 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3263 return 0;
3264 }
3265
3266 /* Use deinitialize sequence from CAIL when unbinding device from driver,
3267 * otherwise KIQ is hanging when binding back
3268 */
3269 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3270 mutex_lock(&adev->srbm_mutex);
3271 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3272 adev->gfx.kiq.ring.pipe,
3273 adev->gfx.kiq.ring.queue, 0);
3274 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3275 soc15_grbm_select(adev, 0, 0, 0, 0);
3276 mutex_unlock(&adev->srbm_mutex);
3277 }
3278
3279 gfx_v9_0_cp_enable(adev, false);
3280 gfx_v9_0_rlc_stop(adev);
3281
3282 gfx_v9_0_csb_vram_unpin(adev);
3283
3284 return 0;
3285 }
3286
gfx_v9_0_suspend(void * handle)3287 static int gfx_v9_0_suspend(void *handle)
3288 {
3289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3290
3291 adev->gfx.in_suspend = true;
3292 return gfx_v9_0_hw_fini(adev);
3293 }
3294
gfx_v9_0_resume(void * handle)3295 static int gfx_v9_0_resume(void *handle)
3296 {
3297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3298 int r;
3299
3300 r = gfx_v9_0_hw_init(adev);
3301 adev->gfx.in_suspend = false;
3302 return r;
3303 }
3304
gfx_v9_0_is_idle(void * handle)3305 static bool gfx_v9_0_is_idle(void *handle)
3306 {
3307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3308
3309 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3310 GRBM_STATUS, GUI_ACTIVE))
3311 return false;
3312 else
3313 return true;
3314 }
3315
gfx_v9_0_wait_for_idle(void * handle)3316 static int gfx_v9_0_wait_for_idle(void *handle)
3317 {
3318 unsigned i;
3319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3320
3321 for (i = 0; i < adev->usec_timeout; i++) {
3322 if (gfx_v9_0_is_idle(handle))
3323 return 0;
3324 udelay(1);
3325 }
3326 return -ETIMEDOUT;
3327 }
3328
gfx_v9_0_soft_reset(void * handle)3329 static int gfx_v9_0_soft_reset(void *handle)
3330 {
3331 u32 grbm_soft_reset = 0;
3332 u32 tmp;
3333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3334
3335 /* GRBM_STATUS */
3336 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3337 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3338 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3339 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3340 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3341 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3342 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3343 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3344 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3345 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3346 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3347 }
3348
3349 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3350 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3351 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3352 }
3353
3354 /* GRBM_STATUS2 */
3355 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3356 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3357 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3358 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3359
3360
3361 if (grbm_soft_reset) {
3362 /* stop the rlc */
3363 gfx_v9_0_rlc_stop(adev);
3364
3365 /* Disable GFX parsing/prefetching */
3366 gfx_v9_0_cp_gfx_enable(adev, false);
3367
3368 /* Disable MEC parsing/prefetching */
3369 gfx_v9_0_cp_compute_enable(adev, false);
3370
3371 if (grbm_soft_reset) {
3372 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3373 tmp |= grbm_soft_reset;
3374 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3375 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3376 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3377
3378 udelay(50);
3379
3380 tmp &= ~grbm_soft_reset;
3381 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3382 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3383 }
3384
3385 /* Wait a little for things to settle down */
3386 udelay(50);
3387 }
3388 return 0;
3389 }
3390
gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device * adev)3391 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3392 {
3393 uint64_t clock;
3394
3395 mutex_lock(&adev->gfx.gpu_clock_mutex);
3396 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3397 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3398 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3399 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3400 return clock;
3401 }
3402
gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)3403 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3404 uint32_t vmid,
3405 uint32_t gds_base, uint32_t gds_size,
3406 uint32_t gws_base, uint32_t gws_size,
3407 uint32_t oa_base, uint32_t oa_size)
3408 {
3409 struct amdgpu_device *adev = ring->adev;
3410
3411 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3412 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3413
3414 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3415 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3416
3417 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3418 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3419
3420 /* GDS Base */
3421 gfx_v9_0_write_data_to_reg(ring, 0, false,
3422 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3423 gds_base);
3424
3425 /* GDS Size */
3426 gfx_v9_0_write_data_to_reg(ring, 0, false,
3427 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3428 gds_size);
3429
3430 /* GWS */
3431 gfx_v9_0_write_data_to_reg(ring, 0, false,
3432 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3433 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3434
3435 /* OA */
3436 gfx_v9_0_write_data_to_reg(ring, 0, false,
3437 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3438 (1 << (oa_size + oa_base)) - (1 << oa_base));
3439 }
3440
gfx_v9_0_early_init(void * handle)3441 static int gfx_v9_0_early_init(void *handle)
3442 {
3443 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3444
3445 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3446 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3447 gfx_v9_0_set_ring_funcs(adev);
3448 gfx_v9_0_set_irq_funcs(adev);
3449 gfx_v9_0_set_gds_init(adev);
3450 gfx_v9_0_set_rlc_funcs(adev);
3451
3452 return 0;
3453 }
3454
gfx_v9_0_late_init(void * handle)3455 static int gfx_v9_0_late_init(void *handle)
3456 {
3457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3458 int r;
3459
3460 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3461 if (r)
3462 return r;
3463
3464 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3465 if (r)
3466 return r;
3467
3468 return 0;
3469 }
3470
gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device * adev)3471 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3472 {
3473 uint32_t rlc_setting, data;
3474 unsigned i;
3475
3476 if (adev->gfx.rlc.in_safe_mode)
3477 return;
3478
3479 /* if RLC is not enabled, do nothing */
3480 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3481 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3482 return;
3483
3484 if (adev->cg_flags &
3485 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3486 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3487 data = RLC_SAFE_MODE__CMD_MASK;
3488 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3489 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3490
3491 /* wait for RLC_SAFE_MODE */
3492 for (i = 0; i < adev->usec_timeout; i++) {
3493 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3494 break;
3495 udelay(1);
3496 }
3497 adev->gfx.rlc.in_safe_mode = true;
3498 }
3499 }
3500
gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device * adev)3501 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3502 {
3503 uint32_t rlc_setting, data;
3504
3505 if (!adev->gfx.rlc.in_safe_mode)
3506 return;
3507
3508 /* if RLC is not enabled, do nothing */
3509 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3510 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3511 return;
3512
3513 if (adev->cg_flags &
3514 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3515 /*
3516 * Try to exit safe mode only if it is already in safe
3517 * mode.
3518 */
3519 data = RLC_SAFE_MODE__CMD_MASK;
3520 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3521 adev->gfx.rlc.in_safe_mode = false;
3522 }
3523 }
3524
gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)3525 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3526 bool enable)
3527 {
3528 gfx_v9_0_enter_rlc_safe_mode(adev);
3529
3530 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3531 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3532 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3533 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3534 } else {
3535 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3536 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3537 }
3538
3539 gfx_v9_0_exit_rlc_safe_mode(adev);
3540 }
3541
gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device * adev,bool enable)3542 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3543 bool enable)
3544 {
3545 /* TODO: double check if we need to perform under safe mode */
3546 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3547
3548 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3549 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3550 else
3551 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3552
3553 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3554 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3555 else
3556 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3557
3558 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3559 }
3560
gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)3561 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3562 bool enable)
3563 {
3564 uint32_t data, def;
3565
3566 /* It is disabled by HW by default */
3567 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3568 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3569 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3570
3571 if (adev->asic_type != CHIP_VEGA12)
3572 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3573
3574 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3575 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3576 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3577
3578 /* only for Vega10 & Raven1 */
3579 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3580
3581 if (def != data)
3582 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3583
3584 /* MGLS is a global flag to control all MGLS in GFX */
3585 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3586 /* 2 - RLC memory Light sleep */
3587 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3588 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3589 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3590 if (def != data)
3591 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3592 }
3593 /* 3 - CP memory Light sleep */
3594 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3595 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3596 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3597 if (def != data)
3598 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3599 }
3600 }
3601 } else {
3602 /* 1 - MGCG_OVERRIDE */
3603 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3604
3605 if (adev->asic_type != CHIP_VEGA12)
3606 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3607
3608 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3609 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3610 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3611 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3612
3613 if (def != data)
3614 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3615
3616 /* 2 - disable MGLS in RLC */
3617 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3618 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3619 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3620 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3621 }
3622
3623 /* 3 - disable MGLS in CP */
3624 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3625 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3626 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3627 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3628 }
3629 }
3630 }
3631
gfx_v9_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)3632 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3633 bool enable)
3634 {
3635 uint32_t data, def;
3636
3637 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3638
3639 /* Enable 3D CGCG/CGLS */
3640 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3641 /* write cmd to clear cgcg/cgls ov */
3642 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3643 /* unset CGCG override */
3644 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3645 /* update CGCG and CGLS override bits */
3646 if (def != data)
3647 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3648
3649 /* enable 3Dcgcg FSM(0x0000363f) */
3650 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3651
3652 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3653 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3654 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3655 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3656 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3657 if (def != data)
3658 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3659
3660 /* set IDLE_POLL_COUNT(0x00900100) */
3661 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3662 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3663 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3664 if (def != data)
3665 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3666 } else {
3667 /* Disable CGCG/CGLS */
3668 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3669 /* disable cgcg, cgls should be disabled */
3670 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3671 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3672 /* disable cgcg and cgls in FSM */
3673 if (def != data)
3674 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3675 }
3676
3677 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3678 }
3679
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)3680 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3681 bool enable)
3682 {
3683 uint32_t def, data;
3684
3685 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3686
3687 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3688 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3689 /* unset CGCG override */
3690 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3691 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3692 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3693 else
3694 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3695 /* update CGCG and CGLS override bits */
3696 if (def != data)
3697 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3698
3699 /* enable cgcg FSM(0x0000363F) */
3700 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3701
3702 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3703 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3704 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3705 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3706 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3707 if (def != data)
3708 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3709
3710 /* set IDLE_POLL_COUNT(0x00900100) */
3711 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3712 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3713 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3714 if (def != data)
3715 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3716 } else {
3717 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3718 /* reset CGCG/CGLS bits */
3719 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3720 /* disable cgcg and cgls in FSM */
3721 if (def != data)
3722 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3723 }
3724
3725 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3726 }
3727
gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)3728 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3729 bool enable)
3730 {
3731 if (enable) {
3732 /* CGCG/CGLS should be enabled after MGCG/MGLS
3733 * === MGCG + MGLS ===
3734 */
3735 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3736 /* === CGCG /CGLS for GFX 3D Only === */
3737 gfx_v9_0_update_3d_clock_gating(adev, enable);
3738 /* === CGCG + CGLS === */
3739 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3740 } else {
3741 /* CGCG/CGLS should be disabled before MGCG/MGLS
3742 * === CGCG + CGLS ===
3743 */
3744 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3745 /* === CGCG /CGLS for GFX 3D Only === */
3746 gfx_v9_0_update_3d_clock_gating(adev, enable);
3747 /* === MGCG + MGLS === */
3748 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3749 }
3750 return 0;
3751 }
3752
3753 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3754 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3755 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3756 };
3757
gfx_v9_0_set_powergating_state(void * handle,enum amd_powergating_state state)3758 static int gfx_v9_0_set_powergating_state(void *handle,
3759 enum amd_powergating_state state)
3760 {
3761 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3762 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3763
3764 switch (adev->asic_type) {
3765 case CHIP_RAVEN:
3766 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3767 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3768 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3769 } else {
3770 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3771 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3772 }
3773
3774 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3775 gfx_v9_0_enable_cp_power_gating(adev, true);
3776 else
3777 gfx_v9_0_enable_cp_power_gating(adev, false);
3778
3779 /* update gfx cgpg state */
3780 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3781
3782 /* update mgcg state */
3783 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3784
3785 /* set gfx off through smu */
3786 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
3787 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
3788 break;
3789 case CHIP_VEGA12:
3790 /* set gfx off through smu */
3791 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
3792 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
3793 break;
3794 default:
3795 break;
3796 }
3797
3798 return 0;
3799 }
3800
gfx_v9_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3801 static int gfx_v9_0_set_clockgating_state(void *handle,
3802 enum amd_clockgating_state state)
3803 {
3804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3805
3806 if (amdgpu_sriov_vf(adev))
3807 return 0;
3808
3809 switch (adev->asic_type) {
3810 case CHIP_VEGA10:
3811 case CHIP_VEGA12:
3812 case CHIP_VEGA20:
3813 case CHIP_RAVEN:
3814 gfx_v9_0_update_gfx_clock_gating(adev,
3815 state == AMD_CG_STATE_GATE ? true : false);
3816 break;
3817 default:
3818 break;
3819 }
3820 return 0;
3821 }
3822
gfx_v9_0_get_clockgating_state(void * handle,u32 * flags)3823 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3824 {
3825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3826 int data;
3827
3828 if (amdgpu_sriov_vf(adev))
3829 *flags = 0;
3830
3831 /* AMD_CG_SUPPORT_GFX_MGCG */
3832 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3833 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3834 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3835
3836 /* AMD_CG_SUPPORT_GFX_CGCG */
3837 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3838 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3839 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3840
3841 /* AMD_CG_SUPPORT_GFX_CGLS */
3842 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3843 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3844
3845 /* AMD_CG_SUPPORT_GFX_RLC_LS */
3846 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3847 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3848 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3849
3850 /* AMD_CG_SUPPORT_GFX_CP_LS */
3851 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3852 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3853 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3854
3855 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3856 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3857 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3858 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3859
3860 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3861 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3862 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3863 }
3864
gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)3865 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3866 {
3867 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3868 }
3869
gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)3870 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3871 {
3872 struct amdgpu_device *adev = ring->adev;
3873 u64 wptr;
3874
3875 /* XXX check if swapping is necessary on BE */
3876 if (ring->use_doorbell) {
3877 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3878 } else {
3879 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3880 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3881 }
3882
3883 return wptr;
3884 }
3885
gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)3886 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3887 {
3888 struct amdgpu_device *adev = ring->adev;
3889
3890 if (ring->use_doorbell) {
3891 /* XXX check if swapping is necessary on BE */
3892 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3893 WDOORBELL64(ring->doorbell_index, ring->wptr);
3894 } else {
3895 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3896 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3897 }
3898 }
3899
gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)3900 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3901 {
3902 struct amdgpu_device *adev = ring->adev;
3903 u32 ref_and_mask, reg_mem_engine;
3904 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3905
3906 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3907 switch (ring->me) {
3908 case 1:
3909 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3910 break;
3911 case 2:
3912 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3913 break;
3914 default:
3915 return;
3916 }
3917 reg_mem_engine = 0;
3918 } else {
3919 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3920 reg_mem_engine = 1; /* pfp */
3921 }
3922
3923 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3924 adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3925 adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3926 ref_and_mask, ref_and_mask, 0x20);
3927 }
3928
gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned vmid,bool ctx_switch)3929 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3930 struct amdgpu_ib *ib,
3931 unsigned vmid, bool ctx_switch)
3932 {
3933 u32 header, control = 0;
3934
3935 if (ib->flags & AMDGPU_IB_FLAG_CE)
3936 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3937 else
3938 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3939
3940 control |= ib->length_dw | (vmid << 24);
3941
3942 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3943 control |= INDIRECT_BUFFER_PRE_ENB(1);
3944
3945 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3946 gfx_v9_0_ring_emit_de_meta(ring);
3947 }
3948
3949 amdgpu_ring_write(ring, header);
3950 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3951 amdgpu_ring_write(ring,
3952 #ifdef __BIG_ENDIAN
3953 (2 << 0) |
3954 #endif
3955 lower_32_bits(ib->gpu_addr));
3956 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3957 amdgpu_ring_write(ring, control);
3958 }
3959
gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_ib * ib,unsigned vmid,bool ctx_switch)3960 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3961 struct amdgpu_ib *ib,
3962 unsigned vmid, bool ctx_switch)
3963 {
3964 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3965
3966 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3967 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3968 amdgpu_ring_write(ring,
3969 #ifdef __BIG_ENDIAN
3970 (2 << 0) |
3971 #endif
3972 lower_32_bits(ib->gpu_addr));
3973 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3974 amdgpu_ring_write(ring, control);
3975 }
3976
gfx_v9_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)3977 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3978 u64 seq, unsigned flags)
3979 {
3980 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3981 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3982 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3983
3984 /* RELEASE_MEM - flush caches, send int */
3985 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3986 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3987 EOP_TC_NC_ACTION_EN) :
3988 (EOP_TCL1_ACTION_EN |
3989 EOP_TC_ACTION_EN |
3990 EOP_TC_WB_ACTION_EN |
3991 EOP_TC_MD_ACTION_EN)) |
3992 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3993 EVENT_INDEX(5)));
3994 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3995
3996 /*
3997 * the address should be Qword aligned if 64bit write, Dword
3998 * aligned if only send 32bit data low (discard data high)
3999 */
4000 if (write64bit)
4001 BUG_ON(addr & 0x7);
4002 else
4003 BUG_ON(addr & 0x3);
4004 amdgpu_ring_write(ring, lower_32_bits(addr));
4005 amdgpu_ring_write(ring, upper_32_bits(addr));
4006 amdgpu_ring_write(ring, lower_32_bits(seq));
4007 amdgpu_ring_write(ring, upper_32_bits(seq));
4008 amdgpu_ring_write(ring, 0);
4009 }
4010
gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4011 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4012 {
4013 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4014 uint32_t seq = ring->fence_drv.sync_seq;
4015 uint64_t addr = ring->fence_drv.gpu_addr;
4016
4017 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4018 lower_32_bits(addr), upper_32_bits(addr),
4019 seq, 0xffffffff, 4);
4020 }
4021
gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4022 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4023 unsigned vmid, uint64_t pd_addr)
4024 {
4025 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4026
4027 /* compute doesn't have PFP */
4028 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4029 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4030 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4031 amdgpu_ring_write(ring, 0x0);
4032 }
4033 }
4034
gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4035 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4036 {
4037 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4038 }
4039
gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4040 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4041 {
4042 u64 wptr;
4043
4044 /* XXX check if swapping is necessary on BE */
4045 if (ring->use_doorbell)
4046 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4047 else
4048 BUG();
4049 return wptr;
4050 }
4051
gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring * ring,bool acquire)4052 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4053 bool acquire)
4054 {
4055 struct amdgpu_device *adev = ring->adev;
4056 int pipe_num, tmp, reg;
4057 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4058
4059 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4060
4061 /* first me only has 2 entries, GFX and HP3D */
4062 if (ring->me > 0)
4063 pipe_num -= 2;
4064
4065 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4066 tmp = RREG32(reg);
4067 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4068 WREG32(reg, tmp);
4069 }
4070
gfx_v9_0_pipe_reserve_resources(struct amdgpu_device * adev,struct amdgpu_ring * ring,bool acquire)4071 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4072 struct amdgpu_ring *ring,
4073 bool acquire)
4074 {
4075 int i, pipe;
4076 bool reserve;
4077 struct amdgpu_ring *iring;
4078
4079 mutex_lock(&adev->gfx.pipe_reserve_mutex);
4080 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4081 if (acquire)
4082 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4083 else
4084 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4085
4086 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4087 /* Clear all reservations - everyone reacquires all resources */
4088 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4089 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4090 true);
4091
4092 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4093 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4094 true);
4095 } else {
4096 /* Lower all pipes without a current reservation */
4097 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4098 iring = &adev->gfx.gfx_ring[i];
4099 pipe = amdgpu_gfx_queue_to_bit(adev,
4100 iring->me,
4101 iring->pipe,
4102 0);
4103 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4104 gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4105 }
4106
4107 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4108 iring = &adev->gfx.compute_ring[i];
4109 pipe = amdgpu_gfx_queue_to_bit(adev,
4110 iring->me,
4111 iring->pipe,
4112 0);
4113 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4114 gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4115 }
4116 }
4117
4118 mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4119 }
4120
gfx_v9_0_hqd_set_priority(struct amdgpu_device * adev,struct amdgpu_ring * ring,bool acquire)4121 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4122 struct amdgpu_ring *ring,
4123 bool acquire)
4124 {
4125 uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4126 uint32_t queue_priority = acquire ? 0xf : 0x0;
4127
4128 mutex_lock(&adev->srbm_mutex);
4129 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4130
4131 WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4132 WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4133
4134 soc15_grbm_select(adev, 0, 0, 0, 0);
4135 mutex_unlock(&adev->srbm_mutex);
4136 }
4137
gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring * ring,enum drm_sched_priority priority)4138 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4139 enum drm_sched_priority priority)
4140 {
4141 struct amdgpu_device *adev = ring->adev;
4142 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4143
4144 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4145 return;
4146
4147 gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4148 gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4149 }
4150
gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4151 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4152 {
4153 struct amdgpu_device *adev = ring->adev;
4154
4155 /* XXX check if swapping is necessary on BE */
4156 if (ring->use_doorbell) {
4157 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4158 WDOORBELL64(ring->doorbell_index, ring->wptr);
4159 } else{
4160 BUG(); /* only DOORBELL method supported on gfx9 now */
4161 }
4162 }
4163
gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4164 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4165 u64 seq, unsigned int flags)
4166 {
4167 struct amdgpu_device *adev = ring->adev;
4168
4169 /* we only allocate 32bit for each seq wb address */
4170 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4171
4172 /* write fence seq to the "addr" */
4173 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4174 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4175 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4176 amdgpu_ring_write(ring, lower_32_bits(addr));
4177 amdgpu_ring_write(ring, upper_32_bits(addr));
4178 amdgpu_ring_write(ring, lower_32_bits(seq));
4179
4180 if (flags & AMDGPU_FENCE_FLAG_INT) {
4181 /* set register to trigger INT */
4182 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4183 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4184 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4185 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4186 amdgpu_ring_write(ring, 0);
4187 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4188 }
4189 }
4190
gfx_v9_ring_emit_sb(struct amdgpu_ring * ring)4191 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4192 {
4193 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4194 amdgpu_ring_write(ring, 0);
4195 }
4196
gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring * ring)4197 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4198 {
4199 struct v9_ce_ib_state ce_payload = {0};
4200 uint64_t csa_addr;
4201 int cnt;
4202
4203 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4204 csa_addr = amdgpu_csa_vaddr(ring->adev);
4205
4206 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4207 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4208 WRITE_DATA_DST_SEL(8) |
4209 WR_CONFIRM) |
4210 WRITE_DATA_CACHE_POLICY(0));
4211 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4212 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4213 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4214 }
4215
gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring * ring)4216 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4217 {
4218 struct v9_de_ib_state de_payload = {0};
4219 uint64_t csa_addr, gds_addr;
4220 int cnt;
4221
4222 csa_addr = amdgpu_csa_vaddr(ring->adev);
4223 gds_addr = csa_addr + 4096;
4224 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4225 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4226
4227 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4229 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4230 WRITE_DATA_DST_SEL(8) |
4231 WR_CONFIRM) |
4232 WRITE_DATA_CACHE_POLICY(0));
4233 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4234 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4235 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4236 }
4237
gfx_v9_0_ring_emit_tmz(struct amdgpu_ring * ring,bool start)4238 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4239 {
4240 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4241 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4242 }
4243
gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4244 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4245 {
4246 uint32_t dw2 = 0;
4247
4248 if (amdgpu_sriov_vf(ring->adev))
4249 gfx_v9_0_ring_emit_ce_meta(ring);
4250
4251 gfx_v9_0_ring_emit_tmz(ring, true);
4252
4253 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4254 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4255 /* set load_global_config & load_global_uconfig */
4256 dw2 |= 0x8001;
4257 /* set load_cs_sh_regs */
4258 dw2 |= 0x01000000;
4259 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4260 dw2 |= 0x10002;
4261
4262 /* set load_ce_ram if preamble presented */
4263 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4264 dw2 |= 0x10000000;
4265 } else {
4266 /* still load_ce_ram if this is the first time preamble presented
4267 * although there is no context switch happens.
4268 */
4269 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4270 dw2 |= 0x10000000;
4271 }
4272
4273 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4274 amdgpu_ring_write(ring, dw2);
4275 amdgpu_ring_write(ring, 0);
4276 }
4277
gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)4278 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4279 {
4280 unsigned ret;
4281 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4282 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4283 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4284 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4285 ret = ring->wptr & ring->buf_mask;
4286 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4287 return ret;
4288 }
4289
gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)4290 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4291 {
4292 unsigned cur;
4293 BUG_ON(offset > ring->buf_mask);
4294 BUG_ON(ring->ring[offset] != 0x55aa55aa);
4295
4296 cur = (ring->wptr & ring->buf_mask) - 1;
4297 if (likely(cur > offset))
4298 ring->ring[offset] = cur - offset;
4299 else
4300 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4301 }
4302
gfx_v9_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg)4303 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4304 {
4305 struct amdgpu_device *adev = ring->adev;
4306
4307 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4308 amdgpu_ring_write(ring, 0 | /* src: register*/
4309 (5 << 8) | /* dst: memory */
4310 (1 << 20)); /* write confirm */
4311 amdgpu_ring_write(ring, reg);
4312 amdgpu_ring_write(ring, 0);
4313 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4314 adev->virt.reg_val_offs * 4));
4315 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4316 adev->virt.reg_val_offs * 4));
4317 }
4318
gfx_v9_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4319 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4320 uint32_t val)
4321 {
4322 uint32_t cmd = 0;
4323
4324 switch (ring->funcs->type) {
4325 case AMDGPU_RING_TYPE_GFX:
4326 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4327 break;
4328 case AMDGPU_RING_TYPE_KIQ:
4329 cmd = (1 << 16); /* no inc addr */
4330 break;
4331 default:
4332 cmd = WR_CONFIRM;
4333 break;
4334 }
4335 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4336 amdgpu_ring_write(ring, cmd);
4337 amdgpu_ring_write(ring, reg);
4338 amdgpu_ring_write(ring, 0);
4339 amdgpu_ring_write(ring, val);
4340 }
4341
gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4342 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4343 uint32_t val, uint32_t mask)
4344 {
4345 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4346 }
4347
gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4348 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4349 uint32_t reg0, uint32_t reg1,
4350 uint32_t ref, uint32_t mask)
4351 {
4352 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4353
4354 if (amdgpu_sriov_vf(ring->adev))
4355 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4356 ref, mask, 0x20);
4357 else
4358 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4359 ref, mask);
4360 }
4361
gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)4362 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4363 enum amdgpu_interrupt_state state)
4364 {
4365 switch (state) {
4366 case AMDGPU_IRQ_STATE_DISABLE:
4367 case AMDGPU_IRQ_STATE_ENABLE:
4368 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4369 TIME_STAMP_INT_ENABLE,
4370 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4371 break;
4372 default:
4373 break;
4374 }
4375 }
4376
gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4377 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4378 int me, int pipe,
4379 enum amdgpu_interrupt_state state)
4380 {
4381 u32 mec_int_cntl, mec_int_cntl_reg;
4382
4383 /*
4384 * amdgpu controls only the first MEC. That's why this function only
4385 * handles the setting of interrupts for this specific MEC. All other
4386 * pipes' interrupts are set by amdkfd.
4387 */
4388
4389 if (me == 1) {
4390 switch (pipe) {
4391 case 0:
4392 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4393 break;
4394 case 1:
4395 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4396 break;
4397 case 2:
4398 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4399 break;
4400 case 3:
4401 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4402 break;
4403 default:
4404 DRM_DEBUG("invalid pipe %d\n", pipe);
4405 return;
4406 }
4407 } else {
4408 DRM_DEBUG("invalid me %d\n", me);
4409 return;
4410 }
4411
4412 switch (state) {
4413 case AMDGPU_IRQ_STATE_DISABLE:
4414 mec_int_cntl = RREG32(mec_int_cntl_reg);
4415 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4416 TIME_STAMP_INT_ENABLE, 0);
4417 WREG32(mec_int_cntl_reg, mec_int_cntl);
4418 break;
4419 case AMDGPU_IRQ_STATE_ENABLE:
4420 mec_int_cntl = RREG32(mec_int_cntl_reg);
4421 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4422 TIME_STAMP_INT_ENABLE, 1);
4423 WREG32(mec_int_cntl_reg, mec_int_cntl);
4424 break;
4425 default:
4426 break;
4427 }
4428 }
4429
gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4430 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4431 struct amdgpu_irq_src *source,
4432 unsigned type,
4433 enum amdgpu_interrupt_state state)
4434 {
4435 switch (state) {
4436 case AMDGPU_IRQ_STATE_DISABLE:
4437 case AMDGPU_IRQ_STATE_ENABLE:
4438 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4439 PRIV_REG_INT_ENABLE,
4440 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4441 break;
4442 default:
4443 break;
4444 }
4445
4446 return 0;
4447 }
4448
gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4449 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4450 struct amdgpu_irq_src *source,
4451 unsigned type,
4452 enum amdgpu_interrupt_state state)
4453 {
4454 switch (state) {
4455 case AMDGPU_IRQ_STATE_DISABLE:
4456 case AMDGPU_IRQ_STATE_ENABLE:
4457 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4458 PRIV_INSTR_INT_ENABLE,
4459 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4460 default:
4461 break;
4462 }
4463
4464 return 0;
4465 }
4466
gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4467 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4468 struct amdgpu_irq_src *src,
4469 unsigned type,
4470 enum amdgpu_interrupt_state state)
4471 {
4472 switch (type) {
4473 case AMDGPU_CP_IRQ_GFX_EOP:
4474 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4475 break;
4476 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4477 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4478 break;
4479 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4480 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4481 break;
4482 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4483 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4484 break;
4485 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4486 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4487 break;
4488 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4489 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4490 break;
4491 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4492 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4493 break;
4494 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4495 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4496 break;
4497 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4498 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4499 break;
4500 default:
4501 break;
4502 }
4503 return 0;
4504 }
4505
gfx_v9_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4506 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4507 struct amdgpu_irq_src *source,
4508 struct amdgpu_iv_entry *entry)
4509 {
4510 int i;
4511 u8 me_id, pipe_id, queue_id;
4512 struct amdgpu_ring *ring;
4513
4514 DRM_DEBUG("IH: CP EOP\n");
4515 me_id = (entry->ring_id & 0x0c) >> 2;
4516 pipe_id = (entry->ring_id & 0x03) >> 0;
4517 queue_id = (entry->ring_id & 0x70) >> 4;
4518
4519 switch (me_id) {
4520 case 0:
4521 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4522 break;
4523 case 1:
4524 case 2:
4525 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4526 ring = &adev->gfx.compute_ring[i];
4527 /* Per-queue interrupt is supported for MEC starting from VI.
4528 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4529 */
4530 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4531 amdgpu_fence_process(ring);
4532 }
4533 break;
4534 }
4535 return 0;
4536 }
4537
gfx_v9_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4538 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4539 struct amdgpu_irq_src *source,
4540 struct amdgpu_iv_entry *entry)
4541 {
4542 DRM_ERROR("Illegal register access in command stream\n");
4543 schedule_work(&adev->reset_work);
4544 return 0;
4545 }
4546
gfx_v9_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4547 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4548 struct amdgpu_irq_src *source,
4549 struct amdgpu_iv_entry *entry)
4550 {
4551 DRM_ERROR("Illegal instruction in command stream\n");
4552 schedule_work(&adev->reset_work);
4553 return 0;
4554 }
4555
gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)4556 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4557 struct amdgpu_irq_src *src,
4558 unsigned int type,
4559 enum amdgpu_interrupt_state state)
4560 {
4561 uint32_t tmp, target;
4562 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4563
4564 if (ring->me == 1)
4565 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4566 else
4567 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4568 target += ring->pipe;
4569
4570 switch (type) {
4571 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4572 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4573 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4574 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4575 GENERIC2_INT_ENABLE, 0);
4576 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4577
4578 tmp = RREG32(target);
4579 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4580 GENERIC2_INT_ENABLE, 0);
4581 WREG32(target, tmp);
4582 } else {
4583 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4584 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4585 GENERIC2_INT_ENABLE, 1);
4586 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4587
4588 tmp = RREG32(target);
4589 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4590 GENERIC2_INT_ENABLE, 1);
4591 WREG32(target, tmp);
4592 }
4593 break;
4594 default:
4595 BUG(); /* kiq only support GENERIC2_INT now */
4596 break;
4597 }
4598 return 0;
4599 }
4600
gfx_v9_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4601 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4602 struct amdgpu_irq_src *source,
4603 struct amdgpu_iv_entry *entry)
4604 {
4605 u8 me_id, pipe_id, queue_id;
4606 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4607
4608 me_id = (entry->ring_id & 0x0c) >> 2;
4609 pipe_id = (entry->ring_id & 0x03) >> 0;
4610 queue_id = (entry->ring_id & 0x70) >> 4;
4611 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4612 me_id, pipe_id, queue_id);
4613
4614 amdgpu_fence_process(ring);
4615 return 0;
4616 }
4617
4618 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4619 .name = "gfx_v9_0",
4620 .early_init = gfx_v9_0_early_init,
4621 .late_init = gfx_v9_0_late_init,
4622 .sw_init = gfx_v9_0_sw_init,
4623 .sw_fini = gfx_v9_0_sw_fini,
4624 .hw_init = gfx_v9_0_hw_init,
4625 .hw_fini = gfx_v9_0_hw_fini,
4626 .suspend = gfx_v9_0_suspend,
4627 .resume = gfx_v9_0_resume,
4628 .is_idle = gfx_v9_0_is_idle,
4629 .wait_for_idle = gfx_v9_0_wait_for_idle,
4630 .soft_reset = gfx_v9_0_soft_reset,
4631 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4632 .set_powergating_state = gfx_v9_0_set_powergating_state,
4633 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4634 };
4635
4636 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4637 .type = AMDGPU_RING_TYPE_GFX,
4638 .align_mask = 0xff,
4639 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4640 .support_64bit_ptrs = true,
4641 .vmhub = AMDGPU_GFXHUB,
4642 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4643 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4644 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4645 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4646 5 + /* COND_EXEC */
4647 7 + /* PIPELINE_SYNC */
4648 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4649 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4650 2 + /* VM_FLUSH */
4651 8 + /* FENCE for VM_FLUSH */
4652 20 + /* GDS switch */
4653 4 + /* double SWITCH_BUFFER,
4654 the first COND_EXEC jump to the place just
4655 prior to this double SWITCH_BUFFER */
4656 5 + /* COND_EXEC */
4657 7 + /* HDP_flush */
4658 4 + /* VGT_flush */
4659 14 + /* CE_META */
4660 31 + /* DE_META */
4661 3 + /* CNTX_CTRL */
4662 5 + /* HDP_INVL */
4663 8 + 8 + /* FENCE x2 */
4664 2, /* SWITCH_BUFFER */
4665 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4666 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4667 .emit_fence = gfx_v9_0_ring_emit_fence,
4668 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4669 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4670 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4671 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4672 .test_ring = gfx_v9_0_ring_test_ring,
4673 .test_ib = gfx_v9_0_ring_test_ib,
4674 .insert_nop = amdgpu_ring_insert_nop,
4675 .pad_ib = amdgpu_ring_generic_pad_ib,
4676 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4677 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4678 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4679 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4680 .emit_tmz = gfx_v9_0_ring_emit_tmz,
4681 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4682 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4683 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4684 };
4685
4686 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4687 .type = AMDGPU_RING_TYPE_COMPUTE,
4688 .align_mask = 0xff,
4689 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4690 .support_64bit_ptrs = true,
4691 .vmhub = AMDGPU_GFXHUB,
4692 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4693 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4694 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4695 .emit_frame_size =
4696 20 + /* gfx_v9_0_ring_emit_gds_switch */
4697 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4698 5 + /* hdp invalidate */
4699 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4700 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4701 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4702 2 + /* gfx_v9_0_ring_emit_vm_flush */
4703 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4704 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4705 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4706 .emit_fence = gfx_v9_0_ring_emit_fence,
4707 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4708 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4709 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4710 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4711 .test_ring = gfx_v9_0_ring_test_ring,
4712 .test_ib = gfx_v9_0_ring_test_ib,
4713 .insert_nop = amdgpu_ring_insert_nop,
4714 .pad_ib = amdgpu_ring_generic_pad_ib,
4715 .set_priority = gfx_v9_0_ring_set_priority_compute,
4716 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4717 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4718 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4719 };
4720
4721 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4722 .type = AMDGPU_RING_TYPE_KIQ,
4723 .align_mask = 0xff,
4724 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4725 .support_64bit_ptrs = true,
4726 .vmhub = AMDGPU_GFXHUB,
4727 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4728 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4729 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4730 .emit_frame_size =
4731 20 + /* gfx_v9_0_ring_emit_gds_switch */
4732 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4733 5 + /* hdp invalidate */
4734 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4735 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4736 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4737 2 + /* gfx_v9_0_ring_emit_vm_flush */
4738 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4739 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4740 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4741 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4742 .test_ring = gfx_v9_0_ring_test_ring,
4743 .test_ib = gfx_v9_0_ring_test_ib,
4744 .insert_nop = amdgpu_ring_insert_nop,
4745 .pad_ib = amdgpu_ring_generic_pad_ib,
4746 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4747 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4748 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4749 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4750 };
4751
gfx_v9_0_set_ring_funcs(struct amdgpu_device * adev)4752 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4753 {
4754 int i;
4755
4756 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4757
4758 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4759 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4760
4761 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4762 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4763 }
4764
4765 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4766 .set = gfx_v9_0_kiq_set_interrupt_state,
4767 .process = gfx_v9_0_kiq_irq,
4768 };
4769
4770 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4771 .set = gfx_v9_0_set_eop_interrupt_state,
4772 .process = gfx_v9_0_eop_irq,
4773 };
4774
4775 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4776 .set = gfx_v9_0_set_priv_reg_fault_state,
4777 .process = gfx_v9_0_priv_reg_irq,
4778 };
4779
4780 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4781 .set = gfx_v9_0_set_priv_inst_fault_state,
4782 .process = gfx_v9_0_priv_inst_irq,
4783 };
4784
gfx_v9_0_set_irq_funcs(struct amdgpu_device * adev)4785 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4786 {
4787 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4788 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4789
4790 adev->gfx.priv_reg_irq.num_types = 1;
4791 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4792
4793 adev->gfx.priv_inst_irq.num_types = 1;
4794 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4795
4796 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4797 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4798 }
4799
gfx_v9_0_set_rlc_funcs(struct amdgpu_device * adev)4800 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4801 {
4802 switch (adev->asic_type) {
4803 case CHIP_VEGA10:
4804 case CHIP_VEGA12:
4805 case CHIP_VEGA20:
4806 case CHIP_RAVEN:
4807 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4808 break;
4809 default:
4810 break;
4811 }
4812 }
4813
gfx_v9_0_set_gds_init(struct amdgpu_device * adev)4814 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4815 {
4816 /* init asci gds info */
4817 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4818 adev->gds.gws.total_size = 64;
4819 adev->gds.oa.total_size = 16;
4820
4821 if (adev->gds.mem.total_size == 64 * 1024) {
4822 adev->gds.mem.gfx_partition_size = 4096;
4823 adev->gds.mem.cs_partition_size = 4096;
4824
4825 adev->gds.gws.gfx_partition_size = 4;
4826 adev->gds.gws.cs_partition_size = 4;
4827
4828 adev->gds.oa.gfx_partition_size = 4;
4829 adev->gds.oa.cs_partition_size = 1;
4830 } else {
4831 adev->gds.mem.gfx_partition_size = 1024;
4832 adev->gds.mem.cs_partition_size = 1024;
4833
4834 adev->gds.gws.gfx_partition_size = 16;
4835 adev->gds.gws.cs_partition_size = 16;
4836
4837 adev->gds.oa.gfx_partition_size = 4;
4838 adev->gds.oa.cs_partition_size = 4;
4839 }
4840 }
4841
gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)4842 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4843 u32 bitmap)
4844 {
4845 u32 data;
4846
4847 if (!bitmap)
4848 return;
4849
4850 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4851 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4852
4853 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4854 }
4855
gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device * adev)4856 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4857 {
4858 u32 data, mask;
4859
4860 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4861 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4862
4863 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4864 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4865
4866 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4867
4868 return (~data) & mask;
4869 }
4870
gfx_v9_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)4871 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4872 struct amdgpu_cu_info *cu_info)
4873 {
4874 int i, j, k, counter, active_cu_number = 0;
4875 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4876 unsigned disable_masks[4 * 2];
4877
4878 if (!adev || !cu_info)
4879 return -EINVAL;
4880
4881 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4882
4883 mutex_lock(&adev->grbm_idx_mutex);
4884 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4885 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4886 mask = 1;
4887 ao_bitmap = 0;
4888 counter = 0;
4889 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4890 if (i < 4 && j < 2)
4891 gfx_v9_0_set_user_cu_inactive_bitmap(
4892 adev, disable_masks[i * 2 + j]);
4893 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4894 cu_info->bitmap[i][j] = bitmap;
4895
4896 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4897 if (bitmap & mask) {
4898 if (counter < adev->gfx.config.max_cu_per_sh)
4899 ao_bitmap |= mask;
4900 counter ++;
4901 }
4902 mask <<= 1;
4903 }
4904 active_cu_number += counter;
4905 if (i < 2 && j < 2)
4906 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4907 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4908 }
4909 }
4910 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4911 mutex_unlock(&adev->grbm_idx_mutex);
4912
4913 cu_info->number = active_cu_number;
4914 cu_info->ao_cu_mask = ao_cu_mask;
4915 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4916
4917 return 0;
4918 }
4919
4920 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4921 {
4922 .type = AMD_IP_BLOCK_TYPE_GFX,
4923 .major = 9,
4924 .minor = 0,
4925 .rev = 0,
4926 .funcs = &gfx_v9_0_ip_funcs,
4927 };
4928
