1 /*
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef __MLX5_FPGA_IPSEC_H__
35 #define __MLX5_FPGA_IPSEC_H__
36
37 #include "accel/ipsec.h"
38 #include "fs_cmd.h"
39
40 #ifdef CONFIG_MLX5_FPGA
41
42 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev);
43 unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev);
44 int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
45 unsigned int counters_count);
46
47 void *mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
48 struct mlx5_accel_esp_xfrm *accel_xfrm,
49 const __be32 saddr[4],
50 const __be32 daddr[4],
51 const __be32 spi, bool is_ipv6);
52 void mlx5_fpga_ipsec_delete_sa_ctx(void *context);
53
54 int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev);
55 void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev);
56 void mlx5_fpga_ipsec_build_fs_cmds(void);
57
58 struct mlx5_accel_esp_xfrm *
59 mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
60 const struct mlx5_accel_esp_xfrm_attrs *attrs,
61 u32 flags);
62 void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm);
63 int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
64 const struct mlx5_accel_esp_xfrm_attrs *attrs);
65
66 const struct mlx5_flow_cmds *
67 mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type);
68
69 #else
70
mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev * mdev)71 static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
72 {
73 return 0;
74 }
75
76 static inline unsigned int
mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev * mdev)77 mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev)
78 {
79 return 0;
80 }
81
mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev * mdev,u64 * counters)82 static inline int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev,
83 u64 *counters)
84 {
85 return 0;
86 }
87
88 static inline void *
mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev * mdev,struct mlx5_accel_esp_xfrm * accel_xfrm,const __be32 saddr[4],const __be32 daddr[4],const __be32 spi,bool is_ipv6)89 mlx5_fpga_ipsec_create_sa_ctx(struct mlx5_core_dev *mdev,
90 struct mlx5_accel_esp_xfrm *accel_xfrm,
91 const __be32 saddr[4],
92 const __be32 daddr[4],
93 const __be32 spi, bool is_ipv6)
94 {
95 return NULL;
96 }
97
mlx5_fpga_ipsec_delete_sa_ctx(void * context)98 static inline void mlx5_fpga_ipsec_delete_sa_ctx(void *context)
99 {
100 }
101
mlx5_fpga_ipsec_init(struct mlx5_core_dev * mdev)102 static inline int mlx5_fpga_ipsec_init(struct mlx5_core_dev *mdev)
103 {
104 return 0;
105 }
106
mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev * mdev)107 static inline void mlx5_fpga_ipsec_cleanup(struct mlx5_core_dev *mdev)
108 {
109 }
110
mlx5_fpga_ipsec_build_fs_cmds(void)111 static inline void mlx5_fpga_ipsec_build_fs_cmds(void)
112 {
113 }
114
115 static inline struct mlx5_accel_esp_xfrm *
mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev * mdev,const struct mlx5_accel_esp_xfrm_attrs * attrs,u32 flags)116 mlx5_fpga_esp_create_xfrm(struct mlx5_core_dev *mdev,
117 const struct mlx5_accel_esp_xfrm_attrs *attrs,
118 u32 flags)
119 {
120 return ERR_PTR(-EOPNOTSUPP);
121 }
122
mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm * xfrm)123 static inline void mlx5_fpga_esp_destroy_xfrm(struct mlx5_accel_esp_xfrm *xfrm)
124 {
125 }
126
127 static inline int
mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm * xfrm,const struct mlx5_accel_esp_xfrm_attrs * attrs)128 mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
129 const struct mlx5_accel_esp_xfrm_attrs *attrs)
130 {
131 return -EOPNOTSUPP;
132 }
133
134 static inline const struct mlx5_flow_cmds *
mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)135 mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
136 {
137 return mlx5_fs_cmd_get_default(type);
138 }
139
140 #endif /* CONFIG_MLX5_FPGA */
141
142 #endif /* __MLX5_FPGA_SADB_H__ */
143
