1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SAMSUNG EXYNOS5250 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. 9 * EXYNOS5250 based board files can include this file and provide 10 * values for board specfic bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, 14 * additional nodes can be added to this file. 15 */ 16 17#include <dt-bindings/clock/exynos5250.h> 18#include "exynos5.dtsi" 19#include "exynos4-cpu-thermal.dtsi" 20#include <dt-bindings/clock/exynos-audss-clk.h> 21 22/ { 23 compatible = "samsung,exynos5250", "samsung,exynos5"; 24 25 aliases { 26 spi0 = &spi_0; 27 spi1 = &spi_1; 28 spi2 = &spi_2; 29 gsc0 = &gsc_0; 30 gsc1 = &gsc_1; 31 gsc2 = &gsc_2; 32 gsc3 = &gsc_3; 33 mshc0 = &mmc_0; 34 mshc1 = &mmc_1; 35 mshc2 = &mmc_2; 36 mshc3 = &mmc_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7; 41 i2c8 = &i2c_8; 42 i2c9 = &i2c_9; 43 pinctrl0 = &pinctrl_0; 44 pinctrl1 = &pinctrl_1; 45 pinctrl2 = &pinctrl_2; 46 pinctrl3 = &pinctrl_3; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a15"; 56 reg = <0>; 57 clock-frequency = <1700000000>; 58 clocks = <&clock CLK_ARM_CLK>; 59 clock-names = "cpu"; 60 clock-latency = <140000>; 61 62 operating-points = < 63 1700000 1300000 64 1600000 1250000 65 1500000 1225000 66 1400000 1200000 67 1300000 1150000 68 1200000 1125000 69 1100000 1100000 70 1000000 1075000 71 900000 1050000 72 800000 1025000 73 700000 1012500 74 600000 1000000 75 500000 975000 76 400000 950000 77 300000 937500 78 200000 925000 79 >; 80 #cooling-cells = <2>; /* min followed by max */ 81 }; 82 cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a15"; 85 reg = <1>; 86 clock-frequency = <1700000000>; 87 clocks = <&clock CLK_ARM_CLK>; 88 clock-names = "cpu"; 89 clock-latency = <140000>; 90 91 operating-points = < 92 1700000 1300000 93 1600000 1250000 94 1500000 1225000 95 1400000 1200000 96 1300000 1150000 97 1200000 1125000 98 1100000 1100000 99 1000000 1075000 100 900000 1050000 101 800000 1025000 102 700000 1012500 103 600000 1000000 104 500000 975000 105 400000 950000 106 300000 937500 107 200000 925000 108 >; 109 #cooling-cells = <2>; /* min followed by max */ 110 }; 111 }; 112 113 soc: soc { 114 sysram@2020000 { 115 compatible = "mmio-sram"; 116 reg = <0x02020000 0x30000>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0 0x02020000 0x30000>; 120 121 smp-sysram@0 { 122 compatible = "samsung,exynos4210-sysram"; 123 reg = <0x0 0x1000>; 124 }; 125 126 smp-sysram@2f000 { 127 compatible = "samsung,exynos4210-sysram-ns"; 128 reg = <0x2f000 0x1000>; 129 }; 130 }; 131 132 pd_gsc: power-domain@10044000 { 133 compatible = "samsung,exynos4210-pd"; 134 reg = <0x10044000 0x20>; 135 #power-domain-cells = <0>; 136 label = "GSC"; 137 }; 138 139 pd_mfc: power-domain@10044040 { 140 compatible = "samsung,exynos4210-pd"; 141 reg = <0x10044040 0x20>; 142 #power-domain-cells = <0>; 143 label = "MFC"; 144 }; 145 146 pd_g3d: power-domain@10044060 { 147 compatible = "samsung,exynos4210-pd"; 148 reg = <0x10044060 0x20>; 149 #power-domain-cells = <0>; 150 label = "G3D"; 151 }; 152 153 pd_disp1: power-domain@100440a0 { 154 compatible = "samsung,exynos4210-pd"; 155 reg = <0x100440A0 0x20>; 156 #power-domain-cells = <0>; 157 label = "DISP1"; 158 }; 159 160 pd_mau: power-domain@100440c0 { 161 compatible = "samsung,exynos4210-pd"; 162 reg = <0x100440C0 0x20>; 163 #power-domain-cells = <0>; 164 label = "MAU"; 165 }; 166 167 clock: clock-controller@10010000 { 168 compatible = "samsung,exynos5250-clock"; 169 reg = <0x10010000 0x30000>; 170 #clock-cells = <1>; 171 }; 172 173 clock_audss: audss-clock-controller@3810000 { 174 compatible = "samsung,exynos5250-audss-clock"; 175 reg = <0x03810000 0x0C>; 176 #clock-cells = <1>; 177 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 178 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 179 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 180 power-domains = <&pd_mau>; 181 }; 182 183 timer { 184 compatible = "arm,armv7-timer"; 185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 189 /* 190 * Unfortunately we need this since some versions 191 * of U-Boot on Exynos don't set the CNTFRQ register, 192 * so we need the value from DT. 193 */ 194 clock-frequency = <24000000>; 195 }; 196 197 mct@101c0000 { 198 compatible = "samsung,exynos4210-mct"; 199 reg = <0x101C0000 0x800>; 200 interrupt-controller; 201 #interrupt-cells = <2>; 202 interrupt-parent = <&mct_map>; 203 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 204 <4 0>, <5 0>; 205 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 206 clock-names = "fin_pll", "mct"; 207 208 mct_map: mct-map { 209 #interrupt-cells = <2>; 210 #address-cells = <0>; 211 #size-cells = <0>; 212 interrupt-map = <0x0 0 &combiner 23 3>, 213 <0x1 0 &combiner 23 4>, 214 <0x2 0 &combiner 25 2>, 215 <0x3 0 &combiner 25 3>, 216 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>, 217 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>; 218 }; 219 }; 220 221 pmu { 222 compatible = "arm,cortex-a15-pmu"; 223 interrupt-parent = <&combiner>; 224 interrupts = <1 2>, <22 4>; 225 }; 226 227 pinctrl_0: pinctrl@11400000 { 228 compatible = "samsung,exynos5250-pinctrl"; 229 reg = <0x11400000 0x1000>; 230 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 231 232 wakup_eint: wakeup-interrupt-controller { 233 compatible = "samsung,exynos4210-wakeup-eint"; 234 interrupt-parent = <&gic>; 235 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 236 }; 237 }; 238 239 pinctrl_1: pinctrl@13400000 { 240 compatible = "samsung,exynos5250-pinctrl"; 241 reg = <0x13400000 0x1000>; 242 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 243 }; 244 245 pinctrl_2: pinctrl@10d10000 { 246 compatible = "samsung,exynos5250-pinctrl"; 247 reg = <0x10d10000 0x1000>; 248 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 249 }; 250 251 pinctrl_3: pinctrl@3860000 { 252 compatible = "samsung,exynos5250-pinctrl"; 253 reg = <0x03860000 0x1000>; 254 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 255 power-domains = <&pd_mau>; 256 }; 257 258 pmu_system_controller: system-controller@10040000 { 259 compatible = "samsung,exynos5250-pmu", "syscon"; 260 reg = <0x10040000 0x5000>; 261 clock-names = "clkout16"; 262 clocks = <&clock CLK_FIN_PLL>; 263 #clock-cells = <1>; 264 interrupt-controller; 265 #interrupt-cells = <3>; 266 interrupt-parent = <&gic>; 267 }; 268 269 watchdog@101d0000 { 270 compatible = "samsung,exynos5250-wdt"; 271 reg = <0x101D0000 0x100>; 272 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clock CLK_WDT>; 274 clock-names = "watchdog"; 275 samsung,syscon-phandle = <&pmu_system_controller>; 276 }; 277 278 mfc: codec@11000000 { 279 compatible = "samsung,mfc-v6"; 280 reg = <0x11000000 0x10000>; 281 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 282 power-domains = <&pd_mfc>; 283 clocks = <&clock CLK_MFC>; 284 clock-names = "mfc"; 285 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 286 iommu-names = "left", "right"; 287 }; 288 289 rotator: rotator@11c00000 { 290 compatible = "samsung,exynos5250-rotator"; 291 reg = <0x11C00000 0x64>; 292 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clock CLK_ROTATOR>; 294 clock-names = "rotator"; 295 iommus = <&sysmmu_rotator>; 296 }; 297 298 tmu: tmu@10060000 { 299 compatible = "samsung,exynos5250-tmu"; 300 reg = <0x10060000 0x100>; 301 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clock CLK_TMU>; 303 clock-names = "tmu_apbif"; 304 #thermal-sensor-cells = <0>; 305 }; 306 307 sata: sata@122f0000 { 308 compatible = "snps,dwc-ahci"; 309 samsung,sata-freq = <66>; 310 reg = <0x122F0000 0x1ff>; 311 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 313 clock-names = "sata", "sclk_sata"; 314 phys = <&sata_phy>; 315 phy-names = "sata-phy"; 316 status = "disabled"; 317 }; 318 319 sata_phy: sata-phy@12170000 { 320 compatible = "samsung,exynos5250-sata-phy"; 321 reg = <0x12170000 0x1ff>; 322 clocks = <&clock CLK_SATA_PHYCTRL>; 323 clock-names = "sata_phyctrl"; 324 #phy-cells = <0>; 325 samsung,syscon-phandle = <&pmu_system_controller>; 326 status = "disabled"; 327 }; 328 329 /* i2c_0-3 are defined in exynos5.dtsi */ 330 i2c_4: i2c@12ca0000 { 331 compatible = "samsung,s3c2440-i2c"; 332 reg = <0x12CA0000 0x100>; 333 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clocks = <&clock CLK_I2C4>; 337 clock-names = "i2c"; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&i2c4_bus>; 340 status = "disabled"; 341 }; 342 343 i2c_5: i2c@12cb0000 { 344 compatible = "samsung,s3c2440-i2c"; 345 reg = <0x12CB0000 0x100>; 346 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 clocks = <&clock CLK_I2C5>; 350 clock-names = "i2c"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&i2c5_bus>; 353 status = "disabled"; 354 }; 355 356 i2c_6: i2c@12cc0000 { 357 compatible = "samsung,s3c2440-i2c"; 358 reg = <0x12CC0000 0x100>; 359 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clocks = <&clock CLK_I2C6>; 363 clock-names = "i2c"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&i2c6_bus>; 366 status = "disabled"; 367 }; 368 369 i2c_7: i2c@12cd0000 { 370 compatible = "samsung,s3c2440-i2c"; 371 reg = <0x12CD0000 0x100>; 372 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 clocks = <&clock CLK_I2C7>; 376 clock-names = "i2c"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&i2c7_bus>; 379 status = "disabled"; 380 }; 381 382 i2c_8: i2c@12ce0000 { 383 compatible = "samsung,s3c2440-hdmiphy-i2c"; 384 reg = <0x12CE0000 0x1000>; 385 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 clocks = <&clock CLK_I2C_HDMI>; 389 clock-names = "i2c"; 390 status = "disabled"; 391 392 hdmiphy: hdmiphy@38 { 393 compatible = "samsung,exynos4212-hdmiphy"; 394 reg = <0x38>; 395 }; 396 }; 397 398 i2c_9: i2c@121d0000 { 399 compatible = "samsung,exynos5-sata-phy-i2c"; 400 reg = <0x121D0000 0x100>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 clocks = <&clock CLK_SATA_PHYI2C>; 404 clock-names = "i2c"; 405 status = "disabled"; 406 }; 407 408 spi_0: spi@12d20000 { 409 compatible = "samsung,exynos4210-spi"; 410 status = "disabled"; 411 reg = <0x12d20000 0x100>; 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 413 dmas = <&pdma0 5 414 &pdma0 4>; 415 dma-names = "tx", "rx"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 419 clock-names = "spi", "spi_busclk0"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&spi0_bus>; 422 }; 423 424 spi_1: spi@12d30000 { 425 compatible = "samsung,exynos4210-spi"; 426 status = "disabled"; 427 reg = <0x12d30000 0x100>; 428 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 429 dmas = <&pdma1 5 430 &pdma1 4>; 431 dma-names = "tx", "rx"; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 435 clock-names = "spi", "spi_busclk0"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&spi1_bus>; 438 }; 439 440 spi_2: spi@12d40000 { 441 compatible = "samsung,exynos4210-spi"; 442 status = "disabled"; 443 reg = <0x12d40000 0x100>; 444 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 445 dmas = <&pdma0 7 446 &pdma0 6>; 447 dma-names = "tx", "rx"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 451 clock-names = "spi", "spi_busclk0"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&spi2_bus>; 454 }; 455 456 mmc_0: mmc@12200000 { 457 compatible = "samsung,exynos5250-dw-mshc"; 458 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0x12200000 0x1000>; 462 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 463 clock-names = "biu", "ciu"; 464 fifo-depth = <0x80>; 465 status = "disabled"; 466 }; 467 468 mmc_1: mmc@12210000 { 469 compatible = "samsung,exynos5250-dw-mshc"; 470 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 reg = <0x12210000 0x1000>; 474 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 475 clock-names = "biu", "ciu"; 476 fifo-depth = <0x80>; 477 status = "disabled"; 478 }; 479 480 mmc_2: mmc@12220000 { 481 compatible = "samsung,exynos5250-dw-mshc"; 482 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <0x12220000 0x1000>; 486 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 487 clock-names = "biu", "ciu"; 488 fifo-depth = <0x80>; 489 status = "disabled"; 490 }; 491 492 mmc_3: mmc@12230000 { 493 compatible = "samsung,exynos5250-dw-mshc"; 494 reg = <0x12230000 0x1000>; 495 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 499 clock-names = "biu", "ciu"; 500 fifo-depth = <0x80>; 501 status = "disabled"; 502 }; 503 504 i2s0: i2s@3830000 { 505 compatible = "samsung,s5pv210-i2s"; 506 status = "disabled"; 507 reg = <0x03830000 0x100>; 508 dmas = <&pdma0 10 509 &pdma0 9 510 &pdma0 8>; 511 dma-names = "tx", "rx", "tx-sec"; 512 clocks = <&clock_audss EXYNOS_I2S_BUS>, 513 <&clock_audss EXYNOS_I2S_BUS>, 514 <&clock_audss EXYNOS_SCLK_I2S>; 515 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 516 samsung,idma-addr = <0x03000000>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2s0_bus>; 519 power-domains = <&pd_mau>; 520 #clock-cells = <1>; 521 #sound-dai-cells = <1>; 522 }; 523 524 i2s1: i2s@12d60000 { 525 compatible = "samsung,s3c6410-i2s"; 526 status = "disabled"; 527 reg = <0x12D60000 0x100>; 528 dmas = <&pdma1 12 529 &pdma1 11>; 530 dma-names = "tx", "rx"; 531 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 532 clock-names = "iis", "i2s_opclk0"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2s1_bus>; 535 power-domains = <&pd_mau>; 536 #sound-dai-cells = <1>; 537 }; 538 539 i2s2: i2s@12d70000 { 540 compatible = "samsung,s3c6410-i2s"; 541 status = "disabled"; 542 reg = <0x12D70000 0x100>; 543 dmas = <&pdma0 12 544 &pdma0 11>; 545 dma-names = "tx", "rx"; 546 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 547 clock-names = "iis", "i2s_opclk0"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2s2_bus>; 550 power-domains = <&pd_mau>; 551 #sound-dai-cells = <1>; 552 }; 553 554 usb_dwc3 { 555 compatible = "samsung,exynos5250-dwusb3"; 556 clocks = <&clock CLK_USB3>; 557 clock-names = "usbdrd30"; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 ranges; 561 562 usbdrd_dwc3: dwc3@12000000 { 563 compatible = "synopsys,dwc3"; 564 reg = <0x12000000 0x10000>; 565 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 566 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 567 phy-names = "usb2-phy", "usb3-phy"; 568 }; 569 }; 570 571 usbdrd_phy: phy@12100000 { 572 compatible = "samsung,exynos5250-usbdrd-phy"; 573 reg = <0x12100000 0x100>; 574 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 575 clock-names = "phy", "ref"; 576 samsung,pmu-syscon = <&pmu_system_controller>; 577 #phy-cells = <1>; 578 }; 579 580 ehci: usb@12110000 { 581 compatible = "samsung,exynos4210-ehci"; 582 reg = <0x12110000 0x100>; 583 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 584 585 clocks = <&clock CLK_USB2>; 586 clock-names = "usbhost"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 port@0 { 590 reg = <0>; 591 phys = <&usb2_phy_gen 1>; 592 }; 593 }; 594 595 ohci: usb@12120000 { 596 compatible = "samsung,exynos4210-ohci"; 597 reg = <0x12120000 0x100>; 598 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 599 600 clocks = <&clock CLK_USB2>; 601 clock-names = "usbhost"; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 port@0 { 605 reg = <0>; 606 phys = <&usb2_phy_gen 1>; 607 }; 608 }; 609 610 usb2_phy_gen: phy@12130000 { 611 compatible = "samsung,exynos5250-usb2-phy"; 612 reg = <0x12130000 0x100>; 613 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 614 clock-names = "phy", "ref"; 615 #phy-cells = <1>; 616 samsung,sysreg-phandle = <&sysreg_system_controller>; 617 samsung,pmureg-phandle = <&pmu_system_controller>; 618 }; 619 620 amba { 621 #address-cells = <1>; 622 #size-cells = <1>; 623 compatible = "simple-bus"; 624 interrupt-parent = <&gic>; 625 ranges; 626 627 pdma0: pdma@121a0000 { 628 compatible = "arm,pl330", "arm,primecell"; 629 reg = <0x121A0000 0x1000>; 630 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clock CLK_PDMA0>; 632 clock-names = "apb_pclk"; 633 #dma-cells = <1>; 634 #dma-channels = <8>; 635 #dma-requests = <32>; 636 }; 637 638 pdma1: pdma@121b0000 { 639 compatible = "arm,pl330", "arm,primecell"; 640 reg = <0x121B0000 0x1000>; 641 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clock CLK_PDMA1>; 643 clock-names = "apb_pclk"; 644 #dma-cells = <1>; 645 #dma-channels = <8>; 646 #dma-requests = <32>; 647 }; 648 649 mdma0: mdma@10800000 { 650 compatible = "arm,pl330", "arm,primecell"; 651 reg = <0x10800000 0x1000>; 652 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&clock CLK_MDMA0>; 654 clock-names = "apb_pclk"; 655 #dma-cells = <1>; 656 #dma-channels = <8>; 657 #dma-requests = <1>; 658 }; 659 660 mdma1: mdma@11c10000 { 661 compatible = "arm,pl330", "arm,primecell"; 662 reg = <0x11C10000 0x1000>; 663 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&clock CLK_MDMA1>; 665 clock-names = "apb_pclk"; 666 #dma-cells = <1>; 667 #dma-channels = <8>; 668 #dma-requests = <1>; 669 }; 670 }; 671 672 gsc_0: gsc@13e00000 { 673 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 674 reg = <0x13e00000 0x1000>; 675 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 676 power-domains = <&pd_gsc>; 677 clocks = <&clock CLK_GSCL0>; 678 clock-names = "gscl"; 679 iommus = <&sysmmu_gsc0>; 680 }; 681 682 gsc_1: gsc@13e10000 { 683 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 684 reg = <0x13e10000 0x1000>; 685 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 686 power-domains = <&pd_gsc>; 687 clocks = <&clock CLK_GSCL1>; 688 clock-names = "gscl"; 689 iommus = <&sysmmu_gsc1>; 690 }; 691 692 gsc_2: gsc@13e20000 { 693 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 694 reg = <0x13e20000 0x1000>; 695 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 696 power-domains = <&pd_gsc>; 697 clocks = <&clock CLK_GSCL2>; 698 clock-names = "gscl"; 699 iommus = <&sysmmu_gsc2>; 700 }; 701 702 gsc_3: gsc@13e30000 { 703 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; 704 reg = <0x13e30000 0x1000>; 705 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 706 power-domains = <&pd_gsc>; 707 clocks = <&clock CLK_GSCL3>; 708 clock-names = "gscl"; 709 iommus = <&sysmmu_gsc3>; 710 }; 711 712 hdmi: hdmi@14530000 { 713 compatible = "samsung,exynos4212-hdmi"; 714 reg = <0x14530000 0x70000>; 715 power-domains = <&pd_disp1>; 716 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 718 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 719 <&clock CLK_MOUT_HDMI>; 720 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 721 "sclk_hdmiphy", "mout_hdmi"; 722 samsung,syscon-phandle = <&pmu_system_controller>; 723 phy = <&hdmiphy>; 724 #sound-dai-cells = <0>; 725 status = "disabled"; 726 }; 727 728 hdmicec: cec@101b0000 { 729 compatible = "samsung,s5p-cec"; 730 reg = <0x101B0000 0x200>; 731 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&clock CLK_HDMI_CEC>; 733 clock-names = "hdmicec"; 734 samsung,syscon-phandle = <&pmu_system_controller>; 735 hdmi-phandle = <&hdmi>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&hdmi_cec>; 738 status = "disabled"; 739 }; 740 741 mixer: mixer@14450000 { 742 compatible = "samsung,exynos5250-mixer"; 743 reg = <0x14450000 0x10000>; 744 power-domains = <&pd_disp1>; 745 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 747 <&clock CLK_SCLK_HDMI>; 748 clock-names = "mixer", "hdmi", "sclk_hdmi"; 749 iommus = <&sysmmu_tv>; 750 status = "disabled"; 751 }; 752 753 dp_phy: video-phy { 754 compatible = "samsung,exynos5250-dp-video-phy"; 755 samsung,pmu-syscon = <&pmu_system_controller>; 756 #phy-cells = <0>; 757 }; 758 759 adc: adc@12d10000 { 760 compatible = "samsung,exynos-adc-v1"; 761 reg = <0x12D10000 0x100>; 762 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clock CLK_ADC>; 764 clock-names = "adc"; 765 #io-channel-cells = <1>; 766 io-channel-ranges; 767 samsung,syscon-phandle = <&pmu_system_controller>; 768 status = "disabled"; 769 }; 770 771 sysmmu_g2d: sysmmu@10a60000 { 772 compatible = "samsung,exynos-sysmmu"; 773 reg = <0x10A60000 0x1000>; 774 interrupt-parent = <&combiner>; 775 interrupts = <24 5>; 776 clock-names = "sysmmu", "master"; 777 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 778 #iommu-cells = <0>; 779 }; 780 781 sysmmu_mfc_r: sysmmu@11200000 { 782 compatible = "samsung,exynos-sysmmu"; 783 reg = <0x11200000 0x1000>; 784 interrupt-parent = <&combiner>; 785 interrupts = <6 2>; 786 power-domains = <&pd_mfc>; 787 clock-names = "sysmmu", "master"; 788 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 789 #iommu-cells = <0>; 790 }; 791 792 sysmmu_mfc_l: sysmmu@11210000 { 793 compatible = "samsung,exynos-sysmmu"; 794 reg = <0x11210000 0x1000>; 795 interrupt-parent = <&combiner>; 796 interrupts = <8 5>; 797 power-domains = <&pd_mfc>; 798 clock-names = "sysmmu", "master"; 799 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 800 #iommu-cells = <0>; 801 }; 802 803 sysmmu_rotator: sysmmu@11d40000 { 804 compatible = "samsung,exynos-sysmmu"; 805 reg = <0x11D40000 0x1000>; 806 interrupt-parent = <&combiner>; 807 interrupts = <4 0>; 808 clock-names = "sysmmu", "master"; 809 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 810 #iommu-cells = <0>; 811 }; 812 813 sysmmu_jpeg: sysmmu@11f20000 { 814 compatible = "samsung,exynos-sysmmu"; 815 reg = <0x11F20000 0x1000>; 816 interrupt-parent = <&combiner>; 817 interrupts = <4 2>; 818 power-domains = <&pd_gsc>; 819 clock-names = "sysmmu", "master"; 820 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 821 #iommu-cells = <0>; 822 }; 823 824 sysmmu_fimc_isp: sysmmu@13260000 { 825 compatible = "samsung,exynos-sysmmu"; 826 reg = <0x13260000 0x1000>; 827 interrupt-parent = <&combiner>; 828 interrupts = <10 6>; 829 clock-names = "sysmmu"; 830 clocks = <&clock CLK_SMMU_FIMC_ISP>; 831 #iommu-cells = <0>; 832 }; 833 834 sysmmu_fimc_drc: sysmmu@13270000 { 835 compatible = "samsung,exynos-sysmmu"; 836 reg = <0x13270000 0x1000>; 837 interrupt-parent = <&combiner>; 838 interrupts = <11 6>; 839 clock-names = "sysmmu"; 840 clocks = <&clock CLK_SMMU_FIMC_DRC>; 841 #iommu-cells = <0>; 842 }; 843 844 sysmmu_fimc_fd: sysmmu@132a0000 { 845 compatible = "samsung,exynos-sysmmu"; 846 reg = <0x132A0000 0x1000>; 847 interrupt-parent = <&combiner>; 848 interrupts = <5 0>; 849 clock-names = "sysmmu"; 850 clocks = <&clock CLK_SMMU_FIMC_FD>; 851 #iommu-cells = <0>; 852 }; 853 854 sysmmu_fimc_scc: sysmmu@13280000 { 855 compatible = "samsung,exynos-sysmmu"; 856 reg = <0x13280000 0x1000>; 857 interrupt-parent = <&combiner>; 858 interrupts = <5 2>; 859 clock-names = "sysmmu"; 860 clocks = <&clock CLK_SMMU_FIMC_SCC>; 861 #iommu-cells = <0>; 862 }; 863 864 sysmmu_fimc_scp: sysmmu@13290000 { 865 compatible = "samsung,exynos-sysmmu"; 866 reg = <0x13290000 0x1000>; 867 interrupt-parent = <&combiner>; 868 interrupts = <3 6>; 869 clock-names = "sysmmu"; 870 clocks = <&clock CLK_SMMU_FIMC_SCP>; 871 #iommu-cells = <0>; 872 }; 873 874 sysmmu_fimc_mcuctl: sysmmu@132b0000 { 875 compatible = "samsung,exynos-sysmmu"; 876 reg = <0x132B0000 0x1000>; 877 interrupt-parent = <&combiner>; 878 interrupts = <5 4>; 879 clock-names = "sysmmu"; 880 clocks = <&clock CLK_SMMU_FIMC_MCU>; 881 #iommu-cells = <0>; 882 }; 883 884 sysmmu_fimc_odc: sysmmu@132c0000 { 885 compatible = "samsung,exynos-sysmmu"; 886 reg = <0x132C0000 0x1000>; 887 interrupt-parent = <&combiner>; 888 interrupts = <11 0>; 889 clock-names = "sysmmu"; 890 clocks = <&clock CLK_SMMU_FIMC_ODC>; 891 #iommu-cells = <0>; 892 }; 893 894 sysmmu_fimc_dis0: sysmmu@132d0000 { 895 compatible = "samsung,exynos-sysmmu"; 896 reg = <0x132D0000 0x1000>; 897 interrupt-parent = <&combiner>; 898 interrupts = <10 4>; 899 clock-names = "sysmmu"; 900 clocks = <&clock CLK_SMMU_FIMC_DIS0>; 901 #iommu-cells = <0>; 902 }; 903 904 sysmmu_fimc_dis1: sysmmu@132e0000 { 905 compatible = "samsung,exynos-sysmmu"; 906 reg = <0x132E0000 0x1000>; 907 interrupt-parent = <&combiner>; 908 interrupts = <9 4>; 909 clock-names = "sysmmu"; 910 clocks = <&clock CLK_SMMU_FIMC_DIS1>; 911 #iommu-cells = <0>; 912 }; 913 914 sysmmu_fimc_3dnr: sysmmu@132f0000 { 915 compatible = "samsung,exynos-sysmmu"; 916 reg = <0x132F0000 0x1000>; 917 interrupt-parent = <&combiner>; 918 interrupts = <5 6>; 919 clock-names = "sysmmu"; 920 clocks = <&clock CLK_SMMU_FIMC_3DNR>; 921 #iommu-cells = <0>; 922 }; 923 924 sysmmu_fimc_lite0: sysmmu@13c40000 { 925 compatible = "samsung,exynos-sysmmu"; 926 reg = <0x13C40000 0x1000>; 927 interrupt-parent = <&combiner>; 928 interrupts = <3 4>; 929 power-domains = <&pd_gsc>; 930 clock-names = "sysmmu", "master"; 931 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 932 #iommu-cells = <0>; 933 }; 934 935 sysmmu_fimc_lite1: sysmmu@13c50000 { 936 compatible = "samsung,exynos-sysmmu"; 937 reg = <0x13C50000 0x1000>; 938 interrupt-parent = <&combiner>; 939 interrupts = <24 1>; 940 power-domains = <&pd_gsc>; 941 clock-names = "sysmmu", "master"; 942 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 943 #iommu-cells = <0>; 944 }; 945 946 sysmmu_gsc0: sysmmu@13e80000 { 947 compatible = "samsung,exynos-sysmmu"; 948 reg = <0x13E80000 0x1000>; 949 interrupt-parent = <&combiner>; 950 interrupts = <2 0>; 951 power-domains = <&pd_gsc>; 952 clock-names = "sysmmu", "master"; 953 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 954 #iommu-cells = <0>; 955 }; 956 957 sysmmu_gsc1: sysmmu@13e90000 { 958 compatible = "samsung,exynos-sysmmu"; 959 reg = <0x13E90000 0x1000>; 960 interrupt-parent = <&combiner>; 961 interrupts = <2 2>; 962 power-domains = <&pd_gsc>; 963 clock-names = "sysmmu", "master"; 964 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 965 #iommu-cells = <0>; 966 }; 967 968 sysmmu_gsc2: sysmmu@13ea0000 { 969 compatible = "samsung,exynos-sysmmu"; 970 reg = <0x13EA0000 0x1000>; 971 interrupt-parent = <&combiner>; 972 interrupts = <2 4>; 973 power-domains = <&pd_gsc>; 974 clock-names = "sysmmu", "master"; 975 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 976 #iommu-cells = <0>; 977 }; 978 979 sysmmu_gsc3: sysmmu@13eb0000 { 980 compatible = "samsung,exynos-sysmmu"; 981 reg = <0x13EB0000 0x1000>; 982 interrupt-parent = <&combiner>; 983 interrupts = <2 6>; 984 power-domains = <&pd_gsc>; 985 clock-names = "sysmmu", "master"; 986 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 987 #iommu-cells = <0>; 988 }; 989 990 sysmmu_fimd1: sysmmu@14640000 { 991 compatible = "samsung,exynos-sysmmu"; 992 reg = <0x14640000 0x1000>; 993 interrupt-parent = <&combiner>; 994 interrupts = <3 2>; 995 power-domains = <&pd_disp1>; 996 clock-names = "sysmmu", "master"; 997 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 998 #iommu-cells = <0>; 999 }; 1000 1001 sysmmu_tv: sysmmu@14650000 { 1002 compatible = "samsung,exynos-sysmmu"; 1003 reg = <0x14650000 0x1000>; 1004 interrupt-parent = <&combiner>; 1005 interrupts = <7 4>; 1006 power-domains = <&pd_disp1>; 1007 clock-names = "sysmmu", "master"; 1008 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1009 #iommu-cells = <0>; 1010 }; 1011 }; 1012 1013 thermal-zones { 1014 cpu_thermal: cpu-thermal { 1015 polling-delay-passive = <0>; 1016 polling-delay = <0>; 1017 thermal-sensors = <&tmu 0>; 1018 1019 cooling-maps { 1020 map0 { 1021 /* Corresponds to 800MHz at freq_table */ 1022 cooling-device = <&cpu0 9 9>; 1023 }; 1024 map1 { 1025 /* Corresponds to 200MHz at freq_table */ 1026 cooling-device = <&cpu0 15 15>; 1027 }; 1028 }; 1029 }; 1030 }; 1031}; 1032 1033&dp { 1034 power-domains = <&pd_disp1>; 1035 clocks = <&clock CLK_DP>; 1036 clock-names = "dp"; 1037 phys = <&dp_phy>; 1038 phy-names = "dp"; 1039}; 1040 1041&fimd { 1042 power-domains = <&pd_disp1>; 1043 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1044 clock-names = "sclk_fimd", "fimd"; 1045 iommus = <&sysmmu_fimd1>; 1046}; 1047 1048&g2d { 1049 iommus = <&sysmmu_g2d>; 1050 clocks = <&clock CLK_G2D>; 1051 clock-names = "fimg2d"; 1052 status = "okay"; 1053}; 1054 1055&i2c_0 { 1056 clocks = <&clock CLK_I2C0>; 1057 clock-names = "i2c"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&i2c0_bus>; 1060}; 1061 1062&i2c_1 { 1063 clocks = <&clock CLK_I2C1>; 1064 clock-names = "i2c"; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&i2c1_bus>; 1067}; 1068 1069&i2c_2 { 1070 clocks = <&clock CLK_I2C2>; 1071 clock-names = "i2c"; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&i2c2_bus>; 1074}; 1075 1076&i2c_3 { 1077 clocks = <&clock CLK_I2C3>; 1078 clock-names = "i2c"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&i2c3_bus>; 1081}; 1082 1083&prng { 1084 clocks = <&clock CLK_SSS>; 1085 clock-names = "secss"; 1086}; 1087 1088&pwm { 1089 clocks = <&clock CLK_PWM>; 1090 clock-names = "timers"; 1091}; 1092 1093&rtc { 1094 clocks = <&clock CLK_RTC>; 1095 clock-names = "rtc"; 1096 interrupt-parent = <&pmu_system_controller>; 1097 status = "disabled"; 1098}; 1099 1100&serial_0 { 1101 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1102 clock-names = "uart", "clk_uart_baud0"; 1103 dmas = <&pdma0 13>, <&pdma0 14>; 1104 dma-names = "rx", "tx"; 1105}; 1106 1107&serial_1 { 1108 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1109 clock-names = "uart", "clk_uart_baud0"; 1110 dmas = <&pdma1 15>, <&pdma1 16>; 1111 dma-names = "rx", "tx"; 1112}; 1113 1114&serial_2 { 1115 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1116 clock-names = "uart", "clk_uart_baud0"; 1117 dmas = <&pdma0 15>, <&pdma0 16>; 1118 dma-names = "rx", "tx"; 1119}; 1120 1121&serial_3 { 1122 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1123 clock-names = "uart", "clk_uart_baud0"; 1124 dmas = <&pdma1 17>, <&pdma1 18>; 1125 dma-names = "rx", "tx"; 1126}; 1127 1128&sss { 1129 clocks = <&clock CLK_SSS>; 1130 clock-names = "secss"; 1131}; 1132 1133&trng { 1134 clocks = <&clock CLK_SSS>; 1135 clock-names = "secss"; 1136}; 1137 1138#include "exynos5250-pinctrl.dtsi" 1139#include "exynos-syscon-restart.dtsi" 1140
