1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4.dtsi"
18
19#include "exynos4-cpu-thermal.dtsi"
20
21/ {
22	compatible = "samsung,exynos4412", "samsung,exynos4";
23
24	aliases {
25		pinctrl0 = &pinctrl_0;
26		pinctrl1 = &pinctrl_1;
27		pinctrl2 = &pinctrl_2;
28		pinctrl3 = &pinctrl_3;
29		fimc-lite0 = &fimc_lite_0;
30		fimc-lite1 = &fimc_lite_1;
31		mshc0 = &mshc_0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu0: cpu@a00 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a9";
41			reg = <0xA00>;
42			clocks = <&clock CLK_ARM_CLK>;
43			clock-names = "cpu";
44			operating-points-v2 = <&cpu0_opp_table>;
45			#cooling-cells = <2>; /* min followed by max */
46		};
47
48		cpu1: cpu@a01 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a9";
51			reg = <0xA01>;
52			clocks = <&clock CLK_ARM_CLK>;
53			clock-names = "cpu";
54			operating-points-v2 = <&cpu0_opp_table>;
55			#cooling-cells = <2>; /* min followed by max */
56		};
57
58		cpu2: cpu@a02 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a9";
61			reg = <0xA02>;
62			clocks = <&clock CLK_ARM_CLK>;
63			clock-names = "cpu";
64			operating-points-v2 = <&cpu0_opp_table>;
65			#cooling-cells = <2>; /* min followed by max */
66		};
67
68		cpu3: cpu@a03 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a9";
71			reg = <0xA03>;
72			clocks = <&clock CLK_ARM_CLK>;
73			clock-names = "cpu";
74			operating-points-v2 = <&cpu0_opp_table>;
75			#cooling-cells = <2>; /* min followed by max */
76		};
77	};
78
79	cpu0_opp_table: opp_table0 {
80		compatible = "operating-points-v2";
81		opp-shared;
82
83		opp-200000000 {
84			opp-hz = /bits/ 64 <200000000>;
85			opp-microvolt = <900000>;
86			clock-latency-ns = <200000>;
87		};
88		opp-300000000 {
89			opp-hz = /bits/ 64 <300000000>;
90			opp-microvolt = <900000>;
91			clock-latency-ns = <200000>;
92		};
93		opp-400000000 {
94			opp-hz = /bits/ 64 <400000000>;
95			opp-microvolt = <925000>;
96			clock-latency-ns = <200000>;
97		};
98		opp-500000000 {
99			opp-hz = /bits/ 64 <500000000>;
100			opp-microvolt = <950000>;
101			clock-latency-ns = <200000>;
102		};
103		opp-600000000 {
104			opp-hz = /bits/ 64 <600000000>;
105			opp-microvolt = <975000>;
106			clock-latency-ns = <200000>;
107		};
108		opp-700000000 {
109			opp-hz = /bits/ 64 <700000000>;
110			opp-microvolt = <987500>;
111			clock-latency-ns = <200000>;
112		};
113		opp-800000000 {
114			opp-hz = /bits/ 64 <800000000>;
115			opp-microvolt = <1000000>;
116			clock-latency-ns = <200000>;
117			opp-suspend;
118		};
119		opp-900000000 {
120			opp-hz = /bits/ 64 <900000000>;
121			opp-microvolt = <1037500>;
122			clock-latency-ns = <200000>;
123		};
124		opp-1000000000 {
125			opp-hz = /bits/ 64 <1000000000>;
126			opp-microvolt = <1087500>;
127			clock-latency-ns = <200000>;
128		};
129		opp-1100000000 {
130			opp-hz = /bits/ 64 <1100000000>;
131			opp-microvolt = <1137500>;
132			clock-latency-ns = <200000>;
133		};
134		opp-1200000000 {
135			opp-hz = /bits/ 64 <1200000000>;
136			opp-microvolt = <1187500>;
137			clock-latency-ns = <200000>;
138		};
139		opp-1300000000 {
140			opp-hz = /bits/ 64 <1300000000>;
141			opp-microvolt = <1250000>;
142			clock-latency-ns = <200000>;
143		};
144		opp-1400000000 {
145			opp-hz = /bits/ 64 <1400000000>;
146			opp-microvolt = <1287500>;
147			clock-latency-ns = <200000>;
148		};
149		cpu0_opp_1500: opp-1500000000 {
150			opp-hz = /bits/ 64 <1500000000>;
151			opp-microvolt = <1350000>;
152			clock-latency-ns = <200000>;
153			turbo-mode;
154		};
155	};
156
157
158	soc: soc {
159
160		pinctrl_0: pinctrl@11400000 {
161			compatible = "samsung,exynos4x12-pinctrl";
162			reg = <0x11400000 0x1000>;
163			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
164		};
165
166		pinctrl_1: pinctrl@11000000 {
167			compatible = "samsung,exynos4x12-pinctrl";
168			reg = <0x11000000 0x1000>;
169			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
170
171			wakup_eint: wakeup-interrupt-controller {
172				compatible = "samsung,exynos4210-wakeup-eint";
173				interrupt-parent = <&gic>;
174				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175			};
176		};
177
178		pinctrl_2: pinctrl@3860000 {
179			compatible = "samsung,exynos4x12-pinctrl";
180			reg = <0x03860000 0x1000>;
181			interrupt-parent = <&combiner>;
182			interrupts = <10 0>;
183		};
184
185		pinctrl_3: pinctrl@106e0000 {
186			compatible = "samsung,exynos4x12-pinctrl";
187			reg = <0x106E0000 0x1000>;
188			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
189		};
190
191		sysram@2020000 {
192			compatible = "mmio-sram";
193			reg = <0x02020000 0x40000>;
194			#address-cells = <1>;
195			#size-cells = <1>;
196			ranges = <0 0x02020000 0x40000>;
197
198			smp-sysram@0 {
199				compatible = "samsung,exynos4210-sysram";
200				reg = <0x0 0x1000>;
201			};
202
203			smp-sysram@2f000 {
204				compatible = "samsung,exynos4210-sysram-ns";
205				reg = <0x2f000 0x1000>;
206			};
207		};
208
209		pd_isp: isp-power-domain@10023ca0 {
210			compatible = "samsung,exynos4210-pd";
211			reg = <0x10023CA0 0x20>;
212			#power-domain-cells = <0>;
213			label = "ISP";
214		};
215
216		l2c: l2-cache-controller@10502000 {
217			compatible = "arm,pl310-cache";
218			reg = <0x10502000 0x1000>;
219			cache-unified;
220			cache-level = <2>;
221			arm,tag-latency = <2 2 1>;
222			arm,data-latency = <3 2 1>;
223			arm,double-linefill = <1>;
224			arm,double-linefill-incr = <0>;
225			arm,double-linefill-wrap = <1>;
226			arm,prefetch-drop = <1>;
227			arm,prefetch-offset = <7>;
228		};
229
230		clock: clock-controller@10030000 {
231			compatible = "samsung,exynos4412-clock";
232			reg = <0x10030000 0x18000>;
233			#clock-cells = <1>;
234		};
235
236		isp_clock: clock-controller@10048000 {
237			compatible = "samsung,exynos4412-isp-clock";
238			reg = <0x10048000 0x1000>;
239			#clock-cells = <1>;
240			power-domains = <&pd_isp>;
241			clocks = <&clock CLK_ACLK200>,
242				 <&clock CLK_ACLK400_MCUISP>;
243			clock-names = "aclk200", "aclk400_mcuisp";
244		};
245
246		mct@10050000 {
247			compatible = "samsung,exynos4412-mct";
248			reg = <0x10050000 0x800>;
249			interrupt-parent = <&mct_map>;
250			interrupts = <0>, <1>, <2>, <3>, <4>;
251			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
252			clock-names = "fin_pll", "mct";
253
254			mct_map: mct-map {
255				#interrupt-cells = <1>;
256				#address-cells = <0>;
257				#size-cells = <0>;
258				interrupt-map =
259					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
260					<1 &combiner 12 5>,
261					<2 &combiner 12 6>,
262					<3 &combiner 12 7>,
263					<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
264			};
265		};
266
267		watchdog: watchdog@10060000 {
268			compatible = "samsung,exynos5250-wdt";
269			reg = <0x10060000 0x100>;
270			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
271			clocks = <&clock CLK_WDT>;
272			clock-names = "watchdog";
273			samsung,syscon-phandle = <&pmu_system_controller>;
274		};
275
276		adc: adc@126c0000 {
277			compatible = "samsung,exynos4212-adc";
278			reg = <0x126C0000 0x100>;
279			interrupt-parent = <&combiner>;
280			interrupts = <10 3>;
281			clocks = <&clock CLK_TSADC>;
282			clock-names = "adc";
283			#io-channel-cells = <1>;
284			io-channel-ranges;
285			samsung,syscon-phandle = <&pmu_system_controller>;
286			status = "disabled";
287		};
288
289		g2d: g2d@10800000 {
290			compatible = "samsung,exynos4212-g2d";
291			reg = <0x10800000 0x1000>;
292			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
293			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
294			clock-names = "sclk_fimg2d", "fimg2d";
295			iommus = <&sysmmu_g2d>;
296		};
297
298		mshc_0: mmc@12550000 {
299			compatible = "samsung,exynos4412-dw-mshc";
300			reg = <0x12550000 0x1000>;
301			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
302			#address-cells = <1>;
303			#size-cells = <0>;
304			fifo-depth = <0x80>;
305			clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
306			clock-names = "biu", "ciu";
307			status = "disabled";
308		};
309
310		sysmmu_g2d: sysmmu@10a40000 {
311			compatible = "samsung,exynos-sysmmu";
312			reg = <0x10A40000 0x1000>;
313			interrupt-parent = <&combiner>;
314			interrupts = <4 7>;
315			clock-names = "sysmmu", "master";
316			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
317			#iommu-cells = <0>;
318		};
319
320		sysmmu_fimc_isp: sysmmu@12260000 {
321			compatible = "samsung,exynos-sysmmu";
322			reg = <0x12260000 0x1000>;
323			interrupt-parent = <&combiner>;
324			interrupts = <16 2>;
325			power-domains = <&pd_isp>;
326			clock-names = "sysmmu";
327			clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
328			#iommu-cells = <0>;
329		};
330
331		sysmmu_fimc_drc: sysmmu@12270000 {
332			compatible = "samsung,exynos-sysmmu";
333			reg = <0x12270000 0x1000>;
334			interrupt-parent = <&combiner>;
335			interrupts = <16 3>;
336			power-domains = <&pd_isp>;
337			clock-names = "sysmmu";
338			clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
339			#iommu-cells = <0>;
340		};
341
342		sysmmu_fimc_fd: sysmmu@122a0000 {
343			compatible = "samsung,exynos-sysmmu";
344			reg = <0x122A0000 0x1000>;
345			interrupt-parent = <&combiner>;
346			interrupts = <16 4>;
347			power-domains = <&pd_isp>;
348			clock-names = "sysmmu";
349			clocks = <&isp_clock CLK_ISP_SMMU_FD>;
350			#iommu-cells = <0>;
351		};
352
353		sysmmu_fimc_mcuctl: sysmmu@122b0000 {
354			compatible = "samsung,exynos-sysmmu";
355			reg = <0x122B0000 0x1000>;
356			interrupt-parent = <&combiner>;
357			interrupts = <16 5>;
358			power-domains = <&pd_isp>;
359			clock-names = "sysmmu";
360			clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
361			#iommu-cells = <0>;
362		};
363
364		sysmmu_fimc_lite0: sysmmu@123b0000 {
365			compatible = "samsung,exynos-sysmmu";
366			reg = <0x123B0000 0x1000>;
367			interrupt-parent = <&combiner>;
368			interrupts = <16 0>;
369			power-domains = <&pd_isp>;
370			clock-names = "sysmmu", "master";
371			clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
372				 <&isp_clock CLK_ISP_FIMC_LITE0>;
373			#iommu-cells = <0>;
374		};
375
376		sysmmu_fimc_lite1: sysmmu@123c0000 {
377			compatible = "samsung,exynos-sysmmu";
378			reg = <0x123C0000 0x1000>;
379			interrupt-parent = <&combiner>;
380			interrupts = <16 1>;
381			power-domains = <&pd_isp>;
382			clock-names = "sysmmu", "master";
383			clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
384				 <&isp_clock CLK_ISP_FIMC_LITE1>;
385			#iommu-cells = <0>;
386		};
387
388		bus_dmc: bus_dmc {
389			compatible = "samsung,exynos-bus";
390			clocks = <&clock CLK_DIV_DMC>;
391			clock-names = "bus";
392			operating-points-v2 = <&bus_dmc_opp_table>;
393			status = "disabled";
394		};
395
396		bus_acp: bus_acp {
397			compatible = "samsung,exynos-bus";
398			clocks = <&clock CLK_DIV_ACP>;
399			clock-names = "bus";
400			operating-points-v2 = <&bus_acp_opp_table>;
401			status = "disabled";
402		};
403
404		bus_c2c: bus_c2c {
405			compatible = "samsung,exynos-bus";
406			clocks = <&clock CLK_DIV_C2C>;
407			clock-names = "bus";
408			operating-points-v2 = <&bus_dmc_opp_table>;
409			status = "disabled";
410		};
411
412		bus_dmc_opp_table: opp_table1 {
413			compatible = "operating-points-v2";
414			opp-shared;
415
416			opp-100000000 {
417				opp-hz = /bits/ 64 <100000000>;
418				opp-microvolt = <900000>;
419			};
420			opp-134000000 {
421				opp-hz = /bits/ 64 <134000000>;
422				opp-microvolt = <900000>;
423			};
424			opp-160000000 {
425				opp-hz = /bits/ 64 <160000000>;
426				opp-microvolt = <900000>;
427			};
428			opp-267000000 {
429				opp-hz = /bits/ 64 <267000000>;
430				opp-microvolt = <950000>;
431			};
432			opp-400000000 {
433				opp-hz = /bits/ 64 <400000000>;
434				opp-microvolt = <1050000>;
435				opp-suspend;
436			};
437		};
438
439		bus_acp_opp_table: opp_table2 {
440			compatible = "operating-points-v2";
441			opp-shared;
442
443			opp-100000000 {
444				opp-hz = /bits/ 64 <100000000>;
445			};
446			opp-134000000 {
447				opp-hz = /bits/ 64 <134000000>;
448			};
449			opp-160000000 {
450				opp-hz = /bits/ 64 <160000000>;
451			};
452			opp-267000000 {
453				opp-hz = /bits/ 64 <267000000>;
454			};
455		};
456
457		bus_leftbus: bus_leftbus {
458			compatible = "samsung,exynos-bus";
459			clocks = <&clock CLK_DIV_GDL>;
460			clock-names = "bus";
461			operating-points-v2 = <&bus_leftbus_opp_table>;
462			status = "disabled";
463		};
464
465		bus_rightbus: bus_rightbus {
466			compatible = "samsung,exynos-bus";
467			clocks = <&clock CLK_DIV_GDR>;
468			clock-names = "bus";
469			operating-points-v2 = <&bus_leftbus_opp_table>;
470			status = "disabled";
471		};
472
473		bus_display: bus_display {
474			compatible = "samsung,exynos-bus";
475			clocks = <&clock CLK_ACLK160>;
476			clock-names = "bus";
477			operating-points-v2 = <&bus_display_opp_table>;
478			status = "disabled";
479		};
480
481		bus_fsys: bus_fsys {
482			compatible = "samsung,exynos-bus";
483			clocks = <&clock CLK_ACLK133>;
484			clock-names = "bus";
485			operating-points-v2 = <&bus_fsys_opp_table>;
486			status = "disabled";
487		};
488
489		bus_peri: bus_peri {
490			compatible = "samsung,exynos-bus";
491			clocks = <&clock CLK_ACLK100>;
492			clock-names = "bus";
493			operating-points-v2 = <&bus_peri_opp_table>;
494			status = "disabled";
495		};
496
497		bus_mfc: bus_mfc {
498			compatible = "samsung,exynos-bus";
499			clocks = <&clock CLK_SCLK_MFC>;
500			clock-names = "bus";
501			operating-points-v2 = <&bus_leftbus_opp_table>;
502			status = "disabled";
503		};
504
505		bus_leftbus_opp_table: opp_table3 {
506			compatible = "operating-points-v2";
507			opp-shared;
508
509			opp-100000000 {
510				opp-hz = /bits/ 64 <100000000>;
511				opp-microvolt = <900000>;
512			};
513			opp-134000000 {
514				opp-hz = /bits/ 64 <134000000>;
515				opp-microvolt = <925000>;
516			};
517			opp-160000000 {
518				opp-hz = /bits/ 64 <160000000>;
519				opp-microvolt = <950000>;
520			};
521			opp-200000000 {
522				opp-hz = /bits/ 64 <200000000>;
523				opp-microvolt = <1000000>;
524				opp-suspend;
525			};
526		};
527
528		bus_display_opp_table: opp_table4 {
529			compatible = "operating-points-v2";
530			opp-shared;
531
532			opp-160000000 {
533				opp-hz = /bits/ 64 <160000000>;
534			};
535			opp-200000000 {
536				opp-hz = /bits/ 64 <200000000>;
537			};
538		};
539
540		bus_fsys_opp_table: opp_table5 {
541			compatible = "operating-points-v2";
542			opp-shared;
543
544			opp-100000000 {
545				opp-hz = /bits/ 64 <100000000>;
546			};
547			opp-134000000 {
548				opp-hz = /bits/ 64 <134000000>;
549			};
550		};
551
552		bus_peri_opp_table: opp_table6 {
553			compatible = "operating-points-v2";
554			opp-shared;
555
556			opp-50000000 {
557				opp-hz = /bits/ 64 <50000000>;
558			};
559			opp-100000000 {
560				opp-hz = /bits/ 64 <100000000>;
561			};
562		};
563	};
564};
565
566&combiner {
567	samsung,combiner-nr = <20>;
568	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
569		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
570		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
571		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
572		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
573		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
574		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
575		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
576		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
577		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
578		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
579		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
580		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
581		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
582		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
583		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
584		     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
585		     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
586		     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
587		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
588};
589
590&camera {
591	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
592		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
593	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
594
595	/* fimc_[0-3] are configured outside, under phandles */
596	fimc_lite_0: fimc-lite@12390000 {
597		compatible = "samsung,exynos4212-fimc-lite";
598		reg = <0x12390000 0x1000>;
599		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
600		power-domains = <&pd_isp>;
601		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
602		clock-names = "flite";
603		iommus = <&sysmmu_fimc_lite0>;
604		status = "disabled";
605	};
606
607	fimc_lite_1: fimc-lite@123a0000 {
608		compatible = "samsung,exynos4212-fimc-lite";
609		reg = <0x123A0000 0x1000>;
610		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
611		power-domains = <&pd_isp>;
612		clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
613		clock-names = "flite";
614		iommus = <&sysmmu_fimc_lite1>;
615		status = "disabled";
616	};
617
618	fimc_is: fimc-is@12000000 {
619		compatible = "samsung,exynos4212-fimc-is";
620		reg = <0x12000000 0x260000>;
621		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
622			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
623		power-domains = <&pd_isp>;
624		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
625			 <&isp_clock CLK_ISP_FIMC_LITE1>,
626			 <&isp_clock CLK_ISP_PPMUISPX>,
627			 <&isp_clock CLK_ISP_PPMUISPMX>,
628			 <&isp_clock CLK_ISP_FIMC_ISP>,
629			 <&isp_clock CLK_ISP_FIMC_DRC>,
630			 <&isp_clock CLK_ISP_FIMC_FD>,
631			 <&isp_clock CLK_ISP_MCUISP>,
632			 <&isp_clock CLK_ISP_GICISP>,
633			 <&isp_clock CLK_ISP_MCUCTL_ISP>,
634			 <&isp_clock CLK_ISP_PWM_ISP>,
635			 <&isp_clock CLK_ISP_DIV_ISP0>,
636			 <&isp_clock CLK_ISP_DIV_ISP1>,
637			 <&isp_clock CLK_ISP_DIV_MCUISP0>,
638			 <&isp_clock CLK_ISP_DIV_MCUISP1>,
639			 <&clock CLK_MOUT_MPLL_USER_T>,
640			 <&clock CLK_ACLK200>,
641			 <&clock CLK_ACLK400_MCUISP>,
642			 <&clock CLK_DIV_ACLK200>,
643			 <&clock CLK_DIV_ACLK400_MCUISP>,
644			 <&clock CLK_UART_ISP_SCLK>;
645		clock-names = "lite0", "lite1", "ppmuispx",
646			      "ppmuispmx", "isp",
647			      "drc", "fd", "mcuisp",
648			      "gicisp", "mcuctl_isp", "pwm_isp",
649			      "ispdiv0", "ispdiv1", "mcuispdiv0",
650			      "mcuispdiv1", "mpll", "aclk200",
651			      "aclk400mcuisp", "div_aclk200",
652			      "div_aclk400mcuisp", "uart";
653		iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
654			 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
655		iommu-names = "isp", "drc", "fd", "mcuctl";
656		#address-cells = <1>;
657		#size-cells = <1>;
658		ranges;
659		status = "disabled";
660
661		pmu@10020000 {
662			reg = <0x10020000 0x3000>;
663		};
664
665		i2c1_isp: i2c-isp@12140000 {
666			compatible = "samsung,exynos4212-i2c-isp";
667			reg = <0x12140000 0x100>;
668			clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
669			clock-names = "i2c_isp";
670			#address-cells = <1>;
671			#size-cells = <0>;
672		};
673	};
674};
675
676&exynos_usbphy {
677	compatible = "samsung,exynos4x12-usb2-phy";
678	samsung,sysreg-phandle = <&sys_reg>;
679};
680
681&fimc_0 {
682	compatible = "samsung,exynos4212-fimc";
683	samsung,pix-limits = <4224 8192 1920 4224>;
684	samsung,mainscaler-ext;
685	samsung,isp-wb;
686	samsung,cam-if;
687};
688
689&fimc_1 {
690	compatible = "samsung,exynos4212-fimc";
691	samsung,pix-limits = <4224 8192 1920 4224>;
692	samsung,mainscaler-ext;
693	samsung,isp-wb;
694	samsung,cam-if;
695};
696
697&fimc_2 {
698	compatible = "samsung,exynos4212-fimc";
699	samsung,pix-limits = <4224 8192 1920 4224>;
700	samsung,mainscaler-ext;
701	samsung,isp-wb;
702	samsung,lcd-wb;
703	samsung,cam-if;
704};
705
706&fimc_3 {
707	compatible = "samsung,exynos4212-fimc";
708	samsung,pix-limits = <1920 8192 1366 1920>;
709	samsung,rotators = <0>;
710	samsung,mainscaler-ext;
711	samsung,isp-wb;
712	samsung,lcd-wb;
713};
714
715&gic {
716	cpu-offset = <0x4000>;
717};
718
719&gpu {
720	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
721		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
722		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
723		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
724		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
725		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
726		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
727		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
728		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
729		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
730		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
731	interrupt-names = "gp",
732			  "gpmmu",
733			  "pp0",
734			  "ppmmu0",
735			  "pp1",
736			  "ppmmu1",
737			  "pp2",
738			  "ppmmu2",
739			  "pp3",
740			  "ppmmu3",
741			  "pmu";
742	operating-points-v2 = <&gpu_opp_table>;
743
744	gpu_opp_table: opp_table {
745		compatible = "operating-points-v2";
746
747		opp-160000000 {
748			opp-hz = /bits/ 64 <160000000>;
749			opp-microvolt = <875000>;
750		};
751		opp-267000000 {
752			opp-hz = /bits/ 64 <267000000>;
753			opp-microvolt = <900000>;
754		};
755		opp-350000000 {
756			opp-hz = /bits/ 64 <350000000>;
757			opp-microvolt = <950000>;
758		};
759		opp-440000000 {
760			opp-hz = /bits/ 64 <440000000>;
761			opp-microvolt = <1025000>;
762		};
763	};
764};
765
766&hdmi {
767	compatible = "samsung,exynos4212-hdmi";
768};
769
770&jpeg_codec {
771	compatible = "samsung,exynos4212-jpeg";
772};
773
774&rotator {
775	compatible = "samsung,exynos4212-rotator";
776};
777
778&mixer {
779	compatible = "samsung,exynos4212-mixer";
780	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
781	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
782		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
783};
784
785&pmu {
786	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
787	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
788	status = "okay";
789};
790
791&pmu_system_controller {
792	compatible = "samsung,exynos4412-pmu", "syscon";
793	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
794			"clkout4", "clkout8", "clkout9";
795	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
796		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
797		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
798	#clock-cells = <1>;
799};
800
801&tmu {
802	compatible = "samsung,exynos4412-tmu";
803	interrupt-parent = <&combiner>;
804	interrupts = <2 4>;
805	reg = <0x100C0000 0x100>;
806	clocks = <&clock 383>;
807	clock-names = "tmu_apbif";
808	status = "disabled";
809};
810
811#include "exynos4412-pinctrl.dtsi"
812