1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos3250 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 9 * based board files can include this file and provide values for board specfic 10 * bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 14 * nodes can be added to this file. 15 */ 16 17#include "exynos4-cpu-thermal.dtsi" 18#include <dt-bindings/clock/exynos3250.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/interrupt-controller/irq.h> 21 22/ { 23 compatible = "samsung,exynos3250"; 24 interrupt-parent = <&gic>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 mshc2 = &mshc_2; 34 spi0 = &spi_0; 35 spi1 = &spi_1; 36 i2c0 = &i2c_0; 37 i2c1 = &i2c_1; 38 i2c2 = &i2c_2; 39 i2c3 = &i2c_3; 40 i2c4 = &i2c_4; 41 i2c5 = &i2c_5; 42 i2c6 = &i2c_6; 43 i2c7 = &i2c_7; 44 serial0 = &serial_0; 45 serial1 = &serial_1; 46 serial2 = &serial_2; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0>; 57 clock-frequency = <1000000000>; 58 clocks = <&cmu CLK_ARM_CLK>; 59 clock-names = "cpu"; 60 #cooling-cells = <2>; 61 62 operating-points = < 63 1000000 1150000 64 900000 1112500 65 800000 1075000 66 700000 1037500 67 600000 1000000 68 500000 962500 69 400000 925000 70 300000 887500 71 200000 850000 72 100000 850000 73 >; 74 }; 75 76 cpu1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <1>; 80 clock-frequency = <1000000000>; 81 clocks = <&cmu CLK_ARM_CLK>; 82 clock-names = "cpu"; 83 #cooling-cells = <2>; 84 85 operating-points = < 86 1000000 1150000 87 900000 1112500 88 800000 1075000 89 700000 1037500 90 600000 1000000 91 500000 962500 92 400000 925000 93 300000 887500 94 200000 850000 95 100000 850000 96 >; 97 }; 98 }; 99 100 fixed-rate-clocks { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 xusbxti: clock@0 { 105 compatible = "fixed-clock"; 106 reg = <0>; 107 clock-frequency = <0>; 108 #clock-cells = <0>; 109 clock-output-names = "xusbxti"; 110 }; 111 112 xxti: clock@1 { 113 compatible = "fixed-clock"; 114 reg = <1>; 115 clock-frequency = <0>; 116 #clock-cells = <0>; 117 clock-output-names = "xxti"; 118 }; 119 120 xtcxo: clock@2 { 121 compatible = "fixed-clock"; 122 reg = <2>; 123 clock-frequency = <0>; 124 #clock-cells = <0>; 125 clock-output-names = "xtcxo"; 126 }; 127 }; 128 129 pmu { 130 compatible = "arm,cortex-a7-pmu"; 131 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 133 }; 134 135 soc: soc { 136 compatible = "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 141 sysram@2020000 { 142 compatible = "mmio-sram"; 143 reg = <0x02020000 0x40000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0 0x02020000 0x40000>; 147 148 smp-sysram@0 { 149 compatible = "samsung,exynos4210-sysram"; 150 reg = <0x0 0x1000>; 151 }; 152 153 smp-sysram@3f000 { 154 compatible = "samsung,exynos4210-sysram-ns"; 155 reg = <0x3f000 0x1000>; 156 }; 157 }; 158 159 chipid@10000000 { 160 compatible = "samsung,exynos4210-chipid"; 161 reg = <0x10000000 0x100>; 162 }; 163 164 sys_reg: syscon@10010000 { 165 compatible = "samsung,exynos3-sysreg", "syscon"; 166 reg = <0x10010000 0x400>; 167 }; 168 169 pmu_system_controller: system-controller@10020000 { 170 compatible = "samsung,exynos3250-pmu", "syscon"; 171 reg = <0x10020000 0x4000>; 172 interrupt-controller; 173 #interrupt-cells = <3>; 174 interrupt-parent = <&gic>; 175 clock-names = "clkout8"; 176 clocks = <&cmu CLK_FIN_PLL>; 177 #clock-cells = <1>; 178 }; 179 180 mipi_phy: video-phy { 181 compatible = "samsung,s5pv210-mipi-video-phy"; 182 #phy-cells = <1>; 183 syscon = <&pmu_system_controller>; 184 }; 185 186 pd_cam: power-domain@10023c00 { 187 compatible = "samsung,exynos4210-pd"; 188 reg = <0x10023C00 0x20>; 189 #power-domain-cells = <0>; 190 label = "CAM"; 191 }; 192 193 pd_mfc: power-domain@10023c40 { 194 compatible = "samsung,exynos4210-pd"; 195 reg = <0x10023C40 0x20>; 196 #power-domain-cells = <0>; 197 label = "MFC"; 198 }; 199 200 pd_g3d: power-domain@10023c60 { 201 compatible = "samsung,exynos4210-pd"; 202 reg = <0x10023C60 0x20>; 203 #power-domain-cells = <0>; 204 label = "G3D"; 205 }; 206 207 pd_lcd0: power-domain@10023c80 { 208 compatible = "samsung,exynos4210-pd"; 209 reg = <0x10023C80 0x20>; 210 #power-domain-cells = <0>; 211 label = "LCD0"; 212 }; 213 214 pd_isp: power-domain@10023ca0 { 215 compatible = "samsung,exynos4210-pd"; 216 reg = <0x10023CA0 0x20>; 217 #power-domain-cells = <0>; 218 label = "ISP"; 219 }; 220 221 cmu: clock-controller@10030000 { 222 compatible = "samsung,exynos3250-cmu"; 223 reg = <0x10030000 0x20000>; 224 #clock-cells = <1>; 225 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 226 <&cmu CLK_MOUT_ACLK_266_SUB>; 227 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 228 <&cmu CLK_FIN_PLL>; 229 }; 230 231 cmu_dmc: clock-controller@105c0000 { 232 compatible = "samsung,exynos3250-cmu-dmc"; 233 reg = <0x105C0000 0x2000>; 234 #clock-cells = <1>; 235 }; 236 237 rtc: rtc@10070000 { 238 compatible = "samsung,s3c6410-rtc"; 239 reg = <0x10070000 0x100>; 240 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-parent = <&pmu_system_controller>; 243 status = "disabled"; 244 }; 245 246 tmu: tmu@100c0000 { 247 compatible = "samsung,exynos3250-tmu"; 248 reg = <0x100C0000 0x100>; 249 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&cmu CLK_TMU_APBIF>; 251 clock-names = "tmu_apbif"; 252 #thermal-sensor-cells = <0>; 253 status = "disabled"; 254 }; 255 256 gic: interrupt-controller@10481000 { 257 compatible = "arm,cortex-a15-gic"; 258 #interrupt-cells = <3>; 259 interrupt-controller; 260 reg = <0x10481000 0x1000>, 261 <0x10482000 0x2000>, 262 <0x10484000 0x2000>, 263 <0x10486000 0x2000>; 264 interrupts = <GIC_PPI 9 265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 266 }; 267 268 mct@10050000 { 269 compatible = "samsung,exynos4210-mct"; 270 reg = <0x10050000 0x800>; 271 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 280 clock-names = "fin_pll", "mct"; 281 }; 282 283 pinctrl_1: pinctrl@11000000 { 284 compatible = "samsung,exynos3250-pinctrl"; 285 reg = <0x11000000 0x1000>; 286 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 287 288 wakeup-interrupt-controller { 289 compatible = "samsung,exynos4210-wakeup-eint"; 290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 291 }; 292 }; 293 294 pinctrl_0: pinctrl@11400000 { 295 compatible = "samsung,exynos3250-pinctrl"; 296 reg = <0x11400000 0x1000>; 297 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 298 }; 299 300 jpeg: codec@11830000 { 301 compatible = "samsung,exynos3250-jpeg"; 302 reg = <0x11830000 0x1000>; 303 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 305 clock-names = "jpeg", "sclk"; 306 power-domains = <&pd_cam>; 307 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; 308 assigned-clock-rates = <0>, <150000000>; 309 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; 310 iommus = <&sysmmu_jpeg>; 311 status = "disabled"; 312 }; 313 314 sysmmu_jpeg: sysmmu@11a60000 { 315 compatible = "samsung,exynos-sysmmu"; 316 reg = <0x11a60000 0x1000>; 317 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 319 clock-names = "sysmmu", "master"; 320 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 321 power-domains = <&pd_cam>; 322 #iommu-cells = <0>; 323 }; 324 325 fimd: fimd@11c00000 { 326 compatible = "samsung,exynos3250-fimd"; 327 reg = <0x11c00000 0x30000>; 328 interrupt-names = "fifo", "vsync", "lcd_sys"; 329 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 333 clock-names = "sclk_fimd", "fimd"; 334 power-domains = <&pd_lcd0>; 335 iommus = <&sysmmu_fimd0>; 336 samsung,sysreg = <&sys_reg>; 337 status = "disabled"; 338 }; 339 340 dsi_0: dsi@11c80000 { 341 compatible = "samsung,exynos3250-mipi-dsi"; 342 reg = <0x11C80000 0x10000>; 343 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 344 samsung,phy-type = <0>; 345 power-domains = <&pd_lcd0>; 346 phys = <&mipi_phy 1>; 347 phy-names = "dsim"; 348 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 349 clock-names = "bus_clk", "pll_clk"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 355 sysmmu_fimd0: sysmmu@11e20000 { 356 compatible = "samsung,exynos-sysmmu"; 357 reg = <0x11e20000 0x1000>; 358 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 360 clock-names = "sysmmu", "master"; 361 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 362 power-domains = <&pd_lcd0>; 363 #iommu-cells = <0>; 364 }; 365 366 hsotg: hsotg@12480000 { 367 compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; 368 reg = <0x12480000 0x20000>; 369 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cmu CLK_USBOTG>; 371 clock-names = "otg"; 372 phys = <&exynos_usbphy 0>; 373 phy-names = "usb2-phy"; 374 status = "disabled"; 375 }; 376 377 mshc_0: mshc@12510000 { 378 compatible = "samsung,exynos5420-dw-mshc"; 379 reg = <0x12510000 0x1000>; 380 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 382 clock-names = "biu", "ciu"; 383 fifo-depth = <0x80>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 mshc_1: mshc@12520000 { 390 compatible = "samsung,exynos5420-dw-mshc"; 391 reg = <0x12520000 0x1000>; 392 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 394 clock-names = "biu", "ciu"; 395 fifo-depth = <0x80>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 401 mshc_2: mshc@12530000 { 402 compatible = "samsung,exynos5250-dw-mshc"; 403 reg = <0x12530000 0x1000>; 404 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 406 clock-names = "biu", "ciu"; 407 fifo-depth = <0x80>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 exynos_usbphy: exynos-usbphy@125b0000 { 414 compatible = "samsung,exynos3250-usb2-phy"; 415 reg = <0x125B0000 0x100>; 416 samsung,pmureg-phandle = <&pmu_system_controller>; 417 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 418 clock-names = "phy", "ref"; 419 #phy-cells = <1>; 420 status = "disabled"; 421 }; 422 423 amba { 424 compatible = "simple-bus"; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges; 428 429 pdma0: pdma@12680000 { 430 compatible = "arm,pl330", "arm,primecell"; 431 reg = <0x12680000 0x1000>; 432 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cmu CLK_PDMA0>; 434 clock-names = "apb_pclk"; 435 #dma-cells = <1>; 436 #dma-channels = <8>; 437 #dma-requests = <32>; 438 }; 439 440 pdma1: pdma@12690000 { 441 compatible = "arm,pl330", "arm,primecell"; 442 reg = <0x12690000 0x1000>; 443 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cmu CLK_PDMA1>; 445 clock-names = "apb_pclk"; 446 #dma-cells = <1>; 447 #dma-channels = <8>; 448 #dma-requests = <32>; 449 }; 450 }; 451 452 adc: adc@126c0000 { 453 compatible = "samsung,exynos3250-adc"; 454 reg = <0x126C0000 0x100>; 455 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 456 clock-names = "adc", "sclk"; 457 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 458 #io-channel-cells = <1>; 459 io-channel-ranges; 460 samsung,syscon-phandle = <&pmu_system_controller>; 461 status = "disabled"; 462 }; 463 464 gpu: gpu@13000000 { 465 compatible = "samsung,exynos4210-mali", "arm,mali-400"; 466 reg = <0x13000000 0x10000>; 467 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 478 interrupt-names = "gp", 479 "gpmmu", 480 "pp0", 481 "ppmmu0", 482 "pp1", 483 "ppmmu1", 484 "pp2", 485 "ppmmu2", 486 "pp3", 487 "ppmmu3", 488 "pmu"; 489 clocks = <&cmu CLK_G3D>, 490 <&cmu CLK_SCLK_G3D>; 491 clock-names = "bus", "core"; 492 power-domains = <&pd_g3d>; 493 status = "disabled"; 494 /* TODO: operating points for DVFS, assigned clock as 134 MHz */ 495 }; 496 497 mfc: codec@13400000 { 498 compatible = "samsung,mfc-v7"; 499 reg = <0x13400000 0x10000>; 500 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 501 clock-names = "mfc", "sclk_mfc"; 502 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 503 power-domains = <&pd_mfc>; 504 iommus = <&sysmmu_mfc>; 505 }; 506 507 sysmmu_mfc: sysmmu@13620000 { 508 compatible = "samsung,exynos-sysmmu"; 509 reg = <0x13620000 0x1000>; 510 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 512 clock-names = "sysmmu", "master"; 513 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 514 power-domains = <&pd_mfc>; 515 #iommu-cells = <0>; 516 }; 517 518 serial_0: serial@13800000 { 519 compatible = "samsung,exynos4210-uart"; 520 reg = <0x13800000 0x100>; 521 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 523 clock-names = "uart", "clk_uart_baud0"; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&uart0_data &uart0_fctl>; 526 status = "disabled"; 527 }; 528 529 serial_1: serial@13810000 { 530 compatible = "samsung,exynos4210-uart"; 531 reg = <0x13810000 0x100>; 532 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 534 clock-names = "uart", "clk_uart_baud0"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&uart1_data>; 537 status = "disabled"; 538 }; 539 540 serial_2: serial@13820000 { 541 compatible = "samsung,exynos4210-uart"; 542 reg = <0x13820000 0x100>; 543 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 545 clock-names = "uart", "clk_uart_baud0"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&uart2_data>; 548 status = "disabled"; 549 }; 550 551 i2c_0: i2c@13860000 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "samsung,s3c2440-i2c"; 555 reg = <0x13860000 0x100>; 556 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cmu CLK_I2C0>; 558 clock-names = "i2c"; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c0_bus>; 561 status = "disabled"; 562 }; 563 564 i2c_1: i2c@13870000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "samsung,s3c2440-i2c"; 568 reg = <0x13870000 0x100>; 569 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cmu CLK_I2C1>; 571 clock-names = "i2c"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c1_bus>; 574 status = "disabled"; 575 }; 576 577 i2c_2: i2c@13880000 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 compatible = "samsung,s3c2440-i2c"; 581 reg = <0x13880000 0x100>; 582 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cmu CLK_I2C2>; 584 clock-names = "i2c"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2c2_bus>; 587 status = "disabled"; 588 }; 589 590 i2c_3: i2c@13890000 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 compatible = "samsung,s3c2440-i2c"; 594 reg = <0x13890000 0x100>; 595 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cmu CLK_I2C3>; 597 clock-names = "i2c"; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&i2c3_bus>; 600 status = "disabled"; 601 }; 602 603 i2c_4: i2c@138a0000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "samsung,s3c2440-i2c"; 607 reg = <0x138A0000 0x100>; 608 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cmu CLK_I2C4>; 610 clock-names = "i2c"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&i2c4_bus>; 613 status = "disabled"; 614 }; 615 616 i2c_5: i2c@138b0000 { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 compatible = "samsung,s3c2440-i2c"; 620 reg = <0x138B0000 0x100>; 621 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cmu CLK_I2C5>; 623 clock-names = "i2c"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&i2c5_bus>; 626 status = "disabled"; 627 }; 628 629 i2c_6: i2c@138c0000 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 compatible = "samsung,s3c2440-i2c"; 633 reg = <0x138C0000 0x100>; 634 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cmu CLK_I2C6>; 636 clock-names = "i2c"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&i2c6_bus>; 639 status = "disabled"; 640 }; 641 642 i2c_7: i2c@138d0000 { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 compatible = "samsung,s3c2440-i2c"; 646 reg = <0x138D0000 0x100>; 647 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cmu CLK_I2C7>; 649 clock-names = "i2c"; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&i2c7_bus>; 652 status = "disabled"; 653 }; 654 655 spi_0: spi@13920000 { 656 compatible = "samsung,exynos4210-spi"; 657 reg = <0x13920000 0x100>; 658 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 659 dmas = <&pdma0 7>, <&pdma0 6>; 660 dma-names = "tx", "rx"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 664 clock-names = "spi", "spi_busclk0"; 665 samsung,spi-src-clk = <0>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&spi0_bus>; 668 status = "disabled"; 669 }; 670 671 spi_1: spi@13930000 { 672 compatible = "samsung,exynos4210-spi"; 673 reg = <0x13930000 0x100>; 674 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 675 dmas = <&pdma1 7>, <&pdma1 6>; 676 dma-names = "tx", "rx"; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 680 clock-names = "spi", "spi_busclk0"; 681 samsung,spi-src-clk = <0>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&spi1_bus>; 684 status = "disabled"; 685 }; 686 687 i2s2: i2s@13970000 { 688 compatible = "samsung,s3c6410-i2s"; 689 reg = <0x13970000 0x100>; 690 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 692 clock-names = "iis", "i2s_opclk0"; 693 dmas = <&pdma0 14>, <&pdma0 13>; 694 dma-names = "tx", "rx"; 695 pinctrl-0 = <&i2s2_bus>; 696 pinctrl-names = "default"; 697 status = "disabled"; 698 }; 699 700 pwm: pwm@139d0000 { 701 compatible = "samsung,exynos4210-pwm"; 702 reg = <0x139D0000 0x1000>; 703 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 708 #pwm-cells = <3>; 709 status = "disabled"; 710 }; 711 712 ppmu_dmc0: ppmu_dmc0@106a0000 { 713 compatible = "samsung,exynos-ppmu"; 714 reg = <0x106a0000 0x2000>; 715 status = "disabled"; 716 }; 717 718 ppmu_dmc1: ppmu_dmc1@106b0000 { 719 compatible = "samsung,exynos-ppmu"; 720 reg = <0x106b0000 0x2000>; 721 status = "disabled"; 722 }; 723 724 ppmu_cpu: ppmu_cpu@106c0000 { 725 compatible = "samsung,exynos-ppmu"; 726 reg = <0x106c0000 0x2000>; 727 status = "disabled"; 728 }; 729 730 ppmu_rightbus: ppmu_rightbus@112a0000 { 731 compatible = "samsung,exynos-ppmu"; 732 reg = <0x112a0000 0x2000>; 733 clocks = <&cmu CLK_PPMURIGHT>; 734 clock-names = "ppmu"; 735 status = "disabled"; 736 }; 737 738 ppmu_leftbus: ppmu_leftbus0@116a0000 { 739 compatible = "samsung,exynos-ppmu"; 740 reg = <0x116a0000 0x2000>; 741 clocks = <&cmu CLK_PPMULEFT>; 742 clock-names = "ppmu"; 743 status = "disabled"; 744 }; 745 746 ppmu_camif: ppmu_camif@11ac0000 { 747 compatible = "samsung,exynos-ppmu"; 748 reg = <0x11ac0000 0x2000>; 749 clocks = <&cmu CLK_PPMUCAMIF>; 750 clock-names = "ppmu"; 751 status = "disabled"; 752 }; 753 754 ppmu_lcd0: ppmu_lcd0@11e40000 { 755 compatible = "samsung,exynos-ppmu"; 756 reg = <0x11e40000 0x2000>; 757 clocks = <&cmu CLK_PPMULCD0>; 758 clock-names = "ppmu"; 759 status = "disabled"; 760 }; 761 762 ppmu_fsys: ppmu_fsys@12630000 { 763 compatible = "samsung,exynos-ppmu"; 764 reg = <0x12630000 0x2000>; 765 clocks = <&cmu CLK_PPMUFILE>; 766 clock-names = "ppmu"; 767 status = "disabled"; 768 }; 769 770 ppmu_g3d: ppmu_g3d@13220000 { 771 compatible = "samsung,exynos-ppmu"; 772 reg = <0x13220000 0x2000>; 773 clocks = <&cmu CLK_PPMUG3D>; 774 clock-names = "ppmu"; 775 status = "disabled"; 776 }; 777 778 ppmu_mfc: ppmu_mfc@13660000 { 779 compatible = "samsung,exynos-ppmu"; 780 reg = <0x13660000 0x2000>; 781 clocks = <&cmu CLK_PPMUMFC_L>; 782 clock-names = "ppmu"; 783 status = "disabled"; 784 }; 785 786 bus_dmc: bus_dmc { 787 compatible = "samsung,exynos-bus"; 788 clocks = <&cmu_dmc CLK_DIV_DMC>; 789 clock-names = "bus"; 790 operating-points-v2 = <&bus_dmc_opp_table>; 791 status = "disabled"; 792 }; 793 794 bus_dmc_opp_table: opp_table1 { 795 compatible = "operating-points-v2"; 796 opp-shared; 797 798 opp-50000000 { 799 opp-hz = /bits/ 64 <50000000>; 800 opp-microvolt = <800000>; 801 }; 802 opp-100000000 { 803 opp-hz = /bits/ 64 <100000000>; 804 opp-microvolt = <800000>; 805 }; 806 opp-134000000 { 807 opp-hz = /bits/ 64 <134000000>; 808 opp-microvolt = <800000>; 809 }; 810 opp-200000000 { 811 opp-hz = /bits/ 64 <200000000>; 812 opp-microvolt = <825000>; 813 }; 814 opp-400000000 { 815 opp-hz = /bits/ 64 <400000000>; 816 opp-microvolt = <875000>; 817 }; 818 }; 819 820 bus_leftbus: bus_leftbus { 821 compatible = "samsung,exynos-bus"; 822 clocks = <&cmu CLK_DIV_GDL>; 823 clock-names = "bus"; 824 operating-points-v2 = <&bus_leftbus_opp_table>; 825 status = "disabled"; 826 }; 827 828 bus_rightbus: bus_rightbus { 829 compatible = "samsung,exynos-bus"; 830 clocks = <&cmu CLK_DIV_GDR>; 831 clock-names = "bus"; 832 operating-points-v2 = <&bus_leftbus_opp_table>; 833 status = "disabled"; 834 }; 835 836 bus_lcd0: bus_lcd0 { 837 compatible = "samsung,exynos-bus"; 838 clocks = <&cmu CLK_DIV_ACLK_160>; 839 clock-names = "bus"; 840 operating-points-v2 = <&bus_leftbus_opp_table>; 841 status = "disabled"; 842 }; 843 844 bus_fsys: bus_fsys { 845 compatible = "samsung,exynos-bus"; 846 clocks = <&cmu CLK_DIV_ACLK_200>; 847 clock-names = "bus"; 848 operating-points-v2 = <&bus_leftbus_opp_table>; 849 status = "disabled"; 850 }; 851 852 bus_mcuisp: bus_mcuisp { 853 compatible = "samsung,exynos-bus"; 854 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; 855 clock-names = "bus"; 856 operating-points-v2 = <&bus_mcuisp_opp_table>; 857 status = "disabled"; 858 }; 859 860 bus_isp: bus_isp { 861 compatible = "samsung,exynos-bus"; 862 clocks = <&cmu CLK_DIV_ACLK_266>; 863 clock-names = "bus"; 864 operating-points-v2 = <&bus_isp_opp_table>; 865 status = "disabled"; 866 }; 867 868 bus_peril: bus_peril { 869 compatible = "samsung,exynos-bus"; 870 clocks = <&cmu CLK_DIV_ACLK_100>; 871 clock-names = "bus"; 872 operating-points-v2 = <&bus_peril_opp_table>; 873 status = "disabled"; 874 }; 875 876 bus_mfc: bus_mfc { 877 compatible = "samsung,exynos-bus"; 878 clocks = <&cmu CLK_SCLK_MFC>; 879 clock-names = "bus"; 880 operating-points-v2 = <&bus_leftbus_opp_table>; 881 status = "disabled"; 882 }; 883 884 bus_leftbus_opp_table: opp_table2 { 885 compatible = "operating-points-v2"; 886 opp-shared; 887 888 opp-50000000 { 889 opp-hz = /bits/ 64 <50000000>; 890 opp-microvolt = <900000>; 891 }; 892 opp-80000000 { 893 opp-hz = /bits/ 64 <80000000>; 894 opp-microvolt = <900000>; 895 }; 896 opp-100000000 { 897 opp-hz = /bits/ 64 <100000000>; 898 opp-microvolt = <1000000>; 899 }; 900 opp-134000000 { 901 opp-hz = /bits/ 64 <134000000>; 902 opp-microvolt = <1000000>; 903 }; 904 opp-200000000 { 905 opp-hz = /bits/ 64 <200000000>; 906 opp-microvolt = <1000000>; 907 }; 908 }; 909 910 bus_mcuisp_opp_table: opp_table3 { 911 compatible = "operating-points-v2"; 912 opp-shared; 913 914 opp-50000000 { 915 opp-hz = /bits/ 64 <50000000>; 916 }; 917 opp-80000000 { 918 opp-hz = /bits/ 64 <80000000>; 919 }; 920 opp-100000000 { 921 opp-hz = /bits/ 64 <100000000>; 922 }; 923 opp-200000000 { 924 opp-hz = /bits/ 64 <200000000>; 925 }; 926 opp-400000000 { 927 opp-hz = /bits/ 64 <400000000>; 928 }; 929 }; 930 931 bus_isp_opp_table: opp_table4 { 932 compatible = "operating-points-v2"; 933 opp-shared; 934 935 opp-50000000 { 936 opp-hz = /bits/ 64 <50000000>; 937 }; 938 opp-80000000 { 939 opp-hz = /bits/ 64 <80000000>; 940 }; 941 opp-100000000 { 942 opp-hz = /bits/ 64 <100000000>; 943 }; 944 opp-200000000 { 945 opp-hz = /bits/ 64 <200000000>; 946 }; 947 opp-300000000 { 948 opp-hz = /bits/ 64 <300000000>; 949 }; 950 }; 951 952 bus_peril_opp_table: opp_table5 { 953 compatible = "operating-points-v2"; 954 opp-shared; 955 956 opp-50000000 { 957 opp-hz = /bits/ 64 <50000000>; 958 }; 959 opp-80000000 { 960 opp-hz = /bits/ 64 <80000000>; 961 }; 962 opp-100000000 { 963 opp-hz = /bits/ 64 <100000000>; 964 }; 965 }; 966 }; 967}; 968 969#include "exynos3250-pinctrl.dtsi" 970#include "exynos-syscon-restart.dtsi" 971
