1synopsys DWC3 CORE 2 3DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 4 as described in 'usb/generic.txt' 5 6Required properties: 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: should contain "ref", "bus_early", "suspend" 11 - clocks: list of phandle and clock specifier pairs corresponding to 12 entries in the clock-names property. 13 14Exception for clocks: 15 clocks are optional if the parent node (i.e. glue-layer) is compatible to 16 one of the following: 17 "amlogic,meson-axg-dwc3" 18 "amlogic,meson-gxl-dwc3" 19 "cavium,octeon-7130-usb-uctl" 20 "qcom,dwc3" 21 "samsung,exynos5250-dwusb3" 22 "samsung,exynos5433-dwusb3" 23 "samsung,exynos7-dwusb3" 24 "sprd,sc9860-dwc3" 25 "st,stih407-dwc3" 26 "ti,am437x-dwc3" 27 "ti,dwc3" 28 "ti,keystone-dwc3" 29 "rockchip,rk3399-dwc3" 30 "xlnx,zynqmp-dwc3" 31 32Optional properties: 33 - usb-phy : array of phandle for the PHY device. The first element 34 in the array is expected to be a handle to the USB2/HS PHY and 35 the second element is expected to be a handle to the USB3/SS PHY 36 - phys: from the *Generic PHY* bindings 37 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" 38 or "usb3-phy". 39 - resets: a single pair of phandle and reset specifier 40 - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM 41 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable 42 - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command 43 failure SW work-around for DWC_usb31 version 1.70a-ea06 44 and prior. 45 - snps,disable_scramble_quirk: true when SW should disable data scrambling. 46 Only really useful for FPGA builds. 47 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled 48 - snps,lpm-nyet-threshold: LPM NYET threshold 49 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk 50 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 51 - snps,req_p1p2p3_quirk: when set, the core will always request for 52 P1/P2/P3 transition sequence. 53 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain 54 amount of 8B10B errors occur. 55 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change 56 from P0 to P1/P2/P3. 57 - snps,lfps_filter_quirk: when set core will filter LFPS reception. 58 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start 59 Polling LFPS after RX.Detect. 60 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value. 61 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the 62 LTSSM during USB3 Compliance mode. 63 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy. 64 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy. 65 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG, 66 disabling the suspend signal to the PHY. 67 - snps,dis-u1-entry-quirk: set if link entering into U1 needs to be disabled. 68 - snps,dis-u2-entry-quirk: set if link entering into U2 needs to be disabled. 69 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection 70 in PHY P3 power state. 71 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists 72 in GUSB2PHYCFG, specify that USB2 PHY doesn't provide 73 a free-running PHY clock. 74 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power 75 from P0 to P1/P2/P3 without delay. 76 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check 77 during HS transmit. 78 - snps,dis_metastability_quirk: when set, disable metastability workaround. 79 CAUTION: use only if you are absolutely sure of it. 80 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal 81 utmi_l1_suspend_n, false when asserts utmi_sleep_n 82 - snps,hird-threshold: HIRD threshold 83 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for 84 UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. 85 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ 86 register for post-silicon frame length adjustment when the 87 fladj_30mhz_sdbnd signal is invalid or incorrect. 88 - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode 89 only. Set this and rx-max-burst-prd to a valid, 90 non-zero value 1-16 (DWC_usb31 programming guide 91 section 1.2.4) to enable periodic ESS RX threshold. 92 - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set 93 this and rx-thr-num-pkt-prd to a valid, non-zero value 94 1-16 (DWC_usb31 programming guide section 1.2.4) to 95 enable periodic ESS RX threshold. 96 - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode 97 only. Set this and tx-max-burst-prd to a valid, 98 non-zero value 1-16 (DWC_usb31 programming guide 99 section 1.2.3) to enable periodic ESS TX threshold. 100 - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set 101 this and tx-thr-num-pkt-prd to a valid, non-zero value 102 1-16 (DWC_usb31 programming guide section 1.2.3) to 103 enable periodic ESS TX threshold. 104 105 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. 106 - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 107 register, undefined length INCR burst type enable and INCRx type. 108 When just one value, which means INCRX burst mode enabled. When 109 more than one value, which means undefined length INCR burst type 110 enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. 111 112 - in addition all properties from usb-xhci.txt from the current directory are 113 supported as well 114 115 116This is usually a subnode to DWC3 glue to which it is connected. 117 118dwc3@4a030000 { 119 compatible = "snps,dwc3"; 120 reg = <0x4a030000 0xcfff>; 121 interrupts = <0 92 4> 122 usb-phy = <&usb2_phy>, <&usb3,phy>; 123 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 124}; 125
