1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * coh901327_wdt.c
4 *
5 * Copyright (C) 2008-2009 ST-Ericsson AB
6 * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 */
9 #include <linux/module.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/types.h>
12 #include <linux/watchdog.h>
13 #include <linux/interrupt.h>
14 #include <linux/pm.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/bitops.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21
22 #define DRV_NAME "WDOG COH 901 327"
23
24 /*
25 * COH 901 327 register definitions
26 */
27
28 /* WDOG_FEED Register 32bit (-/W) */
29 #define U300_WDOG_FR 0x00
30 #define U300_WDOG_FR_FEED_RESTART_TIMER 0xFEEDU
31 /* WDOG_TIMEOUT Register 32bit (R/W) */
32 #define U300_WDOG_TR 0x04
33 #define U300_WDOG_TR_TIMEOUT_MASK 0x7FFFU
34 /* WDOG_DISABLE1 Register 32bit (-/W) */
35 #define U300_WDOG_D1R 0x08
36 #define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER 0x2BADU
37 /* WDOG_DISABLE2 Register 32bit (R/W) */
38 #define U300_WDOG_D2R 0x0C
39 #define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER 0xCAFEU
40 #define U300_WDOG_D2R_DISABLE_STATUS_DISABLED 0xDABEU
41 #define U300_WDOG_D2R_DISABLE_STATUS_ENABLED 0x0000U
42 /* WDOG_STATUS Register 32bit (R/W) */
43 #define U300_WDOG_SR 0x10
44 #define U300_WDOG_SR_STATUS_TIMED_OUT 0xCFE8U
45 #define U300_WDOG_SR_STATUS_NORMAL 0x0000U
46 #define U300_WDOG_SR_RESET_STATUS_RESET 0xE8B4U
47 /* WDOG_COUNT Register 32bit (R/-) */
48 #define U300_WDOG_CR 0x14
49 #define U300_WDOG_CR_VALID_IND 0x8000U
50 #define U300_WDOG_CR_VALID_STABLE 0x0000U
51 #define U300_WDOG_CR_COUNT_VALUE_MASK 0x7FFFU
52 /* WDOG_JTAGOVR Register 32bit (R/W) */
53 #define U300_WDOG_JOR 0x18
54 #define U300_WDOG_JOR_JTAG_MODE_IND 0x0002U
55 #define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE 0x0001U
56 /* WDOG_RESTART Register 32bit (-/W) */
57 #define U300_WDOG_RR 0x1C
58 #define U300_WDOG_RR_RESTART_VALUE_RESUME 0xACEDU
59 /* WDOG_IRQ_EVENT Register 32bit (R/W) */
60 #define U300_WDOG_IER 0x20
61 #define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND 0x0001U
62 #define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE 0x0001U
63 /* WDOG_IRQ_MASK Register 32bit (R/W) */
64 #define U300_WDOG_IMR 0x24
65 #define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE 0x0001U
66 /* WDOG_IRQ_FORCE Register 32bit (R/W) */
67 #define U300_WDOG_IFR 0x28
68 #define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE 0x0001U
69
70 /* Default timeout in seconds = 1 minute */
71 #define U300_WDOG_DEFAULT_TIMEOUT 60
72
73 static unsigned int margin;
74 static int irq;
75 static void __iomem *virtbase;
76 static struct device *parent;
77
78 static struct clk *clk;
79
80 /*
81 * Enabling and disabling functions.
82 */
coh901327_enable(u16 timeout)83 static void coh901327_enable(u16 timeout)
84 {
85 u16 val;
86 unsigned long freq;
87 unsigned long delay_ns;
88
89 /* Restart timer if it is disabled */
90 val = readw(virtbase + U300_WDOG_D2R);
91 if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
92 writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
93 virtbase + U300_WDOG_RR);
94 /* Acknowledge any pending interrupt so it doesn't just fire off */
95 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
96 virtbase + U300_WDOG_IER);
97 /*
98 * The interrupt is cleared in the 32 kHz clock domain.
99 * Wait 3 32 kHz cycles for it to take effect
100 */
101 freq = clk_get_rate(clk);
102 delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
103 delay_ns = 3 * delay_ns; /* Wait 3 cycles */
104 ndelay(delay_ns);
105 /* Enable the watchdog interrupt */
106 writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
107 /* Activate the watchdog timer */
108 writew(timeout, virtbase + U300_WDOG_TR);
109 /* Start the watchdog timer */
110 writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
111 /*
112 * Extra read so that this change propagate in the watchdog.
113 */
114 (void) readw(virtbase + U300_WDOG_CR);
115 val = readw(virtbase + U300_WDOG_D2R);
116 if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
117 dev_err(parent,
118 "%s(): watchdog not enabled! D2R value %04x\n",
119 __func__, val);
120 }
121
coh901327_disable(void)122 static void coh901327_disable(void)
123 {
124 u16 val;
125
126 /* Disable the watchdog interrupt if it is active */
127 writew(0x0000U, virtbase + U300_WDOG_IMR);
128 /* If the watchdog is currently enabled, attempt to disable it */
129 val = readw(virtbase + U300_WDOG_D2R);
130 if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
131 writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
132 virtbase + U300_WDOG_D1R);
133 writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
134 virtbase + U300_WDOG_D2R);
135 /* Write this twice (else problems occur) */
136 writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
137 virtbase + U300_WDOG_D2R);
138 }
139 val = readw(virtbase + U300_WDOG_D2R);
140 if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
141 dev_err(parent,
142 "%s(): watchdog not disabled! D2R value %04x\n",
143 __func__, val);
144 }
145
coh901327_start(struct watchdog_device * wdt_dev)146 static int coh901327_start(struct watchdog_device *wdt_dev)
147 {
148 coh901327_enable(wdt_dev->timeout * 100);
149 return 0;
150 }
151
coh901327_stop(struct watchdog_device * wdt_dev)152 static int coh901327_stop(struct watchdog_device *wdt_dev)
153 {
154 coh901327_disable();
155 return 0;
156 }
157
coh901327_ping(struct watchdog_device * wdd)158 static int coh901327_ping(struct watchdog_device *wdd)
159 {
160 /* Feed the watchdog */
161 writew(U300_WDOG_FR_FEED_RESTART_TIMER,
162 virtbase + U300_WDOG_FR);
163 return 0;
164 }
165
coh901327_settimeout(struct watchdog_device * wdt_dev,unsigned int time)166 static int coh901327_settimeout(struct watchdog_device *wdt_dev,
167 unsigned int time)
168 {
169 wdt_dev->timeout = time;
170 /* Set new timeout value */
171 writew(time * 100, virtbase + U300_WDOG_TR);
172 /* Feed the dog */
173 writew(U300_WDOG_FR_FEED_RESTART_TIMER,
174 virtbase + U300_WDOG_FR);
175 return 0;
176 }
177
coh901327_gettimeleft(struct watchdog_device * wdt_dev)178 static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
179 {
180 u16 val;
181
182 /* Read repeatedly until the value is stable! */
183 val = readw(virtbase + U300_WDOG_CR);
184 while (val & U300_WDOG_CR_VALID_IND)
185 val = readw(virtbase + U300_WDOG_CR);
186 val &= U300_WDOG_CR_COUNT_VALUE_MASK;
187 if (val != 0)
188 val /= 100;
189
190 return val;
191 }
192
193 /*
194 * This interrupt occurs 10 ms before the watchdog WILL bark.
195 */
coh901327_interrupt(int irq,void * data)196 static irqreturn_t coh901327_interrupt(int irq, void *data)
197 {
198 u16 val;
199
200 /*
201 * Ack IRQ? If this occurs we're FUBAR anyway, so
202 * just acknowledge, disable the interrupt and await the imminent end.
203 * If you at some point need a host of callbacks to be called
204 * when the system is about to watchdog-reset, add them here!
205 *
206 * NOTE: on future versions of this IP-block, it will be possible
207 * to prevent a watchdog reset by feeding the watchdog at this
208 * point.
209 */
210 val = readw(virtbase + U300_WDOG_IER);
211 if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
212 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
213 virtbase + U300_WDOG_IER);
214 writew(0x0000U, virtbase + U300_WDOG_IMR);
215 dev_crit(parent, "watchdog is barking!\n");
216 return IRQ_HANDLED;
217 }
218
219 static const struct watchdog_info coh901327_ident = {
220 .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
221 .identity = DRV_NAME,
222 };
223
224 static const struct watchdog_ops coh901327_ops = {
225 .owner = THIS_MODULE,
226 .start = coh901327_start,
227 .stop = coh901327_stop,
228 .ping = coh901327_ping,
229 .set_timeout = coh901327_settimeout,
230 .get_timeleft = coh901327_gettimeleft,
231 };
232
233 static struct watchdog_device coh901327_wdt = {
234 .info = &coh901327_ident,
235 .ops = &coh901327_ops,
236 /*
237 * Max timeout is 327 since the 10ms
238 * timeout register is max
239 * 0x7FFF = 327670ms ~= 327s.
240 */
241 .min_timeout = 1,
242 .max_timeout = 327,
243 .timeout = U300_WDOG_DEFAULT_TIMEOUT,
244 };
245
coh901327_remove(struct platform_device * pdev)246 static int __exit coh901327_remove(struct platform_device *pdev)
247 {
248 watchdog_unregister_device(&coh901327_wdt);
249 coh901327_disable();
250 free_irq(irq, pdev);
251 clk_disable_unprepare(clk);
252 clk_put(clk);
253 return 0;
254 }
255
coh901327_probe(struct platform_device * pdev)256 static int __init coh901327_probe(struct platform_device *pdev)
257 {
258 struct device *dev = &pdev->dev;
259 int ret;
260 u16 val;
261 struct resource *res;
262
263 parent = dev;
264
265 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
266 virtbase = devm_ioremap_resource(dev, res);
267 if (IS_ERR(virtbase))
268 return PTR_ERR(virtbase);
269
270 clk = clk_get(dev, NULL);
271 if (IS_ERR(clk)) {
272 ret = PTR_ERR(clk);
273 dev_err(dev, "could not get clock\n");
274 return ret;
275 }
276 ret = clk_prepare_enable(clk);
277 if (ret) {
278 dev_err(dev, "could not prepare and enable clock\n");
279 goto out_no_clk_enable;
280 }
281
282 val = readw(virtbase + U300_WDOG_SR);
283 switch (val) {
284 case U300_WDOG_SR_STATUS_TIMED_OUT:
285 dev_info(dev, "watchdog timed out since last chip reset!\n");
286 coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
287 /* Status will be cleared below */
288 break;
289 case U300_WDOG_SR_STATUS_NORMAL:
290 dev_info(dev, "in normal status, no timeouts have occurred.\n");
291 break;
292 default:
293 dev_info(dev, "contains an illegal status code (%08x)\n", val);
294 break;
295 }
296
297 val = readw(virtbase + U300_WDOG_D2R);
298 switch (val) {
299 case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
300 dev_info(dev, "currently disabled.\n");
301 break;
302 case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
303 dev_info(dev, "currently enabled! (disabling it now)\n");
304 coh901327_disable();
305 break;
306 default:
307 dev_err(dev, "contains an illegal enable/disable code (%08x)\n",
308 val);
309 break;
310 }
311
312 /* Reset the watchdog */
313 writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
314
315 irq = platform_get_irq(pdev, 0);
316 if (request_irq(irq, coh901327_interrupt, 0,
317 DRV_NAME " Bark", pdev)) {
318 ret = -EIO;
319 goto out_no_irq;
320 }
321
322 watchdog_init_timeout(&coh901327_wdt, margin, dev);
323
324 coh901327_wdt.parent = dev;
325 ret = watchdog_register_device(&coh901327_wdt);
326 if (ret)
327 goto out_no_wdog;
328
329 dev_info(dev, "initialized. (timeout=%d sec)\n",
330 coh901327_wdt.timeout);
331 return 0;
332
333 out_no_wdog:
334 free_irq(irq, pdev);
335 out_no_irq:
336 clk_disable_unprepare(clk);
337 out_no_clk_enable:
338 clk_put(clk);
339 return ret;
340 }
341
342 #ifdef CONFIG_PM
343
344 static u16 wdogenablestore;
345 static u16 irqmaskstore;
346
coh901327_suspend(struct platform_device * pdev,pm_message_t state)347 static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
348 {
349 irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
350 wdogenablestore = readw(virtbase + U300_WDOG_D2R);
351 /* If watchdog is on, disable it here and now */
352 if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
353 coh901327_disable();
354 return 0;
355 }
356
coh901327_resume(struct platform_device * pdev)357 static int coh901327_resume(struct platform_device *pdev)
358 {
359 /* Restore the watchdog interrupt */
360 writew(irqmaskstore, virtbase + U300_WDOG_IMR);
361 if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
362 /* Restart the watchdog timer */
363 writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
364 virtbase + U300_WDOG_RR);
365 writew(U300_WDOG_FR_FEED_RESTART_TIMER,
366 virtbase + U300_WDOG_FR);
367 }
368 return 0;
369 }
370 #else
371 #define coh901327_suspend NULL
372 #define coh901327_resume NULL
373 #endif
374
375 /*
376 * Mistreating the watchdog is the only way to perform a software reset of the
377 * system on EMP platforms. So we implement this and export a symbol for it.
378 */
coh901327_watchdog_reset(void)379 void coh901327_watchdog_reset(void)
380 {
381 /* Enable even if on JTAG too */
382 writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
383 virtbase + U300_WDOG_JOR);
384 /*
385 * Timeout = 5s, we have to wait for the watchdog reset to
386 * actually take place: the watchdog will be reloaded with the
387 * default value immediately, so we HAVE to reboot and get back
388 * into the kernel in 30s, or the device will reboot again!
389 * The boot loader will typically deactivate the watchdog, so we
390 * need time enough for the boot loader to get to the point of
391 * deactivating the watchdog before it is shut down by it.
392 *
393 * NOTE: on future versions of the watchdog, this restriction is
394 * gone: the watchdog will be reloaded with a default value (1 min)
395 * instead of last value, and you can conveniently set the watchdog
396 * timeout to 10ms (value = 1) without any problems.
397 */
398 coh901327_enable(500);
399 /* Return and await doom */
400 }
401
402 static const struct of_device_id coh901327_dt_match[] = {
403 { .compatible = "stericsson,coh901327" },
404 {},
405 };
406
407 static struct platform_driver coh901327_driver = {
408 .driver = {
409 .name = "coh901327_wdog",
410 .of_match_table = coh901327_dt_match,
411 },
412 .remove = __exit_p(coh901327_remove),
413 .suspend = coh901327_suspend,
414 .resume = coh901327_resume,
415 };
416
417 module_platform_driver_probe(coh901327_driver, coh901327_probe);
418
419 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
420 MODULE_DESCRIPTION("COH 901 327 Watchdog");
421
422 module_param(margin, uint, 0);
423 MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
424
425 MODULE_LICENSE("GPL v2");
426 MODULE_ALIAS("platform:coh901327-watchdog");
427
