1 /* drivers/video/s1d13xxxfb.c
2 *
3 * (c) 2004 Simtec Electronics
4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
6 *
7 * Driver for Epson S1D13xxx series framebuffer chips
8 *
9 * Adapted from
10 * linux/drivers/video/skeletonfb.c
11 * linux/drivers/video/epson1355fb.c
12 * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
13 *
14 * TODO: - handle dual screen display (CRT and LCD at the same time).
15 * - check_var(), mode change, etc.
16 * - probably not SMP safe :)
17 * - support all bitblt operations on all cards
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive for
21 * more details.
22 */
23
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/mm.h>
30 #include <linux/mman.h>
31 #include <linux/fb.h>
32 #include <linux/spinlock_types.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/io.h>
36
37 #include <video/s1d13xxxfb.h>
38
39 #define PFX "s1d13xxxfb: "
40 #define BLIT "s1d13xxxfb_bitblt: "
41
42 /*
43 * set this to enable debugging on general functions
44 */
45 #if 0
46 #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
47 #else
48 #define dbg(fmt, args...) do { no_printk(KERN_INFO fmt, ## args); } while (0)
49 #endif
50
51 /*
52 * set this to enable debugging on 2D acceleration
53 */
54 #if 0
55 #define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
56 #else
57 #define dbg_blit(fmt, args...) do { } while (0)
58 #endif
59
60 /*
61 * we make sure only one bitblt operation is running
62 */
63 static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
64
65 /*
66 * list of card production ids
67 */
68 static const int s1d13xxxfb_prod_ids[] = {
69 S1D13505_PROD_ID,
70 S1D13506_PROD_ID,
71 S1D13806_PROD_ID,
72 };
73
74 /*
75 * List of card strings
76 */
77 static const char *s1d13xxxfb_prod_names[] = {
78 "S1D13505",
79 "S1D13506",
80 "S1D13806",
81 };
82
83 /*
84 * here we define the default struct fb_fix_screeninfo
85 */
86 static const struct fb_fix_screeninfo s1d13xxxfb_fix = {
87 .id = S1D_FBID,
88 .type = FB_TYPE_PACKED_PIXELS,
89 .visual = FB_VISUAL_PSEUDOCOLOR,
90 .xpanstep = 0,
91 .ypanstep = 1,
92 .ywrapstep = 0,
93 .accel = FB_ACCEL_NONE,
94 };
95
96 static inline u8
s1d13xxxfb_readreg(struct s1d13xxxfb_par * par,u16 regno)97 s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
98 {
99 return readb(par->regs + regno);
100 }
101
102 static inline void
s1d13xxxfb_writereg(struct s1d13xxxfb_par * par,u16 regno,u8 value)103 s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
104 {
105 writeb(value, par->regs + regno);
106 }
107
108 static inline void
s1d13xxxfb_runinit(struct s1d13xxxfb_par * par,const struct s1d13xxxfb_regval * initregs,const unsigned int size)109 s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
110 const struct s1d13xxxfb_regval *initregs,
111 const unsigned int size)
112 {
113 int i;
114
115 for (i = 0; i < size; i++) {
116 if ((initregs[i].addr == S1DREG_DELAYOFF) ||
117 (initregs[i].addr == S1DREG_DELAYON))
118 mdelay((int)initregs[i].value);
119 else {
120 s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
121 }
122 }
123
124 /* make sure the hardware can cope with us */
125 mdelay(1);
126 }
127
128 static inline void
lcd_enable(struct s1d13xxxfb_par * par,int enable)129 lcd_enable(struct s1d13xxxfb_par *par, int enable)
130 {
131 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
132
133 if (enable)
134 mode |= 0x01;
135 else
136 mode &= ~0x01;
137
138 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
139 }
140
141 static inline void
crt_enable(struct s1d13xxxfb_par * par,int enable)142 crt_enable(struct s1d13xxxfb_par *par, int enable)
143 {
144 u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
145
146 if (enable)
147 mode |= 0x02;
148 else
149 mode &= ~0x02;
150
151 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
152 }
153
154
155 /*************************************************************
156 framebuffer control functions
157 *************************************************************/
158 static inline void
s1d13xxxfb_setup_pseudocolour(struct fb_info * info)159 s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
160 {
161 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
162
163 info->var.red.length = 4;
164 info->var.green.length = 4;
165 info->var.blue.length = 4;
166 }
167
168 static inline void
s1d13xxxfb_setup_truecolour(struct fb_info * info)169 s1d13xxxfb_setup_truecolour(struct fb_info *info)
170 {
171 info->fix.visual = FB_VISUAL_TRUECOLOR;
172 info->var.bits_per_pixel = 16;
173
174 info->var.red.length = 5;
175 info->var.red.offset = 11;
176
177 info->var.green.length = 6;
178 info->var.green.offset = 5;
179
180 info->var.blue.length = 5;
181 info->var.blue.offset = 0;
182 }
183
184 /**
185 * s1d13xxxfb_set_par - Alters the hardware state.
186 * @info: frame buffer structure
187 *
188 * Using the fb_var_screeninfo in fb_info we set the depth of the
189 * framebuffer. This function alters the par AND the
190 * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
191 * fb_info since we are using that data. This means we depend on the
192 * data in var inside fb_info to be supported by the hardware.
193 * xxxfb_check_var is always called before xxxfb_set_par to ensure this.
194 *
195 * XXX TODO: write proper s1d13xxxfb_check_var(), without which that
196 * function is quite useless.
197 */
198 static int
s1d13xxxfb_set_par(struct fb_info * info)199 s1d13xxxfb_set_par(struct fb_info *info)
200 {
201 struct s1d13xxxfb_par *s1dfb = info->par;
202 unsigned int val;
203
204 dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
205
206 if ((s1dfb->display & 0x01)) /* LCD */
207 val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
208 else /* CRT */
209 val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
210
211 val &= ~0x07;
212
213 switch (info->var.bits_per_pixel) {
214 case 4:
215 dbg("pseudo colour 4\n");
216 s1d13xxxfb_setup_pseudocolour(info);
217 val |= 2;
218 break;
219 case 8:
220 dbg("pseudo colour 8\n");
221 s1d13xxxfb_setup_pseudocolour(info);
222 val |= 3;
223 break;
224 case 16:
225 dbg("true colour\n");
226 s1d13xxxfb_setup_truecolour(info);
227 val |= 5;
228 break;
229
230 default:
231 dbg("bpp not supported!\n");
232 return -EINVAL;
233 }
234
235 dbg("writing %02x to display mode register\n", val);
236
237 if ((s1dfb->display & 0x01)) /* LCD */
238 s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
239 else /* CRT */
240 s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
241
242 info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
243 info->fix.line_length /= 8;
244
245 dbg("setting line_length to %d\n", info->fix.line_length);
246
247 dbg("done setup\n");
248
249 return 0;
250 }
251
252 /**
253 * s1d13xxxfb_setcolreg - sets a color register.
254 * @regno: Which register in the CLUT we are programming
255 * @red: The red value which can be up to 16 bits wide
256 * @green: The green value which can be up to 16 bits wide
257 * @blue: The blue value which can be up to 16 bits wide.
258 * @transp: If supported the alpha value which can be up to 16 bits wide.
259 * @info: frame buffer info structure
260 *
261 * Returns negative errno on error, or zero on success.
262 */
263 static int
s1d13xxxfb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * info)264 s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
265 u_int transp, struct fb_info *info)
266 {
267 struct s1d13xxxfb_par *s1dfb = info->par;
268 unsigned int pseudo_val;
269
270 if (regno >= S1D_PALETTE_SIZE)
271 return -EINVAL;
272
273 dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
274 regno, red, green, blue, transp);
275
276 if (info->var.grayscale)
277 red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
278
279 switch (info->fix.visual) {
280 case FB_VISUAL_TRUECOLOR:
281 if (regno >= 16)
282 return -EINVAL;
283
284 /* deal with creating pseudo-palette entries */
285
286 pseudo_val = (red >> 11) << info->var.red.offset;
287 pseudo_val |= (green >> 10) << info->var.green.offset;
288 pseudo_val |= (blue >> 11) << info->var.blue.offset;
289
290 dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
291 regno, pseudo_val);
292
293 ((u32 *)info->pseudo_palette)[regno] = pseudo_val;
294
295 break;
296 case FB_VISUAL_PSEUDOCOLOR:
297 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
298 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
299 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
300 s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
301
302 break;
303 default:
304 return -ENOSYS;
305 }
306
307 dbg("s1d13xxxfb_setcolreg: done\n");
308
309 return 0;
310 }
311
312 /**
313 * s1d13xxxfb_blank - blanks the display.
314 * @blank_mode: the blank mode we want.
315 * @info: frame buffer structure that represents a single frame buffer
316 *
317 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
318 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
319 * video mode which doesn't support it. Implements VESA suspend
320 * and powerdown modes on hardware that supports disabling hsync/vsync:
321 * blank_mode == 2: suspend vsync
322 * blank_mode == 3: suspend hsync
323 * blank_mode == 4: powerdown
324 *
325 * Returns negative errno on error, or zero on success.
326 */
327 static int
s1d13xxxfb_blank(int blank_mode,struct fb_info * info)328 s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
329 {
330 struct s1d13xxxfb_par *par = info->par;
331
332 dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
333
334 switch (blank_mode) {
335 case FB_BLANK_UNBLANK:
336 case FB_BLANK_NORMAL:
337 if ((par->display & 0x01) != 0)
338 lcd_enable(par, 1);
339 if ((par->display & 0x02) != 0)
340 crt_enable(par, 1);
341 break;
342 case FB_BLANK_VSYNC_SUSPEND:
343 case FB_BLANK_HSYNC_SUSPEND:
344 break;
345 case FB_BLANK_POWERDOWN:
346 lcd_enable(par, 0);
347 crt_enable(par, 0);
348 break;
349 default:
350 return -EINVAL;
351 }
352
353 /* let fbcon do a soft blank for us */
354 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
355 }
356
357 /**
358 * s1d13xxxfb_pan_display - Pans the display.
359 * @var: frame buffer variable screen structure
360 * @info: frame buffer structure that represents a single frame buffer
361 *
362 * Pan (or wrap, depending on the `vmode' field) the display using the
363 * `yoffset' field of the `var' structure (`xoffset' not yet supported).
364 * If the values don't fit, return -EINVAL.
365 *
366 * Returns negative errno on error, or zero on success.
367 */
368 static int
s1d13xxxfb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)369 s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
370 {
371 struct s1d13xxxfb_par *par = info->par;
372 u32 start;
373
374 if (var->xoffset != 0) /* not yet ... */
375 return -EINVAL;
376
377 if (var->yoffset + info->var.yres > info->var.yres_virtual)
378 return -EINVAL;
379
380 start = (info->fix.line_length >> 1) * var->yoffset;
381
382 if ((par->display & 0x01)) {
383 /* LCD */
384 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
385 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
386 s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
387 } else {
388 /* CRT */
389 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
390 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
391 s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
392 }
393
394 return 0;
395 }
396
397 /************************************************************
398 functions to handle bitblt acceleration
399 ************************************************************/
400
401 /**
402 * bltbit_wait_bitclear - waits for change in register value
403 * @info : frambuffer structure
404 * @bit : value currently in register
405 * @timeout : ...
406 *
407 * waits until value changes FROM bit
408 *
409 */
410 static u8
bltbit_wait_bitclear(struct fb_info * info,u8 bit,int timeout)411 bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
412 {
413 while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
414 udelay(10);
415 if (!--timeout) {
416 dbg_blit("wait_bitclear timeout\n");
417 break;
418 }
419 }
420
421 return timeout;
422 }
423
424 /*
425 * s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
426 * @info : framebuffer structure
427 * @area : fb_copyarea structure
428 *
429 * supports (atleast) S1D13506
430 *
431 */
432 static void
s1d13xxxfb_bitblt_copyarea(struct fb_info * info,const struct fb_copyarea * area)433 s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
434 {
435 u32 dst, src;
436 u32 stride;
437 u16 reverse = 0;
438 u16 sx = area->sx, sy = area->sy;
439 u16 dx = area->dx, dy = area->dy;
440 u16 width = area->width, height = area->height;
441 u16 bpp;
442
443 spin_lock(&s1d13xxxfb_bitblt_lock);
444
445 /* bytes per xres line */
446 bpp = (info->var.bits_per_pixel >> 3);
447 stride = bpp * info->var.xres;
448
449 /* reverse, calculate the last pixel in rectangle */
450 if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
451 dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
452 src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
453 reverse = 1;
454 /* not reverse, calculate the first pixel in rectangle */
455 } else { /* (y * xres) + (bpp * x) */
456 dst = (dy * stride) + (bpp * dx);
457 src = (sy * stride) + (bpp * sx);
458 }
459
460 /* set source address */
461 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
462 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
463 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
464
465 /* set destination address */
466 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
467 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
468 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
469
470 /* program height and width */
471 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
472 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
473
474 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
475 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
476
477 /* negative direction ROP */
478 if (reverse == 1) {
479 dbg_blit("(copyarea) negative rop\n");
480 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
481 } else /* positive direction ROP */ {
482 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
483 dbg_blit("(copyarea) positive rop\n");
484 }
485
486 /* set for rectangel mode and not linear */
487 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
488
489 /* setup the bpp 1 = 16bpp, 0 = 8bpp*/
490 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
491
492 /* set words per xres */
493 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
494 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
495
496 dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
497 dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
498 dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
499 dbg_blit("(copyarea) stride=%d\n", stride);
500 dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
501 (stride >> 1) & 0xff, stride >> 9);
502
503 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
504
505 /* initialize the engine */
506 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
507
508 /* wait to complete */
509 bltbit_wait_bitclear(info, 0x80, 8000);
510
511 spin_unlock(&s1d13xxxfb_bitblt_lock);
512 }
513
514 /**
515 * s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
516 * @info : framebuffer structure
517 * @rect : fb_fillrect structure
518 *
519 * supports (atleast 13506)
520 *
521 **/
522 static void
s1d13xxxfb_bitblt_solidfill(struct fb_info * info,const struct fb_fillrect * rect)523 s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
524 {
525 u32 screen_stride, dest;
526 u32 fg;
527 u16 bpp = (info->var.bits_per_pixel >> 3);
528
529 /* grab spinlock */
530 spin_lock(&s1d13xxxfb_bitblt_lock);
531
532 /* bytes per x width */
533 screen_stride = (bpp * info->var.xres);
534
535 /* bytes to starting point */
536 dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
537
538 dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
539 "(solidfill) : rect_width=%d, rect_height=%d\n",
540 rect->dx, rect->dy, screen_stride, dest,
541 rect->width - 1, rect->height - 1);
542
543 dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
544 info->var.xres, info->var.yres,
545 info->var.bits_per_pixel);
546 dbg_blit("(solidfill) : rop=%d\n", rect->rop);
547
548 /* We split the destination into the three registers */
549 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
550 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
551 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
552
553 /* give information regarding rectangel width */
554 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
555 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
556
557 /* give information regarding rectangel height */
558 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
559 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
560
561 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
562 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
563 fg = ((u32 *)info->pseudo_palette)[rect->color];
564 dbg_blit("(solidfill) truecolor/directcolor\n");
565 dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
566 } else {
567 fg = rect->color;
568 dbg_blit("(solidfill) color = %d\n", rect->color);
569 }
570
571 /* set foreground color */
572 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
573 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
574
575 /* set rectangual region of memory (rectangle and not linear) */
576 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
577
578 /* set operation mode SOLID_FILL */
579 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
580
581 /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
582 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
583
584 /* set the memory offset for the bblt in word sizes */
585 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
586 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
587
588 /* and away we go.... */
589 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
590
591 /* wait until its done */
592 bltbit_wait_bitclear(info, 0x80, 8000);
593
594 /* let others play */
595 spin_unlock(&s1d13xxxfb_bitblt_lock);
596 }
597
598 /* framebuffer information structures */
599 static struct fb_ops s1d13xxxfb_fbops = {
600 .owner = THIS_MODULE,
601 .fb_set_par = s1d13xxxfb_set_par,
602 .fb_setcolreg = s1d13xxxfb_setcolreg,
603 .fb_blank = s1d13xxxfb_blank,
604
605 .fb_pan_display = s1d13xxxfb_pan_display,
606
607 /* gets replaced at chip detection time */
608 .fb_fillrect = cfb_fillrect,
609 .fb_copyarea = cfb_copyarea,
610 .fb_imageblit = cfb_imageblit,
611 };
612
613 static int s1d13xxxfb_width_tab[2][4] = {
614 {4, 8, 16, -1},
615 {9, 12, 18, -1},
616 };
617
618 /**
619 * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
620 * hardware setup.
621 * @info: frame buffer structure
622 *
623 * We setup the framebuffer structures according to the current
624 * hardware setup. On some machines, the BIOS will have filled
625 * the chip registers with such info, on others, these values will
626 * have been written in some init procedure. In any case, the
627 * software values needs to match the hardware ones. This is what
628 * this function ensures.
629 *
630 * Note: some of the hardcoded values here might need some love to
631 * work on various chips, and might need to no longer be hardcoded.
632 */
s1d13xxxfb_fetch_hw_state(struct fb_info * info)633 static void s1d13xxxfb_fetch_hw_state(struct fb_info *info)
634 {
635 struct fb_var_screeninfo *var = &info->var;
636 struct fb_fix_screeninfo *fix = &info->fix;
637 struct s1d13xxxfb_par *par = info->par;
638 u8 panel, display;
639 u16 offset;
640 u32 xres, yres;
641 u32 xres_virtual, yres_virtual;
642 int bpp, lcd_bpp;
643 int is_color, is_dual, is_tft;
644 int lcd_enabled, crt_enabled;
645
646 fix->type = FB_TYPE_PACKED_PIXELS;
647
648 /* general info */
649 par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
650 crt_enabled = (par->display & 0x02) != 0;
651 lcd_enabled = (par->display & 0x01) != 0;
652
653 if (lcd_enabled && crt_enabled)
654 printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
655
656 if (lcd_enabled)
657 display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
658 else /* CRT */
659 display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
660
661 bpp = display & 0x07;
662
663 switch (bpp) {
664 case 2: /* 4 bpp */
665 case 3: /* 8 bpp */
666 var->bits_per_pixel = 8;
667 var->red.offset = var->green.offset = var->blue.offset = 0;
668 var->red.length = var->green.length = var->blue.length = 8;
669 break;
670 case 5: /* 16 bpp */
671 s1d13xxxfb_setup_truecolour(info);
672 break;
673 default:
674 dbg("bpp: %i\n", bpp);
675 }
676 fb_alloc_cmap(&info->cmap, 256, 0);
677
678 /* LCD info */
679 panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
680 is_color = (panel & 0x04) != 0;
681 is_dual = (panel & 0x02) != 0;
682 is_tft = (panel & 0x01) != 0;
683 lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
684
685 if (lcd_enabled) {
686 xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
687 yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
688 ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
689
690 offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
691 ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
692 } else { /* crt */
693 xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
694 yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
695 ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
696
697 offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
698 ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
699 }
700 xres_virtual = offset * 16 / var->bits_per_pixel;
701 yres_virtual = fix->smem_len / (offset * 2);
702
703 var->xres = xres;
704 var->yres = yres;
705 var->xres_virtual = xres_virtual;
706 var->yres_virtual = yres_virtual;
707 var->xoffset = var->yoffset = 0;
708
709 fix->line_length = offset * 2;
710
711 var->grayscale = !is_color;
712
713 var->activate = FB_ACTIVATE_NOW;
714
715 dbg(PFX "bpp=%d, lcd_bpp=%d, "
716 "crt_enabled=%d, lcd_enabled=%d\n",
717 var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
718 dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
719 "is_color=%d, is_dual=%d, is_tft=%d\n",
720 xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
721 }
722
__s1d13xxxfb_remove(struct platform_device * pdev)723 static void __s1d13xxxfb_remove(struct platform_device *pdev)
724 {
725 struct fb_info *info = platform_get_drvdata(pdev);
726 struct s1d13xxxfb_par *par = NULL;
727
728 if (info) {
729 par = info->par;
730 if (par && par->regs) {
731 /* disable output & enable powersave */
732 s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
733 s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
734 iounmap(par->regs);
735 }
736
737 fb_dealloc_cmap(&info->cmap);
738
739 if (info->screen_base)
740 iounmap(info->screen_base);
741
742 framebuffer_release(info);
743 }
744
745 release_mem_region(pdev->resource[0].start,
746 resource_size(&pdev->resource[0]));
747 release_mem_region(pdev->resource[1].start,
748 resource_size(&pdev->resource[1]));
749 }
750
s1d13xxxfb_remove(struct platform_device * pdev)751 static void s1d13xxxfb_remove(struct platform_device *pdev)
752 {
753 struct fb_info *info = platform_get_drvdata(pdev);
754
755 unregister_framebuffer(info);
756 __s1d13xxxfb_remove(pdev);
757 }
758
s1d13xxxfb_probe(struct platform_device * pdev)759 static int s1d13xxxfb_probe(struct platform_device *pdev)
760 {
761 struct s1d13xxxfb_par *default_par;
762 struct fb_info *info;
763 struct s1d13xxxfb_pdata *pdata = NULL;
764 int ret = 0;
765 int i;
766 u8 revision, prod_id;
767
768 dbg("probe called: device is %p\n", pdev);
769
770 printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
771
772 /* enable platform-dependent hardware glue, if any */
773 if (dev_get_platdata(&pdev->dev))
774 pdata = dev_get_platdata(&pdev->dev);
775
776 if (pdata && pdata->platform_init_video)
777 pdata->platform_init_video();
778
779 if (pdev->num_resources != 2) {
780 dev_err(&pdev->dev, "invalid num_resources: %i\n",
781 pdev->num_resources);
782 ret = -ENODEV;
783 goto bail;
784 }
785
786 /* resource[0] is VRAM, resource[1] is registers */
787 if (pdev->resource[0].flags != IORESOURCE_MEM
788 || pdev->resource[1].flags != IORESOURCE_MEM) {
789 dev_err(&pdev->dev, "invalid resource type\n");
790 ret = -ENODEV;
791 goto bail;
792 }
793
794 if (!request_mem_region(pdev->resource[0].start,
795 resource_size(&pdev->resource[0]), "s1d13xxxfb mem")) {
796 dev_dbg(&pdev->dev, "request_mem_region failed\n");
797 ret = -EBUSY;
798 goto bail;
799 }
800
801 if (!request_mem_region(pdev->resource[1].start,
802 resource_size(&pdev->resource[1]), "s1d13xxxfb regs")) {
803 dev_dbg(&pdev->dev, "request_mem_region failed\n");
804 ret = -EBUSY;
805 goto bail;
806 }
807
808 info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
809 if (!info) {
810 ret = -ENOMEM;
811 goto bail;
812 }
813
814 platform_set_drvdata(pdev, info);
815 default_par = info->par;
816 default_par->regs = ioremap(pdev->resource[1].start,
817 resource_size(&pdev->resource[1]));
818 if (!default_par->regs) {
819 printk(KERN_ERR PFX "unable to map registers\n");
820 ret = -ENOMEM;
821 goto bail;
822 }
823 info->pseudo_palette = default_par->pseudo_palette;
824
825 info->screen_base = ioremap(pdev->resource[0].start,
826 resource_size(&pdev->resource[0]));
827
828 if (!info->screen_base) {
829 printk(KERN_ERR PFX "unable to map framebuffer\n");
830 ret = -ENOMEM;
831 goto bail;
832 }
833
834 /* production id is top 6 bits */
835 prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
836 /* revision id is lower 2 bits */
837 revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;
838 ret = -ENODEV;
839
840 for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) {
841 if (prod_id == s1d13xxxfb_prod_ids[i]) {
842 /* looks like we got it in our list */
843 default_par->prod_id = prod_id;
844 default_par->revision = revision;
845 ret = 0;
846 break;
847 }
848 }
849
850 if (!ret) {
851 printk(KERN_INFO PFX "chip production id %i = %s\n",
852 prod_id, s1d13xxxfb_prod_names[i]);
853 printk(KERN_INFO PFX "chip revision %i\n", revision);
854 } else {
855 printk(KERN_INFO PFX
856 "unknown chip production id %i, revision %i\n",
857 prod_id, revision);
858 printk(KERN_INFO PFX "please contact maintainer\n");
859 goto bail;
860 }
861
862 info->fix = s1d13xxxfb_fix;
863 info->fix.mmio_start = pdev->resource[1].start;
864 info->fix.mmio_len = resource_size(&pdev->resource[1]);
865 info->fix.smem_start = pdev->resource[0].start;
866 info->fix.smem_len = resource_size(&pdev->resource[0]);
867
868 printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
869 default_par->regs, info->fix.smem_len / 1024, info->screen_base);
870
871 info->par = default_par;
872 info->flags = FBINFO_HWACCEL_YPAN;
873 info->fbops = &s1d13xxxfb_fbops;
874
875 switch(prod_id) {
876 case S1D13506_PROD_ID: /* activate acceleration */
877 s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
878 s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
879 info->flags = FBINFO_HWACCEL_YPAN |
880 FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
881 break;
882 default:
883 break;
884 }
885
886 /* perform "manual" chip initialization, if needed */
887 if (pdata && pdata->initregs)
888 s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
889
890 s1d13xxxfb_fetch_hw_state(info);
891
892 if (register_framebuffer(info) < 0) {
893 ret = -EINVAL;
894 goto bail;
895 }
896
897 fb_info(info, "%s frame buffer device\n", info->fix.id);
898
899 return 0;
900
901 bail:
902 __s1d13xxxfb_remove(pdev);
903 return ret;
904
905 }
906
907 #ifdef CONFIG_PM
s1d13xxxfb_suspend(struct platform_device * dev,pm_message_t state)908 static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
909 {
910 struct fb_info *info = platform_get_drvdata(dev);
911 struct s1d13xxxfb_par *s1dfb = info->par;
912 struct s1d13xxxfb_pdata *pdata = NULL;
913
914 /* disable display */
915 lcd_enable(s1dfb, 0);
916 crt_enable(s1dfb, 0);
917
918 if (dev_get_platdata(&dev->dev))
919 pdata = dev_get_platdata(&dev->dev);
920
921 #if 0
922 if (!s1dfb->disp_save)
923 s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
924
925 if (!s1dfb->disp_save) {
926 printk(KERN_ERR PFX "no memory to save screen\n");
927 return -ENOMEM;
928 }
929
930 memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
931 #else
932 s1dfb->disp_save = NULL;
933 #endif
934
935 if (!s1dfb->regs_save)
936 s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
937
938 if (!s1dfb->regs_save) {
939 printk(KERN_ERR PFX "no memory to save registers");
940 return -ENOMEM;
941 }
942
943 /* backup all registers */
944 memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
945
946 /* now activate power save mode */
947 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
948
949 if (pdata && pdata->platform_suspend_video)
950 return pdata->platform_suspend_video();
951 else
952 return 0;
953 }
954
s1d13xxxfb_resume(struct platform_device * dev)955 static int s1d13xxxfb_resume(struct platform_device *dev)
956 {
957 struct fb_info *info = platform_get_drvdata(dev);
958 struct s1d13xxxfb_par *s1dfb = info->par;
959 struct s1d13xxxfb_pdata *pdata = NULL;
960
961 /* awaken the chip */
962 s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
963
964 /* do not let go until SDRAM "wakes up" */
965 while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
966 udelay(10);
967
968 if (dev_get_platdata(&dev->dev))
969 pdata = dev_get_platdata(&dev->dev);
970
971 if (s1dfb->regs_save) {
972 /* will write RO regs, *should* get away with it :) */
973 memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
974 kfree(s1dfb->regs_save);
975 }
976
977 if (s1dfb->disp_save) {
978 memcpy_toio(info->screen_base, s1dfb->disp_save,
979 info->fix.smem_len);
980 kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
981 }
982
983 if ((s1dfb->display & 0x01) != 0)
984 lcd_enable(s1dfb, 1);
985 if ((s1dfb->display & 0x02) != 0)
986 crt_enable(s1dfb, 1);
987
988 if (pdata && pdata->platform_resume_video)
989 return pdata->platform_resume_video();
990 else
991 return 0;
992 }
993 #endif /* CONFIG_PM */
994
995 static struct platform_driver s1d13xxxfb_driver = {
996 .probe = s1d13xxxfb_probe,
997 .remove_new = s1d13xxxfb_remove,
998 #ifdef CONFIG_PM
999 .suspend = s1d13xxxfb_suspend,
1000 .resume = s1d13xxxfb_resume,
1001 #endif
1002 .driver = {
1003 .name = S1D_DEVICENAME,
1004 },
1005 };
1006
1007
1008 static int __init
s1d13xxxfb_init(void)1009 s1d13xxxfb_init(void)
1010 {
1011
1012 #ifndef MODULE
1013 if (fb_get_options("s1d13xxxfb", NULL))
1014 return -ENODEV;
1015 #endif
1016
1017 return platform_driver_register(&s1d13xxxfb_driver);
1018 }
1019
1020
1021 static void __exit
s1d13xxxfb_exit(void)1022 s1d13xxxfb_exit(void)
1023 {
1024 platform_driver_unregister(&s1d13xxxfb_driver);
1025 }
1026
1027 module_init(s1d13xxxfb_init);
1028 module_exit(s1d13xxxfb_exit);
1029
1030
1031 MODULE_LICENSE("GPL");
1032 MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
1033 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");
1034
