1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * ISP116x register declarations and HCD data structures
4 *
5 * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
6 * Portions:
7 * Copyright (C) 2004 Lothar Wassmann
8 * Copyright (C) 2004 Psion Teklogix
9 * Copyright (C) 2004 David Brownell
10 */
11
12 /* us of 1ms frame */
13 #define MAX_LOAD_LIMIT 850
14
15 /* Full speed: max # of bytes to transfer for a single urb
16 at a time must be < 1024 && must be multiple of 64.
17 832 allows transferring 4kiB within 5 frames. */
18 #define MAX_TRANSFER_SIZE_FULLSPEED 832
19
20 /* Low speed: there is no reason to schedule in very big
21 chunks; often the requested long transfers are for
22 string descriptors containing short strings. */
23 #define MAX_TRANSFER_SIZE_LOWSPEED 64
24
25 /* Bytetime (us), a rough indication of how much time it
26 would take to transfer a byte of useful data over USB */
27 #define BYTE_TIME_FULLSPEED 1
28 #define BYTE_TIME_LOWSPEED 20
29
30 /* Buffer sizes */
31 #define ISP116x_BUF_SIZE 4096
32 #define ISP116x_ITL_BUFSIZE 0
33 #define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
34
35 #define ISP116x_WRITE_OFFSET 0x80
36
37 /*------------ ISP116x registers/bits ------------*/
38 #define HCREVISION 0x00
39 #define HCCONTROL 0x01
40 #define HCCONTROL_HCFS (3 << 6) /* host controller
41 functional state */
42 #define HCCONTROL_USB_RESET (0 << 6)
43 #define HCCONTROL_USB_RESUME (1 << 6)
44 #define HCCONTROL_USB_OPER (2 << 6)
45 #define HCCONTROL_USB_SUSPEND (3 << 6)
46 #define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
47 #define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
48 #define HCCMDSTAT 0x02
49 #define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
50 #define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
51 #define HCINTSTAT 0x03
52 #define HCINT_SO (1 << 0) /* scheduling overrun */
53 #define HCINT_WDH (1 << 1) /* writeback of done_head */
54 #define HCINT_SF (1 << 2) /* start frame */
55 #define HCINT_RD (1 << 3) /* resume detect */
56 #define HCINT_UE (1 << 4) /* unrecoverable error */
57 #define HCINT_FNO (1 << 5) /* frame number overflow */
58 #define HCINT_RHSC (1 << 6) /* root hub status change */
59 #define HCINT_OC (1 << 30) /* ownership change */
60 #define HCINT_MIE (1 << 31) /* master interrupt enable */
61 #define HCINTENB 0x04
62 #define HCINTDIS 0x05
63 #define HCFMINTVL 0x0d
64 #define HCFMREM 0x0e
65 #define HCFMNUM 0x0f
66 #define HCLSTHRESH 0x11
67 #define HCRHDESCA 0x12
68 #define RH_A_NDP (0x3 << 0) /* # downstream ports */
69 #define RH_A_PSM (1 << 8) /* power switching mode */
70 #define RH_A_NPS (1 << 9) /* no power switching */
71 #define RH_A_DT (1 << 10) /* device type (mbz) */
72 #define RH_A_OCPM (1 << 11) /* overcurrent protection
73 mode */
74 #define RH_A_NOCP (1 << 12) /* no overcurrent protection */
75 #define RH_A_POTPGT (0xff << 24) /* power on -> power good
76 time */
77 #define HCRHDESCB 0x13
78 #define RH_B_DR (0xffff << 0) /* device removable flags */
79 #define RH_B_PPCM (0xffff << 16) /* port power control mask */
80 #define HCRHSTATUS 0x14
81 #define RH_HS_LPS (1 << 0) /* local power status */
82 #define RH_HS_OCI (1 << 1) /* over current indicator */
83 #define RH_HS_DRWE (1 << 15) /* device remote wakeup
84 enable */
85 #define RH_HS_LPSC (1 << 16) /* local power status change */
86 #define RH_HS_OCIC (1 << 17) /* over current indicator
87 change */
88 #define RH_HS_CRWE (1 << 31) /* clear remote wakeup
89 enable */
90 #define HCRHPORT1 0x15
91 #define RH_PS_CCS (1 << 0) /* current connect status */
92 #define RH_PS_PES (1 << 1) /* port enable status */
93 #define RH_PS_PSS (1 << 2) /* port suspend status */
94 #define RH_PS_POCI (1 << 3) /* port over current
95 indicator */
96 #define RH_PS_PRS (1 << 4) /* port reset status */
97 #define RH_PS_PPS (1 << 8) /* port power status */
98 #define RH_PS_LSDA (1 << 9) /* low speed device attached */
99 #define RH_PS_CSC (1 << 16) /* connect status change */
100 #define RH_PS_PESC (1 << 17) /* port enable status change */
101 #define RH_PS_PSSC (1 << 18) /* port suspend status
102 change */
103 #define RH_PS_OCIC (1 << 19) /* over current indicator
104 change */
105 #define RH_PS_PRSC (1 << 20) /* port reset status change */
106 #define HCRHPORT_CLRMASK (0x1f << 16)
107 #define HCRHPORT2 0x16
108 #define HCHWCFG 0x20
109 #define HCHWCFG_15KRSEL (1 << 12)
110 #define HCHWCFG_CLKNOTSTOP (1 << 11)
111 #define HCHWCFG_ANALOG_OC (1 << 10)
112 #define HCHWCFG_DACK_MODE (1 << 8)
113 #define HCHWCFG_EOT_POL (1 << 7)
114 #define HCHWCFG_DACK_POL (1 << 6)
115 #define HCHWCFG_DREQ_POL (1 << 5)
116 #define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
117 #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
118 #define HCHWCFG_INT_POL (1 << 2)
119 #define HCHWCFG_INT_TRIGGER (1 << 1)
120 #define HCHWCFG_INT_ENABLE (1 << 0)
121 #define HCDMACFG 0x21
122 #define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
123 #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
124 #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
125 #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
126 #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
127 #define HCDMACFG_DMA_ENABLE (1 << 4)
128 #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
129 #define HCDMACFG_CTR_SEL (1 << 2)
130 #define HCDMACFG_ITLATL_SEL (1 << 1)
131 #define HCDMACFG_DMA_RW_SELECT (1 << 0)
132 #define HCXFERCTR 0x22
133 #define HCuPINT 0x24
134 #define HCuPINT_SOF (1 << 0)
135 #define HCuPINT_ATL (1 << 1)
136 #define HCuPINT_AIIEOT (1 << 2)
137 #define HCuPINT_OPR (1 << 4)
138 #define HCuPINT_SUSP (1 << 5)
139 #define HCuPINT_CLKRDY (1 << 6)
140 #define HCuPINTENB 0x25
141 #define HCCHIPID 0x27
142 #define HCCHIPID_MASK 0xff00
143 #define HCCHIPID_MAGIC 0x6100
144 #define HCSCRATCH 0x28
145 #define HCSWRES 0x29
146 #define HCSWRES_MAGIC 0x00f6
147 #define HCITLBUFLEN 0x2a
148 #define HCATLBUFLEN 0x2b
149 #define HCBUFSTAT 0x2c
150 #define HCBUFSTAT_ITL0_FULL (1 << 0)
151 #define HCBUFSTAT_ITL1_FULL (1 << 1)
152 #define HCBUFSTAT_ATL_FULL (1 << 2)
153 #define HCBUFSTAT_ITL0_DONE (1 << 3)
154 #define HCBUFSTAT_ITL1_DONE (1 << 4)
155 #define HCBUFSTAT_ATL_DONE (1 << 5)
156 #define HCRDITL0LEN 0x2d
157 #define HCRDITL1LEN 0x2e
158 #define HCITLPORT 0x40
159 #define HCATLPORT 0x41
160
161 /* Philips transfer descriptor */
162 struct ptd {
163 u16 count;
164 #define PTD_COUNT_MSK (0x3ff << 0)
165 #define PTD_TOGGLE_MSK (1 << 10)
166 #define PTD_ACTIVE_MSK (1 << 11)
167 #define PTD_CC_MSK (0xf << 12)
168 u16 mps;
169 #define PTD_MPS_MSK (0x3ff << 0)
170 #define PTD_SPD_MSK (1 << 10)
171 #define PTD_LAST_MSK (1 << 11)
172 #define PTD_EP_MSK (0xf << 12)
173 u16 len;
174 #define PTD_LEN_MSK (0x3ff << 0)
175 #define PTD_DIR_MSK (3 << 10)
176 #define PTD_DIR_SETUP (0)
177 #define PTD_DIR_OUT (1)
178 #define PTD_DIR_IN (2)
179 #define PTD_B5_5_MSK (1 << 13)
180 u16 faddr;
181 #define PTD_FA_MSK (0x7f << 0)
182 #define PTD_FMT_MSK (1 << 7)
183 } __attribute__ ((packed, aligned(2)));
184
185 /* PTD accessor macros. */
186 #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
187 #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
188 #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
189 #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
190 #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
191 #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
192 #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
193 #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
194 #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
195 #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
196 #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
197 #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
198 #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
199 #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
200 #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
201 #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
202 #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
203 #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
204 #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
205 #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
206 #define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
207 #define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
208 #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
209 #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
210 #define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
211 #define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
212
213 /* Hardware transfer status codes -- CC from ptd->count */
214 #define TD_CC_NOERROR 0x00
215 #define TD_CC_CRC 0x01
216 #define TD_CC_BITSTUFFING 0x02
217 #define TD_CC_DATATOGGLEM 0x03
218 #define TD_CC_STALL 0x04
219 #define TD_DEVNOTRESP 0x05
220 #define TD_PIDCHECKFAIL 0x06
221 #define TD_UNEXPECTEDPID 0x07
222 #define TD_DATAOVERRUN 0x08
223 #define TD_DATAUNDERRUN 0x09
224 /* 0x0A, 0x0B reserved for hardware */
225 #define TD_BUFFEROVERRUN 0x0C
226 #define TD_BUFFERUNDERRUN 0x0D
227 /* 0x0E, 0x0F reserved for HCD */
228 #define TD_NOTACCESSED 0x0F
229
230 /* map PTD status codes (CC) to errno values */
231 static const int cc_to_error[16] = {
232 /* No Error */ 0,
233 /* CRC Error */ -EILSEQ,
234 /* Bit Stuff */ -EPROTO,
235 /* Data Togg */ -EILSEQ,
236 /* Stall */ -EPIPE,
237 /* DevNotResp */ -ETIME,
238 /* PIDCheck */ -EPROTO,
239 /* UnExpPID */ -EPROTO,
240 /* DataOver */ -EOVERFLOW,
241 /* DataUnder */ -EREMOTEIO,
242 /* (for hw) */ -EIO,
243 /* (for hw) */ -EIO,
244 /* BufferOver */ -ECOMM,
245 /* BuffUnder */ -ENOSR,
246 /* (for HCD) */ -EALREADY,
247 /* (for HCD) */ -EALREADY
248 };
249
250 /*--------------------------------------------------------------*/
251
252 #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
253 #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
254
255 struct isp116x {
256 spinlock_t lock;
257
258 void __iomem *addr_reg;
259 void __iomem *data_reg;
260
261 struct isp116x_platform_data *board;
262
263 struct dentry *dentry;
264 unsigned long stat1, stat2, stat4, stat8, stat16;
265
266 /* HC registers */
267 u32 intenb; /* "OHCI" interrupts */
268 u16 irqenb; /* uP interrupts */
269
270 /* Root hub registers */
271 u32 rhdesca;
272 u32 rhdescb;
273 u32 rhstatus;
274
275 /* async schedule: control, bulk */
276 struct list_head async;
277
278 /* periodic schedule: int */
279 u16 load[PERIODIC_SIZE];
280 struct isp116x_ep *periodic[PERIODIC_SIZE];
281 unsigned periodic_count;
282 u16 fmindex;
283
284 /* Schedule for the current frame */
285 struct isp116x_ep *atl_active;
286 int atl_buflen;
287 int atl_bufshrt;
288 int atl_last_dir;
289 atomic_t atl_finishing;
290 };
291
hcd_to_isp116x(struct usb_hcd * hcd)292 static inline struct isp116x *hcd_to_isp116x(struct usb_hcd *hcd)
293 {
294 return (struct isp116x *)(hcd->hcd_priv);
295 }
296
isp116x_to_hcd(struct isp116x * isp116x)297 static inline struct usb_hcd *isp116x_to_hcd(struct isp116x *isp116x)
298 {
299 return container_of((void *)isp116x, struct usb_hcd, hcd_priv);
300 }
301
302 struct isp116x_ep {
303 struct usb_host_endpoint *hep;
304 struct usb_device *udev;
305 struct ptd ptd;
306
307 u8 maxpacket;
308 u8 epnum;
309 u8 nextpid;
310 u16 error_count;
311 u16 length; /* of current packet */
312 unsigned char *data; /* to databuf */
313 /* queue of active EP's (the ones scheduled for the
314 current frame) */
315 struct isp116x_ep *active;
316
317 /* periodic schedule */
318 u16 period;
319 u16 branch;
320 u16 load;
321 struct isp116x_ep *next;
322
323 /* async schedule */
324 struct list_head schedule;
325 };
326
327 /*-------------------------------------------------------------------------*/
328
329 #define DBG(stuff...) pr_debug("116x: " stuff)
330
331 #ifdef VERBOSE
332 # define VDBG DBG
333 #else
334 # define VDBG(stuff...) do{}while(0)
335 #endif
336
337 #define ERR(stuff...) printk(KERN_ERR "116x: " stuff)
338 #define WARNING(stuff...) printk(KERN_WARNING "116x: " stuff)
339 #define INFO(stuff...) printk(KERN_INFO "116x: " stuff)
340
341 /* ------------------------------------------------- */
342
343 #if defined(USE_PLATFORM_DELAY)
344 #if defined(USE_NDELAY)
345 #error USE_PLATFORM_DELAY and USE_NDELAY simultaneously defined.
346 #endif
347 #define isp116x_delay(h,d) (h)->board->delay( \
348 isp116x_to_hcd(h)->self.controller,d)
349 #define isp116x_check_platform_delay(h) ((h)->board->delay == NULL)
350 #elif defined(USE_NDELAY)
351 #define isp116x_delay(h,d) ndelay(d)
352 #define isp116x_check_platform_delay(h) 0
353 #else
354 #define isp116x_delay(h,d) do{}while(0)
355 #define isp116x_check_platform_delay(h) 0
356 #endif
357
isp116x_write_addr(struct isp116x * isp116x,unsigned reg)358 static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
359 {
360 writew(reg & 0xff, isp116x->addr_reg);
361 isp116x_delay(isp116x, 300);
362 }
363
isp116x_write_data16(struct isp116x * isp116x,u16 val)364 static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
365 {
366 writew(val, isp116x->data_reg);
367 isp116x_delay(isp116x, 150);
368 }
369
isp116x_raw_write_data16(struct isp116x * isp116x,u16 val)370 static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
371 {
372 __raw_writew(val, isp116x->data_reg);
373 isp116x_delay(isp116x, 150);
374 }
375
isp116x_read_data16(struct isp116x * isp116x)376 static inline u16 isp116x_read_data16(struct isp116x *isp116x)
377 {
378 u16 val;
379
380 val = readw(isp116x->data_reg);
381 isp116x_delay(isp116x, 150);
382 return val;
383 }
384
isp116x_raw_read_data16(struct isp116x * isp116x)385 static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
386 {
387 u16 val;
388
389 val = __raw_readw(isp116x->data_reg);
390 isp116x_delay(isp116x, 150);
391 return val;
392 }
393
isp116x_write_data32(struct isp116x * isp116x,u32 val)394 static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
395 {
396 writew(val & 0xffff, isp116x->data_reg);
397 isp116x_delay(isp116x, 150);
398 writew(val >> 16, isp116x->data_reg);
399 isp116x_delay(isp116x, 150);
400 }
401
isp116x_read_data32(struct isp116x * isp116x)402 static inline u32 isp116x_read_data32(struct isp116x *isp116x)
403 {
404 u32 val;
405
406 val = (u32) readw(isp116x->data_reg);
407 isp116x_delay(isp116x, 150);
408 val |= ((u32) readw(isp116x->data_reg)) << 16;
409 isp116x_delay(isp116x, 150);
410 return val;
411 }
412
413 /* Let's keep register access functions out of line. Hint:
414 we wait at least 150 ns at every access.
415 */
isp116x_read_reg16(struct isp116x * isp116x,unsigned reg)416 static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
417 {
418 isp116x_write_addr(isp116x, reg);
419 return isp116x_read_data16(isp116x);
420 }
421
isp116x_read_reg32(struct isp116x * isp116x,unsigned reg)422 static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
423 {
424 isp116x_write_addr(isp116x, reg);
425 return isp116x_read_data32(isp116x);
426 }
427
isp116x_write_reg16(struct isp116x * isp116x,unsigned reg,unsigned val)428 static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
429 unsigned val)
430 {
431 isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
432 isp116x_write_data16(isp116x, (u16) (val & 0xffff));
433 }
434
isp116x_write_reg32(struct isp116x * isp116x,unsigned reg,unsigned val)435 static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
436 unsigned val)
437 {
438 isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
439 isp116x_write_data32(isp116x, (u32) val);
440 }
441
442 #define isp116x_show_reg_log(d,r,s) { \
443 if ((r) < 0x20) { \
444 DBG("%-12s[%02x]: %08x\n", #r, \
445 r, isp116x_read_reg32(d, r)); \
446 } else { \
447 DBG("%-12s[%02x]: %04x\n", #r, \
448 r, isp116x_read_reg16(d, r)); \
449 } \
450 }
451 #define isp116x_show_reg_seq(d,r,s) { \
452 if ((r) < 0x20) { \
453 seq_printf(s, "%-12s[%02x]: %08x\n", #r, \
454 r, isp116x_read_reg32(d, r)); \
455 } else { \
456 seq_printf(s, "%-12s[%02x]: %04x\n", #r, \
457 r, isp116x_read_reg16(d, r)); \
458 } \
459 }
460
461 #define isp116x_show_regs(d,type,s) { \
462 isp116x_show_reg_##type(d, HCREVISION, s); \
463 isp116x_show_reg_##type(d, HCCONTROL, s); \
464 isp116x_show_reg_##type(d, HCCMDSTAT, s); \
465 isp116x_show_reg_##type(d, HCINTSTAT, s); \
466 isp116x_show_reg_##type(d, HCINTENB, s); \
467 isp116x_show_reg_##type(d, HCFMINTVL, s); \
468 isp116x_show_reg_##type(d, HCFMREM, s); \
469 isp116x_show_reg_##type(d, HCFMNUM, s); \
470 isp116x_show_reg_##type(d, HCLSTHRESH, s); \
471 isp116x_show_reg_##type(d, HCRHDESCA, s); \
472 isp116x_show_reg_##type(d, HCRHDESCB, s); \
473 isp116x_show_reg_##type(d, HCRHSTATUS, s); \
474 isp116x_show_reg_##type(d, HCRHPORT1, s); \
475 isp116x_show_reg_##type(d, HCRHPORT2, s); \
476 isp116x_show_reg_##type(d, HCHWCFG, s); \
477 isp116x_show_reg_##type(d, HCDMACFG, s); \
478 isp116x_show_reg_##type(d, HCXFERCTR, s); \
479 isp116x_show_reg_##type(d, HCuPINT, s); \
480 isp116x_show_reg_##type(d, HCuPINTENB, s); \
481 isp116x_show_reg_##type(d, HCCHIPID, s); \
482 isp116x_show_reg_##type(d, HCSCRATCH, s); \
483 isp116x_show_reg_##type(d, HCITLBUFLEN, s); \
484 isp116x_show_reg_##type(d, HCATLBUFLEN, s); \
485 isp116x_show_reg_##type(d, HCBUFSTAT, s); \
486 isp116x_show_reg_##type(d, HCRDITL0LEN, s); \
487 isp116x_show_reg_##type(d, HCRDITL1LEN, s); \
488 }
489
490 /*
491 Dump registers for debugfs.
492 */
isp116x_show_regs_seq(struct isp116x * isp116x,struct seq_file * s)493 static inline void isp116x_show_regs_seq(struct isp116x *isp116x,
494 struct seq_file *s)
495 {
496 isp116x_show_regs(isp116x, seq, s);
497 }
498
499 /*
500 Dump registers to syslog.
501 */
isp116x_show_regs_log(struct isp116x * isp116x)502 static inline void isp116x_show_regs_log(struct isp116x *isp116x)
503 {
504 isp116x_show_regs(isp116x, log, NULL);
505 }
506
507 #if defined(URB_TRACE)
508
509 #define PIPETYPE(pipe) ({ char *__s; \
510 if (usb_pipecontrol(pipe)) __s = "ctrl"; \
511 else if (usb_pipeint(pipe)) __s = "int"; \
512 else if (usb_pipebulk(pipe)) __s = "bulk"; \
513 else __s = "iso"; \
514 __s;})
515 #define PIPEDIR(pipe) ({ usb_pipein(pipe) ? "in" : "out"; })
516 #define URB_NOTSHORT(urb) ({ (urb)->transfer_flags & URB_SHORT_NOT_OK ? \
517 "short_not_ok" : ""; })
518
519 /* print debug info about the URB */
urb_dbg(struct urb * urb,char * msg)520 static void urb_dbg(struct urb *urb, char *msg)
521 {
522 unsigned int pipe;
523
524 if (!urb) {
525 DBG("%s: zero urb\n", msg);
526 return;
527 }
528 pipe = urb->pipe;
529 DBG("%s: FA %d ep%d%s %s: len %d/%d %s\n", msg,
530 usb_pipedevice(pipe), usb_pipeendpoint(pipe),
531 PIPEDIR(pipe), PIPETYPE(pipe),
532 urb->transfer_buffer_length, urb->actual_length, URB_NOTSHORT(urb));
533 }
534
535 #else
536
537 #define urb_dbg(urb,msg) do{}while(0)
538
539 #endif /* ! defined(URB_TRACE) */
540
541 #if defined(PTD_TRACE)
542
543 #define PTD_DIR_STR(ptd) ({char __c; \
544 switch(PTD_GET_DIR(ptd)){ \
545 case 0: __c = 's'; break; \
546 case 1: __c = 'o'; break; \
547 default: __c = 'i'; break; \
548 }; __c;})
549
550 /*
551 Dump PTD info. The code documents the format
552 perfectly, right :)
553 */
dump_ptd(struct ptd * ptd)554 static inline void dump_ptd(struct ptd *ptd)
555 {
556 printk(KERN_WARNING "td: %x %d%c%d %d,%d,%d %x %x%x%x\n",
557 PTD_GET_CC(ptd), PTD_GET_FA(ptd),
558 PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
559 PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
560 PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd),
561 PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
562 }
563
dump_ptd_out_data(struct ptd * ptd,u8 * buf)564 static inline void dump_ptd_out_data(struct ptd *ptd, u8 * buf)
565 {
566 int k;
567
568 if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) {
569 printk(KERN_WARNING "-> ");
570 for (k = 0; k < PTD_GET_LEN(ptd); ++k)
571 printk("%02x ", ((u8 *) buf)[k]);
572 printk("\n");
573 }
574 }
575
dump_ptd_in_data(struct ptd * ptd,u8 * buf)576 static inline void dump_ptd_in_data(struct ptd *ptd, u8 * buf)
577 {
578 int k;
579
580 if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) {
581 printk(KERN_WARNING "<- ");
582 for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
583 printk("%02x ", ((u8 *) buf)[k]);
584 printk("\n");
585 }
586 if (PTD_GET_LAST(ptd))
587 printk(KERN_WARNING "-\n");
588 }
589
590 #else
591
592 #define dump_ptd(ptd) do{}while(0)
593 #define dump_ptd_in_data(ptd,buf) do{}while(0)
594 #define dump_ptd_out_data(ptd,buf) do{}while(0)
595
596 #endif /* ! defined(PTD_TRACE) */
597
