1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/io.h>
9 #include <linux/of.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb.h>
25 #include "core.h"
26
27 /* USB QSCRATCH Hardware registers */
28 #define QSCRATCH_HS_PHY_CTRL 0x10
29 #define UTMI_OTG_VBUS_VALID BIT(20)
30 #define SW_SESSVLD_SEL BIT(28)
31
32 #define QSCRATCH_SS_PHY_CTRL 0x30
33 #define LANE0_PWR_PRESENT BIT(24)
34
35 #define QSCRATCH_GENERAL_CFG 0x08
36 #define PIPE_UTMI_CLK_SEL BIT(0)
37 #define PIPE3_PHYSTATUS_SW BIT(3)
38 #define PIPE_UTMI_CLK_DIS BIT(8)
39
40 #define PWR_EVNT_IRQ_STAT_REG 0x58
41 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
42 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
43
44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45 #define SDM845_QSCRATCH_SIZE 0x400
46 #define SDM845_DWC3_CORE_SIZE 0xcd00
47
48 /* Interconnect path bandwidths in MBps */
49 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
50 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
51 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
52 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
53 #define APPS_USB_AVG_BW 0
54 #define APPS_USB_PEAK_BW MBps_to_icc(40)
55
56 struct dwc3_acpi_pdata {
57 u32 qscratch_base_offset;
58 u32 qscratch_base_size;
59 u32 dwc3_core_base_size;
60 int hs_phy_irq_index;
61 int dp_hs_phy_irq_index;
62 int dm_hs_phy_irq_index;
63 int ss_phy_irq_index;
64 bool is_urs;
65 };
66
67 struct dwc3_qcom {
68 struct device *dev;
69 void __iomem *qscratch_base;
70 struct platform_device *dwc3;
71 struct platform_device *urs_usb;
72 struct clk **clks;
73 int num_clocks;
74 struct reset_control *resets;
75
76 int hs_phy_irq;
77 int dp_hs_phy_irq;
78 int dm_hs_phy_irq;
79 int ss_phy_irq;
80 enum usb_device_speed usb2_speed;
81
82 struct extcon_dev *edev;
83 struct extcon_dev *host_edev;
84 struct notifier_block vbus_nb;
85 struct notifier_block host_nb;
86
87 const struct dwc3_acpi_pdata *acpi_pdata;
88
89 enum usb_dr_mode mode;
90 bool is_suspended;
91 bool pm_suspended;
92 struct icc_path *icc_path_ddr;
93 struct icc_path *icc_path_apps;
94 };
95
dwc3_qcom_setbits(void __iomem * base,u32 offset,u32 val)96 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
97 {
98 u32 reg;
99
100 reg = readl(base + offset);
101 reg |= val;
102 writel(reg, base + offset);
103
104 /* ensure that above write is through */
105 readl(base + offset);
106 }
107
dwc3_qcom_clrbits(void __iomem * base,u32 offset,u32 val)108 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
109 {
110 u32 reg;
111
112 reg = readl(base + offset);
113 reg &= ~val;
114 writel(reg, base + offset);
115
116 /* ensure that above write is through */
117 readl(base + offset);
118 }
119
dwc3_qcom_vbus_override_enable(struct dwc3_qcom * qcom,bool enable)120 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
121 {
122 if (enable) {
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
124 LANE0_PWR_PRESENT);
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
127 } else {
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
129 LANE0_PWR_PRESENT);
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
132 }
133 }
134
dwc3_qcom_vbus_notifier(struct notifier_block * nb,unsigned long event,void * ptr)135 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
136 unsigned long event, void *ptr)
137 {
138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
139
140 /* enable vbus override for device mode */
141 dwc3_qcom_vbus_override_enable(qcom, event);
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
143
144 return NOTIFY_DONE;
145 }
146
dwc3_qcom_host_notifier(struct notifier_block * nb,unsigned long event,void * ptr)147 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
148 unsigned long event, void *ptr)
149 {
150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
151
152 /* disable vbus override in host mode */
153 dwc3_qcom_vbus_override_enable(qcom, !event);
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
155
156 return NOTIFY_DONE;
157 }
158
dwc3_qcom_register_extcon(struct dwc3_qcom * qcom)159 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
160 {
161 struct device *dev = qcom->dev;
162 struct extcon_dev *host_edev;
163 int ret;
164
165 if (!of_property_read_bool(dev->of_node, "extcon"))
166 return 0;
167
168 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
169 if (IS_ERR(qcom->edev))
170 return PTR_ERR(qcom->edev);
171
172 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
173
174 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
175 if (IS_ERR(qcom->host_edev))
176 qcom->host_edev = NULL;
177
178 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
179 &qcom->vbus_nb);
180 if (ret < 0) {
181 dev_err(dev, "VBUS notifier register failed\n");
182 return ret;
183 }
184
185 if (qcom->host_edev)
186 host_edev = qcom->host_edev;
187 else
188 host_edev = qcom->edev;
189
190 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
191 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
192 &qcom->host_nb);
193 if (ret < 0) {
194 dev_err(dev, "Host notifier register failed\n");
195 return ret;
196 }
197
198 /* Update initial VBUS override based on extcon state */
199 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
200 !extcon_get_state(host_edev, EXTCON_USB_HOST))
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
202 else
203 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
204
205 return 0;
206 }
207
dwc3_qcom_interconnect_enable(struct dwc3_qcom * qcom)208 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
209 {
210 int ret;
211
212 ret = icc_enable(qcom->icc_path_ddr);
213 if (ret)
214 return ret;
215
216 ret = icc_enable(qcom->icc_path_apps);
217 if (ret)
218 icc_disable(qcom->icc_path_ddr);
219
220 return ret;
221 }
222
dwc3_qcom_interconnect_disable(struct dwc3_qcom * qcom)223 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
224 {
225 int ret;
226
227 ret = icc_disable(qcom->icc_path_ddr);
228 if (ret)
229 return ret;
230
231 ret = icc_disable(qcom->icc_path_apps);
232 if (ret)
233 icc_enable(qcom->icc_path_ddr);
234
235 return ret;
236 }
237
238 /**
239 * dwc3_qcom_interconnect_init() - Get interconnect path handles
240 * and set bandwidth.
241 * @qcom: Pointer to the concerned usb core.
242 *
243 */
dwc3_qcom_interconnect_init(struct dwc3_qcom * qcom)244 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
245 {
246 enum usb_device_speed max_speed;
247 struct device *dev = qcom->dev;
248 int ret;
249
250 if (has_acpi_companion(dev))
251 return 0;
252
253 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
254 if (IS_ERR(qcom->icc_path_ddr)) {
255 dev_err(dev, "failed to get usb-ddr path: %ld\n",
256 PTR_ERR(qcom->icc_path_ddr));
257 return PTR_ERR(qcom->icc_path_ddr);
258 }
259
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 dev_err(dev, "failed to get apps-usb path: %ld\n",
263 PTR_ERR(qcom->icc_path_apps));
264 return PTR_ERR(qcom->icc_path_apps);
265 }
266
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
271 } else {
272 ret = icc_set_bw(qcom->icc_path_ddr,
273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
274 }
275 if (ret) {
276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
277 return ret;
278 }
279
280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
281 if (ret) {
282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
283 return ret;
284 }
285
286 return 0;
287 }
288
289 /**
290 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
291 * @qcom: Pointer to the concerned usb core.
292 *
293 * This function is used to release interconnect path handle.
294 */
dwc3_qcom_interconnect_exit(struct dwc3_qcom * qcom)295 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
296 {
297 icc_put(qcom->icc_path_ddr);
298 icc_put(qcom->icc_path_apps);
299 }
300
301 /* Only usable in contexts where the role can not change. */
dwc3_qcom_is_host(struct dwc3_qcom * qcom)302 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
303 {
304 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
305
306 return dwc->xhci;
307 }
308
dwc3_qcom_read_usb2_speed(struct dwc3_qcom * qcom)309 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
310 {
311 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
312 struct usb_device *udev;
313 struct usb_hcd __maybe_unused *hcd;
314
315 /*
316 * FIXME: Fix this layering violation.
317 */
318 hcd = platform_get_drvdata(dwc->xhci);
319
320 /*
321 * It is possible to query the speed of all children of
322 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
323 * currently supports only 1 port per controller. So
324 * this is sufficient.
325 */
326 #ifdef CONFIG_USB
327 udev = usb_hub_find_child(hcd->self.root_hub, 1);
328 #else
329 udev = NULL;
330 #endif
331 if (!udev)
332 return USB_SPEED_UNKNOWN;
333
334 return udev->speed;
335 }
336
dwc3_qcom_enable_wakeup_irq(int irq,unsigned int polarity)337 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
338 {
339 if (!irq)
340 return;
341
342 if (polarity)
343 irq_set_irq_type(irq, polarity);
344
345 enable_irq(irq);
346 enable_irq_wake(irq);
347 }
348
dwc3_qcom_disable_wakeup_irq(int irq)349 static void dwc3_qcom_disable_wakeup_irq(int irq)
350 {
351 if (!irq)
352 return;
353
354 disable_irq_wake(irq);
355 disable_irq_nosync(irq);
356 }
357
dwc3_qcom_disable_interrupts(struct dwc3_qcom * qcom)358 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
359 {
360 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
361
362 if (qcom->usb2_speed == USB_SPEED_LOW) {
363 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
364 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
365 (qcom->usb2_speed == USB_SPEED_FULL)) {
366 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
367 } else {
368 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
369 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
370 }
371
372 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
373 }
374
dwc3_qcom_enable_interrupts(struct dwc3_qcom * qcom)375 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
376 {
377 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
378
379 /*
380 * Configure DP/DM line interrupts based on the USB2 device attached to
381 * the root hub port. When HS/FS device is connected, configure the DP line
382 * as falling edge to detect both disconnect and remote wakeup scenarios. When
383 * LS device is connected, configure DM line as falling edge to detect both
384 * disconnect and remote wakeup. When no device is connected, configure both
385 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
386 */
387
388 if (qcom->usb2_speed == USB_SPEED_LOW) {
389 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
390 IRQ_TYPE_EDGE_FALLING);
391 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
392 (qcom->usb2_speed == USB_SPEED_FULL)) {
393 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
394 IRQ_TYPE_EDGE_FALLING);
395 } else {
396 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
397 IRQ_TYPE_EDGE_RISING);
398 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
399 IRQ_TYPE_EDGE_RISING);
400 }
401
402 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
403 }
404
dwc3_qcom_suspend(struct dwc3_qcom * qcom,bool wakeup)405 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
406 {
407 u32 val;
408 int i, ret;
409
410 if (qcom->is_suspended)
411 return 0;
412
413 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
414 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
415 dev_err(qcom->dev, "HS-PHY not in L2\n");
416
417 for (i = qcom->num_clocks - 1; i >= 0; i--)
418 clk_disable_unprepare(qcom->clks[i]);
419
420 ret = dwc3_qcom_interconnect_disable(qcom);
421 if (ret)
422 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
423
424 /*
425 * The role is stable during suspend as role switching is done from a
426 * freezable workqueue.
427 */
428 if (dwc3_qcom_is_host(qcom) && wakeup) {
429 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
430 dwc3_qcom_enable_interrupts(qcom);
431 }
432
433 qcom->is_suspended = true;
434
435 return 0;
436 }
437
dwc3_qcom_resume(struct dwc3_qcom * qcom,bool wakeup)438 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
439 {
440 int ret;
441 int i;
442
443 if (!qcom->is_suspended)
444 return 0;
445
446 if (dwc3_qcom_is_host(qcom) && wakeup)
447 dwc3_qcom_disable_interrupts(qcom);
448
449 for (i = 0; i < qcom->num_clocks; i++) {
450 ret = clk_prepare_enable(qcom->clks[i]);
451 if (ret < 0) {
452 while (--i >= 0)
453 clk_disable_unprepare(qcom->clks[i]);
454 return ret;
455 }
456 }
457
458 ret = dwc3_qcom_interconnect_enable(qcom);
459 if (ret)
460 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
461
462 /* Clear existing events from PHY related to L2 in/out */
463 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
464 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
465
466 qcom->is_suspended = false;
467
468 return 0;
469 }
470
qcom_dwc3_resume_irq(int irq,void * data)471 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
472 {
473 struct dwc3_qcom *qcom = data;
474 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
475
476 /* If pm_suspended then let pm_resume take care of resuming h/w */
477 if (qcom->pm_suspended)
478 return IRQ_HANDLED;
479
480 /*
481 * This is safe as role switching is done from a freezable workqueue
482 * and the wakeup interrupts are disabled as part of resume.
483 */
484 if (dwc3_qcom_is_host(qcom))
485 pm_runtime_resume(&dwc->xhci->dev);
486
487 return IRQ_HANDLED;
488 }
489
dwc3_qcom_select_utmi_clk(struct dwc3_qcom * qcom)490 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
491 {
492 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
493 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
494 PIPE_UTMI_CLK_DIS);
495
496 usleep_range(100, 1000);
497
498 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
499 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
500
501 usleep_range(100, 1000);
502
503 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
504 PIPE_UTMI_CLK_DIS);
505 }
506
dwc3_qcom_get_irq(struct platform_device * pdev,const char * name,int num)507 static int dwc3_qcom_get_irq(struct platform_device *pdev,
508 const char *name, int num)
509 {
510 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
511 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
512 struct device_node *np = pdev->dev.of_node;
513 int ret;
514
515 if (np)
516 ret = platform_get_irq_byname_optional(pdev_irq, name);
517 else
518 ret = platform_get_irq_optional(pdev_irq, num);
519
520 return ret;
521 }
522
dwc3_qcom_setup_irq(struct platform_device * pdev)523 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
524 {
525 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
526 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
527 int irq;
528 int ret;
529
530 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
531 pdata ? pdata->hs_phy_irq_index : -1);
532 if (irq > 0) {
533 /* Keep wakeup interrupts disabled until suspend */
534 irq_set_status_flags(irq, IRQ_NOAUTOEN);
535 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
536 qcom_dwc3_resume_irq,
537 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
538 "qcom_dwc3 HS", qcom);
539 if (ret) {
540 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
541 return ret;
542 }
543 qcom->hs_phy_irq = irq;
544 }
545
546 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
547 pdata ? pdata->dp_hs_phy_irq_index : -1);
548 if (irq > 0) {
549 irq_set_status_flags(irq, IRQ_NOAUTOEN);
550 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
551 qcom_dwc3_resume_irq,
552 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
553 "qcom_dwc3 DP_HS", qcom);
554 if (ret) {
555 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
556 return ret;
557 }
558 qcom->dp_hs_phy_irq = irq;
559 }
560
561 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
562 pdata ? pdata->dm_hs_phy_irq_index : -1);
563 if (irq > 0) {
564 irq_set_status_flags(irq, IRQ_NOAUTOEN);
565 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
566 qcom_dwc3_resume_irq,
567 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
568 "qcom_dwc3 DM_HS", qcom);
569 if (ret) {
570 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
571 return ret;
572 }
573 qcom->dm_hs_phy_irq = irq;
574 }
575
576 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
577 pdata ? pdata->ss_phy_irq_index : -1);
578 if (irq > 0) {
579 irq_set_status_flags(irq, IRQ_NOAUTOEN);
580 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
581 qcom_dwc3_resume_irq,
582 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
583 "qcom_dwc3 SS", qcom);
584 if (ret) {
585 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
586 return ret;
587 }
588 qcom->ss_phy_irq = irq;
589 }
590
591 return 0;
592 }
593
dwc3_qcom_clk_init(struct dwc3_qcom * qcom,int count)594 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
595 {
596 struct device *dev = qcom->dev;
597 struct device_node *np = dev->of_node;
598 int i;
599
600 if (!np || !count)
601 return 0;
602
603 if (count < 0)
604 return count;
605
606 qcom->num_clocks = count;
607
608 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
609 sizeof(struct clk *), GFP_KERNEL);
610 if (!qcom->clks)
611 return -ENOMEM;
612
613 for (i = 0; i < qcom->num_clocks; i++) {
614 struct clk *clk;
615 int ret;
616
617 clk = of_clk_get(np, i);
618 if (IS_ERR(clk)) {
619 while (--i >= 0)
620 clk_put(qcom->clks[i]);
621 return PTR_ERR(clk);
622 }
623
624 ret = clk_prepare_enable(clk);
625 if (ret < 0) {
626 while (--i >= 0) {
627 clk_disable_unprepare(qcom->clks[i]);
628 clk_put(qcom->clks[i]);
629 }
630 clk_put(clk);
631
632 return ret;
633 }
634
635 qcom->clks[i] = clk;
636 }
637
638 return 0;
639 }
640
641 static const struct property_entry dwc3_qcom_acpi_properties[] = {
642 PROPERTY_ENTRY_STRING("dr_mode", "host"),
643 {}
644 };
645
646 static const struct software_node dwc3_qcom_swnode = {
647 .properties = dwc3_qcom_acpi_properties,
648 };
649
dwc3_qcom_acpi_register_core(struct platform_device * pdev)650 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
651 {
652 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
653 struct device *dev = &pdev->dev;
654 struct resource *res, *child_res = NULL;
655 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
656 pdev;
657 int irq;
658 int ret;
659
660 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
661 if (!qcom->dwc3)
662 return -ENOMEM;
663
664 qcom->dwc3->dev.parent = dev;
665 qcom->dwc3->dev.type = dev->type;
666 qcom->dwc3->dev.dma_mask = dev->dma_mask;
667 qcom->dwc3->dev.dma_parms = dev->dma_parms;
668 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
669
670 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
671 if (!child_res) {
672 platform_device_put(qcom->dwc3);
673 return -ENOMEM;
674 }
675
676 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
677 if (!res) {
678 dev_err(&pdev->dev, "failed to get memory resource\n");
679 ret = -ENODEV;
680 goto out;
681 }
682
683 child_res[0].flags = res->flags;
684 child_res[0].start = res->start;
685 child_res[0].end = child_res[0].start +
686 qcom->acpi_pdata->dwc3_core_base_size;
687
688 irq = platform_get_irq(pdev_irq, 0);
689 if (irq < 0) {
690 ret = irq;
691 goto out;
692 }
693 child_res[1].flags = IORESOURCE_IRQ;
694 child_res[1].start = child_res[1].end = irq;
695
696 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
697 if (ret) {
698 dev_err(&pdev->dev, "failed to add resources\n");
699 goto out;
700 }
701
702 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
703 if (ret < 0) {
704 dev_err(&pdev->dev, "failed to add properties\n");
705 goto out;
706 }
707
708 ret = platform_device_add(qcom->dwc3);
709 if (ret) {
710 dev_err(&pdev->dev, "failed to add device\n");
711 device_remove_software_node(&qcom->dwc3->dev);
712 goto out;
713 }
714 kfree(child_res);
715 return 0;
716
717 out:
718 platform_device_put(qcom->dwc3);
719 kfree(child_res);
720 return ret;
721 }
722
dwc3_qcom_of_register_core(struct platform_device * pdev)723 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
724 {
725 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
726 struct device_node *np = pdev->dev.of_node, *dwc3_np;
727 struct device *dev = &pdev->dev;
728 int ret;
729
730 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
731 if (!dwc3_np) {
732 dev_err(dev, "failed to find dwc3 core child\n");
733 return -ENODEV;
734 }
735
736 ret = of_platform_populate(np, NULL, NULL, dev);
737 if (ret) {
738 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
739 goto node_put;
740 }
741
742 qcom->dwc3 = of_find_device_by_node(dwc3_np);
743 if (!qcom->dwc3) {
744 ret = -ENODEV;
745 dev_err(dev, "failed to get dwc3 platform device\n");
746 }
747
748 node_put:
749 of_node_put(dwc3_np);
750
751 return ret;
752 }
753
754 static struct platform_device *
dwc3_qcom_create_urs_usb_platdev(struct device * dev)755 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
756 {
757 struct fwnode_handle *fwh;
758 struct acpi_device *adev;
759 char name[8];
760 int ret;
761 int id;
762
763 /* Figure out device id */
764 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
765 if (!ret)
766 return NULL;
767
768 /* Find the child using name */
769 snprintf(name, sizeof(name), "USB%d", id);
770 fwh = fwnode_get_named_child_node(dev->fwnode, name);
771 if (!fwh)
772 return NULL;
773
774 adev = to_acpi_device_node(fwh);
775 if (!adev)
776 return NULL;
777
778 return acpi_create_platform_device(adev, NULL);
779 }
780
dwc3_qcom_probe(struct platform_device * pdev)781 static int dwc3_qcom_probe(struct platform_device *pdev)
782 {
783 struct device_node *np = pdev->dev.of_node;
784 struct device *dev = &pdev->dev;
785 struct dwc3_qcom *qcom;
786 struct resource *res, *parent_res = NULL;
787 int ret, i;
788 bool ignore_pipe_clk;
789 bool wakeup_source;
790
791 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
792 if (!qcom)
793 return -ENOMEM;
794
795 platform_set_drvdata(pdev, qcom);
796 qcom->dev = &pdev->dev;
797
798 if (has_acpi_companion(dev)) {
799 qcom->acpi_pdata = acpi_device_get_match_data(dev);
800 if (!qcom->acpi_pdata) {
801 dev_err(&pdev->dev, "no supporting ACPI device data\n");
802 return -EINVAL;
803 }
804 }
805
806 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
807 if (IS_ERR(qcom->resets)) {
808 ret = PTR_ERR(qcom->resets);
809 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
810 return ret;
811 }
812
813 ret = reset_control_assert(qcom->resets);
814 if (ret) {
815 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
816 return ret;
817 }
818
819 usleep_range(10, 1000);
820
821 ret = reset_control_deassert(qcom->resets);
822 if (ret) {
823 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
824 goto reset_assert;
825 }
826
827 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
828 if (ret) {
829 dev_err(dev, "failed to get clocks\n");
830 goto reset_assert;
831 }
832
833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834
835 if (np) {
836 parent_res = res;
837 } else {
838 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
839 if (!parent_res)
840 return -ENOMEM;
841
842 parent_res->start = res->start +
843 qcom->acpi_pdata->qscratch_base_offset;
844 parent_res->end = parent_res->start +
845 qcom->acpi_pdata->qscratch_base_size;
846
847 if (qcom->acpi_pdata->is_urs) {
848 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
849 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
850 dev_err(dev, "failed to create URS USB platdev\n");
851 if (!qcom->urs_usb)
852 return -ENODEV;
853 else
854 return PTR_ERR(qcom->urs_usb);
855 }
856 }
857 }
858
859 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
860 if (IS_ERR(qcom->qscratch_base)) {
861 ret = PTR_ERR(qcom->qscratch_base);
862 goto clk_disable;
863 }
864
865 ret = dwc3_qcom_setup_irq(pdev);
866 if (ret) {
867 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
868 goto clk_disable;
869 }
870
871 /*
872 * Disable pipe_clk requirement if specified. Used when dwc3
873 * operates without SSPHY and only HS/FS/LS modes are supported.
874 */
875 ignore_pipe_clk = device_property_read_bool(dev,
876 "qcom,select-utmi-as-pipe-clk");
877 if (ignore_pipe_clk)
878 dwc3_qcom_select_utmi_clk(qcom);
879
880 if (np)
881 ret = dwc3_qcom_of_register_core(pdev);
882 else
883 ret = dwc3_qcom_acpi_register_core(pdev);
884
885 if (ret) {
886 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
887 goto depopulate;
888 }
889
890 ret = dwc3_qcom_interconnect_init(qcom);
891 if (ret)
892 goto depopulate;
893
894 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
895
896 /* enable vbus override for device mode */
897 if (qcom->mode == USB_DR_MODE_PERIPHERAL)
898 dwc3_qcom_vbus_override_enable(qcom, true);
899
900 /* register extcon to override sw_vbus on Vbus change later */
901 ret = dwc3_qcom_register_extcon(qcom);
902 if (ret)
903 goto interconnect_exit;
904
905 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
906 device_init_wakeup(&pdev->dev, wakeup_source);
907 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
908
909 qcom->is_suspended = false;
910 pm_runtime_set_active(dev);
911 pm_runtime_enable(dev);
912 pm_runtime_forbid(dev);
913
914 return 0;
915
916 interconnect_exit:
917 dwc3_qcom_interconnect_exit(qcom);
918 depopulate:
919 if (np)
920 of_platform_depopulate(&pdev->dev);
921 else
922 platform_device_put(pdev);
923 clk_disable:
924 for (i = qcom->num_clocks - 1; i >= 0; i--) {
925 clk_disable_unprepare(qcom->clks[i]);
926 clk_put(qcom->clks[i]);
927 }
928 reset_assert:
929 reset_control_assert(qcom->resets);
930
931 return ret;
932 }
933
dwc3_qcom_remove(struct platform_device * pdev)934 static int dwc3_qcom_remove(struct platform_device *pdev)
935 {
936 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
937 struct device *dev = &pdev->dev;
938 int i;
939
940 device_remove_software_node(&qcom->dwc3->dev);
941 of_platform_depopulate(dev);
942
943 for (i = qcom->num_clocks - 1; i >= 0; i--) {
944 clk_disable_unprepare(qcom->clks[i]);
945 clk_put(qcom->clks[i]);
946 }
947 qcom->num_clocks = 0;
948
949 dwc3_qcom_interconnect_exit(qcom);
950 reset_control_assert(qcom->resets);
951
952 pm_runtime_allow(dev);
953 pm_runtime_disable(dev);
954
955 return 0;
956 }
957
dwc3_qcom_pm_suspend(struct device * dev)958 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
959 {
960 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
961 bool wakeup = device_may_wakeup(dev);
962 int ret;
963
964 ret = dwc3_qcom_suspend(qcom, wakeup);
965 if (ret)
966 return ret;
967
968 qcom->pm_suspended = true;
969
970 return 0;
971 }
972
dwc3_qcom_pm_resume(struct device * dev)973 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
974 {
975 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
976 bool wakeup = device_may_wakeup(dev);
977 int ret;
978
979 ret = dwc3_qcom_resume(qcom, wakeup);
980 if (ret)
981 return ret;
982
983 qcom->pm_suspended = false;
984
985 return 0;
986 }
987
dwc3_qcom_runtime_suspend(struct device * dev)988 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
989 {
990 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
991
992 return dwc3_qcom_suspend(qcom, true);
993 }
994
dwc3_qcom_runtime_resume(struct device * dev)995 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
996 {
997 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
998
999 return dwc3_qcom_resume(qcom, true);
1000 }
1001
1002 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
1003 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
1004 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
1005 NULL)
1006 };
1007
1008 static const struct of_device_id dwc3_qcom_of_match[] = {
1009 { .compatible = "qcom,dwc3" },
1010 { }
1011 };
1012 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
1013
1014 #ifdef CONFIG_ACPI
1015 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1016 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1017 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1018 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1019 .hs_phy_irq_index = 1,
1020 .dp_hs_phy_irq_index = 4,
1021 .dm_hs_phy_irq_index = 3,
1022 .ss_phy_irq_index = 2
1023 };
1024
1025 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1026 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1027 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1028 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1029 .hs_phy_irq_index = 1,
1030 .dp_hs_phy_irq_index = 4,
1031 .dm_hs_phy_irq_index = 3,
1032 .ss_phy_irq_index = 2,
1033 .is_urs = true,
1034 };
1035
1036 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1037 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1038 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1039 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1040 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1041 { },
1042 };
1043 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1044 #endif
1045
1046 static struct platform_driver dwc3_qcom_driver = {
1047 .probe = dwc3_qcom_probe,
1048 .remove = dwc3_qcom_remove,
1049 .driver = {
1050 .name = "dwc3-qcom",
1051 .pm = &dwc3_qcom_dev_pm_ops,
1052 .of_match_table = dwc3_qcom_of_match,
1053 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1054 },
1055 };
1056
1057 module_platform_driver(dwc3_qcom_driver);
1058
1059 MODULE_LICENSE("GPL v2");
1060 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
1061
