1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
4 *
5 * Based on msm_serial.c, which is:
6 * Copyright (C) 2007 Google, Inc.
7 * Author: Robert Love <rlove@google.com>
8 */
9
10 #include <linux/hrtimer.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/init.h>
16 #include <linux/console.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/slab.h>
22 #include <linux/clk.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/err.h>
26
27 /*
28 * UART Register offsets
29 */
30
31 #define VT8500_URTDR 0x0000 /* Transmit data */
32 #define VT8500_URRDR 0x0004 /* Receive data */
33 #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
34 #define VT8500_URLCR 0x000C /* Line control */
35 #define VT8500_URICR 0x0010 /* IrDA control */
36 #define VT8500_URIER 0x0014 /* Interrupt enable */
37 #define VT8500_URISR 0x0018 /* Interrupt status */
38 #define VT8500_URUSR 0x001c /* UART status */
39 #define VT8500_URFCR 0x0020 /* FIFO control */
40 #define VT8500_URFIDX 0x0024 /* FIFO index */
41 #define VT8500_URBKR 0x0028 /* Break signal count */
42 #define VT8500_URTOD 0x002c /* Time out divisor */
43 #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
44 #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
45
46 /*
47 * Interrupt enable and status bits
48 */
49
50 #define TXDE (1 << 0) /* Tx Data empty */
51 #define RXDF (1 << 1) /* Rx Data full */
52 #define TXFAE (1 << 2) /* Tx FIFO almost empty */
53 #define TXFE (1 << 3) /* Tx FIFO empty */
54 #define RXFAF (1 << 4) /* Rx FIFO almost full */
55 #define RXFF (1 << 5) /* Rx FIFO full */
56 #define TXUDR (1 << 6) /* Tx underrun */
57 #define RXOVER (1 << 7) /* Rx overrun */
58 #define PER (1 << 8) /* Parity error */
59 #define FER (1 << 9) /* Frame error */
60 #define TCTS (1 << 10) /* Toggle of CTS */
61 #define RXTOUT (1 << 11) /* Rx timeout */
62 #define BKDONE (1 << 12) /* Break signal done */
63 #define ERR (1 << 13) /* AHB error response */
64
65 #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
66 #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
67
68 /*
69 * Line control bits
70 */
71
72 #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
73 #define VT8500_RXEN (1 << 1) /* Enable receive logic */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
75 #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
76 #define VT8500_PARENB (1 << 4) /* Enable parity */
77 #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
78 #define VT8500_RTS (1 << 6) /* Ready to send */
79 #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
80 #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
81 #define VT8500_BREAK (1 << 9) /* Initiate break signal */
82 #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
84
85 /*
86 * Capability flags (driver-internal)
87 */
88
89 #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
90
91 #define VT8500_RECOMMENDED_CLK 12000000
92 #define VT8500_OVERSAMPLING_DIVISOR 13
93 #define VT8500_MAX_PORTS 6
94
95 struct vt8500_port {
96 struct uart_port uart;
97 char name[16];
98 struct clk *clk;
99 unsigned int clk_predivisor;
100 unsigned int ier;
101 unsigned int vt8500_uart_flags;
102 };
103
104 /*
105 * we use this variable to keep track of which ports
106 * have been allocated as we can't use pdev->id in
107 * devicetree
108 */
109 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
110
vt8500_write(struct uart_port * port,unsigned int val,unsigned int off)111 static inline void vt8500_write(struct uart_port *port, unsigned int val,
112 unsigned int off)
113 {
114 writel(val, port->membase + off);
115 }
116
vt8500_read(struct uart_port * port,unsigned int off)117 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
118 {
119 return readl(port->membase + off);
120 }
121
vt8500_stop_tx(struct uart_port * port)122 static void vt8500_stop_tx(struct uart_port *port)
123 {
124 struct vt8500_port *vt8500_port = container_of(port,
125 struct vt8500_port,
126 uart);
127
128 vt8500_port->ier &= ~TX_FIFO_INTS;
129 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
130 }
131
vt8500_stop_rx(struct uart_port * port)132 static void vt8500_stop_rx(struct uart_port *port)
133 {
134 struct vt8500_port *vt8500_port = container_of(port,
135 struct vt8500_port,
136 uart);
137
138 vt8500_port->ier &= ~RX_FIFO_INTS;
139 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
140 }
141
vt8500_enable_ms(struct uart_port * port)142 static void vt8500_enable_ms(struct uart_port *port)
143 {
144 struct vt8500_port *vt8500_port = container_of(port,
145 struct vt8500_port,
146 uart);
147
148 vt8500_port->ier |= TCTS;
149 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
150 }
151
handle_rx(struct uart_port * port)152 static void handle_rx(struct uart_port *port)
153 {
154 struct tty_port *tport = &port->state->port;
155
156 /*
157 * Handle overrun
158 */
159 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
160 port->icount.overrun++;
161 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
162 }
163
164 /* and now the main RX loop */
165 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
166 unsigned int c;
167 char flag = TTY_NORMAL;
168
169 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
170
171 /* Mask conditions we're ignorning. */
172 c &= ~port->read_status_mask;
173
174 if (c & FER) {
175 port->icount.frame++;
176 flag = TTY_FRAME;
177 } else if (c & PER) {
178 port->icount.parity++;
179 flag = TTY_PARITY;
180 }
181 port->icount.rx++;
182
183 if (!uart_handle_sysrq_char(port, c))
184 tty_insert_flip_char(tport, c, flag);
185 }
186
187 tty_flip_buffer_push(tport);
188 }
189
vt8500_tx_empty(struct uart_port * port)190 static unsigned int vt8500_tx_empty(struct uart_port *port)
191 {
192 unsigned int idx = vt8500_read(port, VT8500_URFIDX) & 0x1f;
193
194 return idx < 16 ? TIOCSER_TEMT : 0;
195 }
196
handle_tx(struct uart_port * port)197 static void handle_tx(struct uart_port *port)
198 {
199 struct circ_buf *xmit = &port->state->xmit;
200
201 if (port->x_char) {
202 writeb(port->x_char, port->membase + VT8500_TXFIFO);
203 port->icount.tx++;
204 port->x_char = 0;
205 }
206 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
207 vt8500_stop_tx(port);
208 return;
209 }
210
211 while (vt8500_tx_empty(port)) {
212 if (uart_circ_empty(xmit))
213 break;
214
215 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
216
217 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
218 port->icount.tx++;
219 }
220
221 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
222 uart_write_wakeup(port);
223
224 if (uart_circ_empty(xmit))
225 vt8500_stop_tx(port);
226 }
227
vt8500_start_tx(struct uart_port * port)228 static void vt8500_start_tx(struct uart_port *port)
229 {
230 struct vt8500_port *vt8500_port = container_of(port,
231 struct vt8500_port,
232 uart);
233
234 vt8500_port->ier &= ~TX_FIFO_INTS;
235 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
236 handle_tx(port);
237 vt8500_port->ier |= TX_FIFO_INTS;
238 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
239 }
240
handle_delta_cts(struct uart_port * port)241 static void handle_delta_cts(struct uart_port *port)
242 {
243 port->icount.cts++;
244 wake_up_interruptible(&port->state->port.delta_msr_wait);
245 }
246
vt8500_irq(int irq,void * dev_id)247 static irqreturn_t vt8500_irq(int irq, void *dev_id)
248 {
249 struct uart_port *port = dev_id;
250 unsigned long isr;
251
252 spin_lock(&port->lock);
253 isr = vt8500_read(port, VT8500_URISR);
254
255 /* Acknowledge active status bits */
256 vt8500_write(port, isr, VT8500_URISR);
257
258 if (isr & RX_FIFO_INTS)
259 handle_rx(port);
260 if (isr & TX_FIFO_INTS)
261 handle_tx(port);
262 if (isr & TCTS)
263 handle_delta_cts(port);
264
265 spin_unlock(&port->lock);
266
267 return IRQ_HANDLED;
268 }
269
vt8500_get_mctrl(struct uart_port * port)270 static unsigned int vt8500_get_mctrl(struct uart_port *port)
271 {
272 unsigned int usr;
273
274 usr = vt8500_read(port, VT8500_URUSR);
275 if (usr & (1 << 4))
276 return TIOCM_CTS;
277 else
278 return 0;
279 }
280
vt8500_set_mctrl(struct uart_port * port,unsigned int mctrl)281 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
282 {
283 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
284
285 if (mctrl & TIOCM_RTS)
286 lcr |= VT8500_RTS;
287 else
288 lcr &= ~VT8500_RTS;
289
290 vt8500_write(port, lcr, VT8500_URLCR);
291 }
292
vt8500_break_ctl(struct uart_port * port,int break_ctl)293 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
294 {
295 if (break_ctl)
296 vt8500_write(port,
297 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
298 VT8500_URLCR);
299 }
300
vt8500_set_baud_rate(struct uart_port * port,unsigned int baud)301 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
302 {
303 struct vt8500_port *vt8500_port =
304 container_of(port, struct vt8500_port, uart);
305 unsigned long div;
306 unsigned int loops = 1000;
307
308 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
309 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
310
311 /* Effective baud rate */
312 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
313
314 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
315 cpu_relax();
316
317 vt8500_write(port, div, VT8500_URDIV);
318
319 /* Break signal timing depends on baud rate, update accordingly */
320 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
321
322 return baud;
323 }
324
vt8500_startup(struct uart_port * port)325 static int vt8500_startup(struct uart_port *port)
326 {
327 struct vt8500_port *vt8500_port =
328 container_of(port, struct vt8500_port, uart);
329 int ret;
330
331 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
332 "vt8500_serial%d", port->line);
333
334 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
335 vt8500_port->name, port);
336 if (unlikely(ret))
337 return ret;
338
339 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
340
341 return 0;
342 }
343
vt8500_shutdown(struct uart_port * port)344 static void vt8500_shutdown(struct uart_port *port)
345 {
346 struct vt8500_port *vt8500_port =
347 container_of(port, struct vt8500_port, uart);
348
349 vt8500_port->ier = 0;
350
351 /* disable interrupts and FIFOs */
352 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
353 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
354 free_irq(port->irq, port);
355 }
356
vt8500_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)357 static void vt8500_set_termios(struct uart_port *port,
358 struct ktermios *termios,
359 const struct ktermios *old)
360 {
361 struct vt8500_port *vt8500_port =
362 container_of(port, struct vt8500_port, uart);
363 unsigned long flags;
364 unsigned int baud, lcr;
365 unsigned int loops = 1000;
366
367 spin_lock_irqsave(&port->lock, flags);
368
369 /* calculate and set baud rate */
370 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
371 baud = vt8500_set_baud_rate(port, baud);
372 if (tty_termios_baud_rate(termios))
373 tty_termios_encode_baud_rate(termios, baud, baud);
374
375 /* calculate parity */
376 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
377 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
378 if (termios->c_cflag & PARENB) {
379 lcr |= VT8500_PARENB;
380 termios->c_cflag &= ~CMSPAR;
381 if (termios->c_cflag & PARODD)
382 lcr |= VT8500_PARODD;
383 }
384
385 /* calculate bits per char */
386 lcr &= ~VT8500_CS8;
387 switch (termios->c_cflag & CSIZE) {
388 case CS7:
389 break;
390 case CS8:
391 default:
392 lcr |= VT8500_CS8;
393 termios->c_cflag &= ~CSIZE;
394 termios->c_cflag |= CS8;
395 break;
396 }
397
398 /* calculate stop bits */
399 lcr &= ~VT8500_CSTOPB;
400 if (termios->c_cflag & CSTOPB)
401 lcr |= VT8500_CSTOPB;
402
403 lcr &= ~VT8500_SWRTSCTS;
404 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
405 lcr |= VT8500_SWRTSCTS;
406
407 /* set parity, bits per char, and stop bit */
408 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
409
410 /* Configure status bits to ignore based on termio flags. */
411 port->read_status_mask = 0;
412 if (termios->c_iflag & IGNPAR)
413 port->read_status_mask = FER | PER;
414
415 uart_update_timeout(port, termios->c_cflag, baud);
416
417 /* Reset FIFOs */
418 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
419 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
420 && --loops)
421 cpu_relax();
422
423 /* Every possible FIFO-related interrupt */
424 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
425
426 /*
427 * CTS flow control
428 */
429 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
430 vt8500_port->ier |= TCTS;
431
432 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
433 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
434
435 spin_unlock_irqrestore(&port->lock, flags);
436 }
437
vt8500_type(struct uart_port * port)438 static const char *vt8500_type(struct uart_port *port)
439 {
440 struct vt8500_port *vt8500_port =
441 container_of(port, struct vt8500_port, uart);
442 return vt8500_port->name;
443 }
444
vt8500_release_port(struct uart_port * port)445 static void vt8500_release_port(struct uart_port *port)
446 {
447 }
448
vt8500_request_port(struct uart_port * port)449 static int vt8500_request_port(struct uart_port *port)
450 {
451 return 0;
452 }
453
vt8500_config_port(struct uart_port * port,int flags)454 static void vt8500_config_port(struct uart_port *port, int flags)
455 {
456 port->type = PORT_VT8500;
457 }
458
vt8500_verify_port(struct uart_port * port,struct serial_struct * ser)459 static int vt8500_verify_port(struct uart_port *port,
460 struct serial_struct *ser)
461 {
462 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
463 return -EINVAL;
464 if (unlikely(port->irq != ser->irq))
465 return -EINVAL;
466 return 0;
467 }
468
469 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
470 static struct uart_driver vt8500_uart_driver;
471
472 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
473
wait_for_xmitr(struct uart_port * port)474 static void wait_for_xmitr(struct uart_port *port)
475 {
476 unsigned int status, tmout = 10000;
477
478 /* Wait up to 10ms for the character(s) to be sent. */
479 do {
480 status = vt8500_read(port, VT8500_URFIDX);
481
482 if (--tmout == 0)
483 break;
484 udelay(1);
485 } while (status & 0x10);
486 }
487
vt8500_console_putchar(struct uart_port * port,unsigned char c)488 static void vt8500_console_putchar(struct uart_port *port, unsigned char c)
489 {
490 wait_for_xmitr(port);
491 writeb(c, port->membase + VT8500_TXFIFO);
492 }
493
vt8500_console_write(struct console * co,const char * s,unsigned int count)494 static void vt8500_console_write(struct console *co, const char *s,
495 unsigned int count)
496 {
497 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
498 unsigned long ier;
499
500 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
501
502 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
503 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
504
505 uart_console_write(&vt8500_port->uart, s, count,
506 vt8500_console_putchar);
507
508 /*
509 * Finally, wait for transmitter to become empty
510 * and switch back to FIFO
511 */
512 wait_for_xmitr(&vt8500_port->uart);
513 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
514 }
515
vt8500_console_setup(struct console * co,char * options)516 static int __init vt8500_console_setup(struct console *co, char *options)
517 {
518 struct vt8500_port *vt8500_port;
519 int baud = 9600;
520 int bits = 8;
521 int parity = 'n';
522 int flow = 'n';
523
524 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
525 return -ENXIO;
526
527 vt8500_port = vt8500_uart_ports[co->index];
528
529 if (!vt8500_port)
530 return -ENODEV;
531
532 if (options)
533 uart_parse_options(options, &baud, &parity, &bits, &flow);
534
535 return uart_set_options(&vt8500_port->uart,
536 co, baud, parity, bits, flow);
537 }
538
539 static struct console vt8500_console = {
540 .name = "ttyWMT",
541 .write = vt8500_console_write,
542 .device = uart_console_device,
543 .setup = vt8500_console_setup,
544 .flags = CON_PRINTBUFFER,
545 .index = -1,
546 .data = &vt8500_uart_driver,
547 };
548
549 #define VT8500_CONSOLE (&vt8500_console)
550
551 #else
552 #define VT8500_CONSOLE NULL
553 #endif
554
555 #ifdef CONFIG_CONSOLE_POLL
vt8500_get_poll_char(struct uart_port * port)556 static int vt8500_get_poll_char(struct uart_port *port)
557 {
558 unsigned int status = vt8500_read(port, VT8500_URFIDX);
559
560 if (!(status & 0x1f00))
561 return NO_POLL_CHAR;
562
563 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
564 }
565
vt8500_put_poll_char(struct uart_port * port,unsigned char c)566 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
567 {
568 unsigned int status, tmout = 10000;
569
570 do {
571 status = vt8500_read(port, VT8500_URFIDX);
572
573 if (--tmout == 0)
574 break;
575 udelay(1);
576 } while (status & 0x10);
577
578 vt8500_write(port, c, VT8500_TXFIFO);
579 }
580 #endif
581
582 static const struct uart_ops vt8500_uart_pops = {
583 .tx_empty = vt8500_tx_empty,
584 .set_mctrl = vt8500_set_mctrl,
585 .get_mctrl = vt8500_get_mctrl,
586 .stop_tx = vt8500_stop_tx,
587 .start_tx = vt8500_start_tx,
588 .stop_rx = vt8500_stop_rx,
589 .enable_ms = vt8500_enable_ms,
590 .break_ctl = vt8500_break_ctl,
591 .startup = vt8500_startup,
592 .shutdown = vt8500_shutdown,
593 .set_termios = vt8500_set_termios,
594 .type = vt8500_type,
595 .release_port = vt8500_release_port,
596 .request_port = vt8500_request_port,
597 .config_port = vt8500_config_port,
598 .verify_port = vt8500_verify_port,
599 #ifdef CONFIG_CONSOLE_POLL
600 .poll_get_char = vt8500_get_poll_char,
601 .poll_put_char = vt8500_put_poll_char,
602 #endif
603 };
604
605 static struct uart_driver vt8500_uart_driver = {
606 .owner = THIS_MODULE,
607 .driver_name = "vt8500_serial",
608 .dev_name = "ttyWMT",
609 .nr = 6,
610 .cons = VT8500_CONSOLE,
611 };
612
613 static unsigned int vt8500_flags; /* none required so far */
614 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
615
616 static const struct of_device_id wmt_dt_ids[] = {
617 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
618 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
619 {}
620 };
621
vt8500_serial_probe(struct platform_device * pdev)622 static int vt8500_serial_probe(struct platform_device *pdev)
623 {
624 struct vt8500_port *vt8500_port;
625 struct resource *mmres;
626 struct device_node *np = pdev->dev.of_node;
627 const unsigned int *flags;
628 int ret;
629 int port;
630 int irq;
631
632 flags = of_device_get_match_data(&pdev->dev);
633 if (!flags)
634 return -EINVAL;
635
636 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
637 if (!mmres)
638 return -ENODEV;
639
640 irq = platform_get_irq(pdev, 0);
641 if (irq < 0)
642 return irq;
643
644 if (np) {
645 port = of_alias_get_id(np, "serial");
646 if (port >= VT8500_MAX_PORTS)
647 port = -1;
648 } else {
649 port = -1;
650 }
651
652 if (port < 0) {
653 /* calculate the port id */
654 port = find_first_zero_bit(vt8500_ports_in_use,
655 VT8500_MAX_PORTS);
656 }
657
658 if (port >= VT8500_MAX_PORTS)
659 return -ENODEV;
660
661 /* reserve the port id */
662 if (test_and_set_bit(port, vt8500_ports_in_use)) {
663 /* port already in use - shouldn't really happen */
664 return -EBUSY;
665 }
666
667 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
668 GFP_KERNEL);
669 if (!vt8500_port)
670 return -ENOMEM;
671
672 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
673 if (IS_ERR(vt8500_port->uart.membase))
674 return PTR_ERR(vt8500_port->uart.membase);
675
676 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
677 if (IS_ERR(vt8500_port->clk)) {
678 dev_err(&pdev->dev, "failed to get clock\n");
679 return -EINVAL;
680 }
681
682 ret = clk_prepare_enable(vt8500_port->clk);
683 if (ret) {
684 dev_err(&pdev->dev, "failed to enable clock\n");
685 return ret;
686 }
687
688 vt8500_port->vt8500_uart_flags = *flags;
689 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
690 clk_get_rate(vt8500_port->clk),
691 VT8500_RECOMMENDED_CLK
692 );
693 vt8500_port->uart.type = PORT_VT8500;
694 vt8500_port->uart.iotype = UPIO_MEM;
695 vt8500_port->uart.mapbase = mmres->start;
696 vt8500_port->uart.irq = irq;
697 vt8500_port->uart.fifosize = 16;
698 vt8500_port->uart.ops = &vt8500_uart_pops;
699 vt8500_port->uart.line = port;
700 vt8500_port->uart.dev = &pdev->dev;
701 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
702 vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
703
704 /* Serial core uses the magic "16" everywhere - adjust for it */
705 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
706 vt8500_port->clk_predivisor /
707 VT8500_OVERSAMPLING_DIVISOR;
708
709 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
710 "VT8500 UART%d", pdev->id);
711
712 vt8500_uart_ports[port] = vt8500_port;
713
714 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
715
716 platform_set_drvdata(pdev, vt8500_port);
717
718 return 0;
719 }
720
721 static struct platform_driver vt8500_platform_driver = {
722 .probe = vt8500_serial_probe,
723 .driver = {
724 .name = "vt8500_serial",
725 .of_match_table = wmt_dt_ids,
726 .suppress_bind_attrs = true,
727 },
728 };
729
vt8500_serial_init(void)730 static int __init vt8500_serial_init(void)
731 {
732 int ret;
733
734 ret = uart_register_driver(&vt8500_uart_driver);
735 if (unlikely(ret))
736 return ret;
737
738 ret = platform_driver_register(&vt8500_platform_driver);
739
740 if (unlikely(ret))
741 uart_unregister_driver(&vt8500_uart_driver);
742
743 return ret;
744 }
745 device_initcall(vt8500_serial_init);
746
