1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
4 *
5 * Based on msm_serial.c, which is:
6 * Copyright (C) 2007 Google, Inc.
7 * Author: Robert Love <rlove@google.com>
8 */
9
10 #if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 # define SUPPORT_SYSRQ
12 #endif
13
14 #include <linux/hrtimer.h>
15 #include <linux/delay.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/err.h>
30
31 /*
32 * UART Register offsets
33 */
34
35 #define VT8500_URTDR 0x0000 /* Transmit data */
36 #define VT8500_URRDR 0x0004 /* Receive data */
37 #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
38 #define VT8500_URLCR 0x000C /* Line control */
39 #define VT8500_URICR 0x0010 /* IrDA control */
40 #define VT8500_URIER 0x0014 /* Interrupt enable */
41 #define VT8500_URISR 0x0018 /* Interrupt status */
42 #define VT8500_URUSR 0x001c /* UART status */
43 #define VT8500_URFCR 0x0020 /* FIFO control */
44 #define VT8500_URFIDX 0x0024 /* FIFO index */
45 #define VT8500_URBKR 0x0028 /* Break signal count */
46 #define VT8500_URTOD 0x002c /* Time out divisor */
47 #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
48 #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
49
50 /*
51 * Interrupt enable and status bits
52 */
53
54 #define TXDE (1 << 0) /* Tx Data empty */
55 #define RXDF (1 << 1) /* Rx Data full */
56 #define TXFAE (1 << 2) /* Tx FIFO almost empty */
57 #define TXFE (1 << 3) /* Tx FIFO empty */
58 #define RXFAF (1 << 4) /* Rx FIFO almost full */
59 #define RXFF (1 << 5) /* Rx FIFO full */
60 #define TXUDR (1 << 6) /* Tx underrun */
61 #define RXOVER (1 << 7) /* Rx overrun */
62 #define PER (1 << 8) /* Parity error */
63 #define FER (1 << 9) /* Frame error */
64 #define TCTS (1 << 10) /* Toggle of CTS */
65 #define RXTOUT (1 << 11) /* Rx timeout */
66 #define BKDONE (1 << 12) /* Break signal done */
67 #define ERR (1 << 13) /* AHB error response */
68
69 #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
70 #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
71
72 /*
73 * Line control bits
74 */
75
76 #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
77 #define VT8500_RXEN (1 << 1) /* Enable receive logic */
78 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
79 #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
80 #define VT8500_PARENB (1 << 4) /* Enable parity */
81 #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
82 #define VT8500_RTS (1 << 6) /* Ready to send */
83 #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
84 #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
85 #define VT8500_BREAK (1 << 9) /* Initiate break signal */
86 #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
87 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
88
89 /*
90 * Capability flags (driver-internal)
91 */
92
93 #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
94
95 #define VT8500_RECOMMENDED_CLK 12000000
96 #define VT8500_OVERSAMPLING_DIVISOR 13
97 #define VT8500_MAX_PORTS 6
98
99 struct vt8500_port {
100 struct uart_port uart;
101 char name[16];
102 struct clk *clk;
103 unsigned int clk_predivisor;
104 unsigned int ier;
105 unsigned int vt8500_uart_flags;
106 };
107
108 /*
109 * we use this variable to keep track of which ports
110 * have been allocated as we can't use pdev->id in
111 * devicetree
112 */
113 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
114
vt8500_write(struct uart_port * port,unsigned int val,unsigned int off)115 static inline void vt8500_write(struct uart_port *port, unsigned int val,
116 unsigned int off)
117 {
118 writel(val, port->membase + off);
119 }
120
vt8500_read(struct uart_port * port,unsigned int off)121 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
122 {
123 return readl(port->membase + off);
124 }
125
vt8500_stop_tx(struct uart_port * port)126 static void vt8500_stop_tx(struct uart_port *port)
127 {
128 struct vt8500_port *vt8500_port = container_of(port,
129 struct vt8500_port,
130 uart);
131
132 vt8500_port->ier &= ~TX_FIFO_INTS;
133 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
134 }
135
vt8500_stop_rx(struct uart_port * port)136 static void vt8500_stop_rx(struct uart_port *port)
137 {
138 struct vt8500_port *vt8500_port = container_of(port,
139 struct vt8500_port,
140 uart);
141
142 vt8500_port->ier &= ~RX_FIFO_INTS;
143 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
144 }
145
vt8500_enable_ms(struct uart_port * port)146 static void vt8500_enable_ms(struct uart_port *port)
147 {
148 struct vt8500_port *vt8500_port = container_of(port,
149 struct vt8500_port,
150 uart);
151
152 vt8500_port->ier |= TCTS;
153 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
154 }
155
handle_rx(struct uart_port * port)156 static void handle_rx(struct uart_port *port)
157 {
158 struct tty_port *tport = &port->state->port;
159
160 /*
161 * Handle overrun
162 */
163 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
164 port->icount.overrun++;
165 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
166 }
167
168 /* and now the main RX loop */
169 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
170 unsigned int c;
171 char flag = TTY_NORMAL;
172
173 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
174
175 /* Mask conditions we're ignorning. */
176 c &= ~port->read_status_mask;
177
178 if (c & FER) {
179 port->icount.frame++;
180 flag = TTY_FRAME;
181 } else if (c & PER) {
182 port->icount.parity++;
183 flag = TTY_PARITY;
184 }
185 port->icount.rx++;
186
187 if (!uart_handle_sysrq_char(port, c))
188 tty_insert_flip_char(tport, c, flag);
189 }
190
191 spin_unlock(&port->lock);
192 tty_flip_buffer_push(tport);
193 spin_lock(&port->lock);
194 }
195
handle_tx(struct uart_port * port)196 static void handle_tx(struct uart_port *port)
197 {
198 struct circ_buf *xmit = &port->state->xmit;
199
200 if (port->x_char) {
201 writeb(port->x_char, port->membase + VT8500_TXFIFO);
202 port->icount.tx++;
203 port->x_char = 0;
204 }
205 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
206 vt8500_stop_tx(port);
207 return;
208 }
209
210 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
211 if (uart_circ_empty(xmit))
212 break;
213
214 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
215
216 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
217 port->icount.tx++;
218 }
219
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(port);
222
223 if (uart_circ_empty(xmit))
224 vt8500_stop_tx(port);
225 }
226
vt8500_start_tx(struct uart_port * port)227 static void vt8500_start_tx(struct uart_port *port)
228 {
229 struct vt8500_port *vt8500_port = container_of(port,
230 struct vt8500_port,
231 uart);
232
233 vt8500_port->ier &= ~TX_FIFO_INTS;
234 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
235 handle_tx(port);
236 vt8500_port->ier |= TX_FIFO_INTS;
237 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
238 }
239
handle_delta_cts(struct uart_port * port)240 static void handle_delta_cts(struct uart_port *port)
241 {
242 port->icount.cts++;
243 wake_up_interruptible(&port->state->port.delta_msr_wait);
244 }
245
vt8500_irq(int irq,void * dev_id)246 static irqreturn_t vt8500_irq(int irq, void *dev_id)
247 {
248 struct uart_port *port = dev_id;
249 unsigned long isr;
250
251 spin_lock(&port->lock);
252 isr = vt8500_read(port, VT8500_URISR);
253
254 /* Acknowledge active status bits */
255 vt8500_write(port, isr, VT8500_URISR);
256
257 if (isr & RX_FIFO_INTS)
258 handle_rx(port);
259 if (isr & TX_FIFO_INTS)
260 handle_tx(port);
261 if (isr & TCTS)
262 handle_delta_cts(port);
263
264 spin_unlock(&port->lock);
265
266 return IRQ_HANDLED;
267 }
268
vt8500_tx_empty(struct uart_port * port)269 static unsigned int vt8500_tx_empty(struct uart_port *port)
270 {
271 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
272 TIOCSER_TEMT : 0;
273 }
274
vt8500_get_mctrl(struct uart_port * port)275 static unsigned int vt8500_get_mctrl(struct uart_port *port)
276 {
277 unsigned int usr;
278
279 usr = vt8500_read(port, VT8500_URUSR);
280 if (usr & (1 << 4))
281 return TIOCM_CTS;
282 else
283 return 0;
284 }
285
vt8500_set_mctrl(struct uart_port * port,unsigned int mctrl)286 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
289
290 if (mctrl & TIOCM_RTS)
291 lcr |= VT8500_RTS;
292 else
293 lcr &= ~VT8500_RTS;
294
295 vt8500_write(port, lcr, VT8500_URLCR);
296 }
297
vt8500_break_ctl(struct uart_port * port,int break_ctl)298 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
299 {
300 if (break_ctl)
301 vt8500_write(port,
302 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
303 VT8500_URLCR);
304 }
305
vt8500_set_baud_rate(struct uart_port * port,unsigned int baud)306 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
307 {
308 struct vt8500_port *vt8500_port =
309 container_of(port, struct vt8500_port, uart);
310 unsigned long div;
311 unsigned int loops = 1000;
312
313 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
314 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
315
316 /* Effective baud rate */
317 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
318
319 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
320 cpu_relax();
321
322 vt8500_write(port, div, VT8500_URDIV);
323
324 /* Break signal timing depends on baud rate, update accordingly */
325 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
326
327 return baud;
328 }
329
vt8500_startup(struct uart_port * port)330 static int vt8500_startup(struct uart_port *port)
331 {
332 struct vt8500_port *vt8500_port =
333 container_of(port, struct vt8500_port, uart);
334 int ret;
335
336 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
337 "vt8500_serial%d", port->line);
338
339 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
340 vt8500_port->name, port);
341 if (unlikely(ret))
342 return ret;
343
344 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
345
346 return 0;
347 }
348
vt8500_shutdown(struct uart_port * port)349 static void vt8500_shutdown(struct uart_port *port)
350 {
351 struct vt8500_port *vt8500_port =
352 container_of(port, struct vt8500_port, uart);
353
354 vt8500_port->ier = 0;
355
356 /* disable interrupts and FIFOs */
357 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
358 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
359 free_irq(port->irq, port);
360 }
361
vt8500_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)362 static void vt8500_set_termios(struct uart_port *port,
363 struct ktermios *termios,
364 struct ktermios *old)
365 {
366 struct vt8500_port *vt8500_port =
367 container_of(port, struct vt8500_port, uart);
368 unsigned long flags;
369 unsigned int baud, lcr;
370 unsigned int loops = 1000;
371
372 spin_lock_irqsave(&port->lock, flags);
373
374 /* calculate and set baud rate */
375 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
376 baud = vt8500_set_baud_rate(port, baud);
377 if (tty_termios_baud_rate(termios))
378 tty_termios_encode_baud_rate(termios, baud, baud);
379
380 /* calculate parity */
381 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
382 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
383 if (termios->c_cflag & PARENB) {
384 lcr |= VT8500_PARENB;
385 termios->c_cflag &= ~CMSPAR;
386 if (termios->c_cflag & PARODD)
387 lcr |= VT8500_PARODD;
388 }
389
390 /* calculate bits per char */
391 lcr &= ~VT8500_CS8;
392 switch (termios->c_cflag & CSIZE) {
393 case CS7:
394 break;
395 case CS8:
396 default:
397 lcr |= VT8500_CS8;
398 termios->c_cflag &= ~CSIZE;
399 termios->c_cflag |= CS8;
400 break;
401 }
402
403 /* calculate stop bits */
404 lcr &= ~VT8500_CSTOPB;
405 if (termios->c_cflag & CSTOPB)
406 lcr |= VT8500_CSTOPB;
407
408 lcr &= ~VT8500_SWRTSCTS;
409 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
410 lcr |= VT8500_SWRTSCTS;
411
412 /* set parity, bits per char, and stop bit */
413 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
414
415 /* Configure status bits to ignore based on termio flags. */
416 port->read_status_mask = 0;
417 if (termios->c_iflag & IGNPAR)
418 port->read_status_mask = FER | PER;
419
420 uart_update_timeout(port, termios->c_cflag, baud);
421
422 /* Reset FIFOs */
423 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
424 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
425 && --loops)
426 cpu_relax();
427
428 /* Every possible FIFO-related interrupt */
429 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
430
431 /*
432 * CTS flow control
433 */
434 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
435 vt8500_port->ier |= TCTS;
436
437 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
438 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
439
440 spin_unlock_irqrestore(&port->lock, flags);
441 }
442
vt8500_type(struct uart_port * port)443 static const char *vt8500_type(struct uart_port *port)
444 {
445 struct vt8500_port *vt8500_port =
446 container_of(port, struct vt8500_port, uart);
447 return vt8500_port->name;
448 }
449
vt8500_release_port(struct uart_port * port)450 static void vt8500_release_port(struct uart_port *port)
451 {
452 }
453
vt8500_request_port(struct uart_port * port)454 static int vt8500_request_port(struct uart_port *port)
455 {
456 return 0;
457 }
458
vt8500_config_port(struct uart_port * port,int flags)459 static void vt8500_config_port(struct uart_port *port, int flags)
460 {
461 port->type = PORT_VT8500;
462 }
463
vt8500_verify_port(struct uart_port * port,struct serial_struct * ser)464 static int vt8500_verify_port(struct uart_port *port,
465 struct serial_struct *ser)
466 {
467 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
468 return -EINVAL;
469 if (unlikely(port->irq != ser->irq))
470 return -EINVAL;
471 return 0;
472 }
473
474 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
475 static struct uart_driver vt8500_uart_driver;
476
477 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
478
wait_for_xmitr(struct uart_port * port)479 static void wait_for_xmitr(struct uart_port *port)
480 {
481 unsigned int status, tmout = 10000;
482
483 /* Wait up to 10ms for the character(s) to be sent. */
484 do {
485 status = vt8500_read(port, VT8500_URFIDX);
486
487 if (--tmout == 0)
488 break;
489 udelay(1);
490 } while (status & 0x10);
491 }
492
vt8500_console_putchar(struct uart_port * port,int c)493 static void vt8500_console_putchar(struct uart_port *port, int c)
494 {
495 wait_for_xmitr(port);
496 writeb(c, port->membase + VT8500_TXFIFO);
497 }
498
vt8500_console_write(struct console * co,const char * s,unsigned int count)499 static void vt8500_console_write(struct console *co, const char *s,
500 unsigned int count)
501 {
502 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
503 unsigned long ier;
504
505 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
506
507 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
508 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
509
510 uart_console_write(&vt8500_port->uart, s, count,
511 vt8500_console_putchar);
512
513 /*
514 * Finally, wait for transmitter to become empty
515 * and switch back to FIFO
516 */
517 wait_for_xmitr(&vt8500_port->uart);
518 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
519 }
520
vt8500_console_setup(struct console * co,char * options)521 static int __init vt8500_console_setup(struct console *co, char *options)
522 {
523 struct vt8500_port *vt8500_port;
524 int baud = 9600;
525 int bits = 8;
526 int parity = 'n';
527 int flow = 'n';
528
529 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
530 return -ENXIO;
531
532 vt8500_port = vt8500_uart_ports[co->index];
533
534 if (!vt8500_port)
535 return -ENODEV;
536
537 if (options)
538 uart_parse_options(options, &baud, &parity, &bits, &flow);
539
540 return uart_set_options(&vt8500_port->uart,
541 co, baud, parity, bits, flow);
542 }
543
544 static struct console vt8500_console = {
545 .name = "ttyWMT",
546 .write = vt8500_console_write,
547 .device = uart_console_device,
548 .setup = vt8500_console_setup,
549 .flags = CON_PRINTBUFFER,
550 .index = -1,
551 .data = &vt8500_uart_driver,
552 };
553
554 #define VT8500_CONSOLE (&vt8500_console)
555
556 #else
557 #define VT8500_CONSOLE NULL
558 #endif
559
560 #ifdef CONFIG_CONSOLE_POLL
vt8500_get_poll_char(struct uart_port * port)561 static int vt8500_get_poll_char(struct uart_port *port)
562 {
563 unsigned int status = vt8500_read(port, VT8500_URFIDX);
564
565 if (!(status & 0x1f00))
566 return NO_POLL_CHAR;
567
568 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
569 }
570
vt8500_put_poll_char(struct uart_port * port,unsigned char c)571 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
572 {
573 unsigned int status, tmout = 10000;
574
575 do {
576 status = vt8500_read(port, VT8500_URFIDX);
577
578 if (--tmout == 0)
579 break;
580 udelay(1);
581 } while (status & 0x10);
582
583 vt8500_write(port, c, VT8500_TXFIFO);
584 }
585 #endif
586
587 static const struct uart_ops vt8500_uart_pops = {
588 .tx_empty = vt8500_tx_empty,
589 .set_mctrl = vt8500_set_mctrl,
590 .get_mctrl = vt8500_get_mctrl,
591 .stop_tx = vt8500_stop_tx,
592 .start_tx = vt8500_start_tx,
593 .stop_rx = vt8500_stop_rx,
594 .enable_ms = vt8500_enable_ms,
595 .break_ctl = vt8500_break_ctl,
596 .startup = vt8500_startup,
597 .shutdown = vt8500_shutdown,
598 .set_termios = vt8500_set_termios,
599 .type = vt8500_type,
600 .release_port = vt8500_release_port,
601 .request_port = vt8500_request_port,
602 .config_port = vt8500_config_port,
603 .verify_port = vt8500_verify_port,
604 #ifdef CONFIG_CONSOLE_POLL
605 .poll_get_char = vt8500_get_poll_char,
606 .poll_put_char = vt8500_put_poll_char,
607 #endif
608 };
609
610 static struct uart_driver vt8500_uart_driver = {
611 .owner = THIS_MODULE,
612 .driver_name = "vt8500_serial",
613 .dev_name = "ttyWMT",
614 .nr = 6,
615 .cons = VT8500_CONSOLE,
616 };
617
618 static unsigned int vt8500_flags; /* none required so far */
619 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
620
621 static const struct of_device_id wmt_dt_ids[] = {
622 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
623 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
624 {}
625 };
626
vt8500_serial_probe(struct platform_device * pdev)627 static int vt8500_serial_probe(struct platform_device *pdev)
628 {
629 struct vt8500_port *vt8500_port;
630 struct resource *mmres, *irqres;
631 struct device_node *np = pdev->dev.of_node;
632 const struct of_device_id *match;
633 const unsigned int *flags;
634 int ret;
635 int port;
636
637 match = of_match_device(wmt_dt_ids, &pdev->dev);
638 if (!match)
639 return -EINVAL;
640
641 flags = match->data;
642
643 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
644 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
645 if (!mmres || !irqres)
646 return -ENODEV;
647
648 if (np) {
649 port = of_alias_get_id(np, "serial");
650 if (port >= VT8500_MAX_PORTS)
651 port = -1;
652 } else {
653 port = -1;
654 }
655
656 if (port < 0) {
657 /* calculate the port id */
658 port = find_first_zero_bit(vt8500_ports_in_use,
659 VT8500_MAX_PORTS);
660 }
661
662 if (port >= VT8500_MAX_PORTS)
663 return -ENODEV;
664
665 /* reserve the port id */
666 if (test_and_set_bit(port, vt8500_ports_in_use)) {
667 /* port already in use - shouldn't really happen */
668 return -EBUSY;
669 }
670
671 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
672 GFP_KERNEL);
673 if (!vt8500_port)
674 return -ENOMEM;
675
676 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
677 if (IS_ERR(vt8500_port->uart.membase))
678 return PTR_ERR(vt8500_port->uart.membase);
679
680 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
681 if (IS_ERR(vt8500_port->clk)) {
682 dev_err(&pdev->dev, "failed to get clock\n");
683 return -EINVAL;
684 }
685
686 ret = clk_prepare_enable(vt8500_port->clk);
687 if (ret) {
688 dev_err(&pdev->dev, "failed to enable clock\n");
689 return ret;
690 }
691
692 vt8500_port->vt8500_uart_flags = *flags;
693 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
694 clk_get_rate(vt8500_port->clk),
695 VT8500_RECOMMENDED_CLK
696 );
697 vt8500_port->uart.type = PORT_VT8500;
698 vt8500_port->uart.iotype = UPIO_MEM;
699 vt8500_port->uart.mapbase = mmres->start;
700 vt8500_port->uart.irq = irqres->start;
701 vt8500_port->uart.fifosize = 16;
702 vt8500_port->uart.ops = &vt8500_uart_pops;
703 vt8500_port->uart.line = port;
704 vt8500_port->uart.dev = &pdev->dev;
705 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
706
707 /* Serial core uses the magic "16" everywhere - adjust for it */
708 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
709 vt8500_port->clk_predivisor /
710 VT8500_OVERSAMPLING_DIVISOR;
711
712 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
713 "VT8500 UART%d", pdev->id);
714
715 vt8500_uart_ports[port] = vt8500_port;
716
717 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
718
719 platform_set_drvdata(pdev, vt8500_port);
720
721 return 0;
722 }
723
724 static struct platform_driver vt8500_platform_driver = {
725 .probe = vt8500_serial_probe,
726 .driver = {
727 .name = "vt8500_serial",
728 .of_match_table = wmt_dt_ids,
729 .suppress_bind_attrs = true,
730 },
731 };
732
vt8500_serial_init(void)733 static int __init vt8500_serial_init(void)
734 {
735 int ret;
736
737 ret = uart_register_driver(&vt8500_uart_driver);
738 if (unlikely(ret))
739 return ret;
740
741 ret = platform_driver_register(&vt8500_platform_driver);
742
743 if (unlikely(ret))
744 uart_unregister_driver(&vt8500_uart_driver);
745
746 return ret;
747 }
748 device_initcall(vt8500_serial_init);
749
