1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale QUICC Engine UART device driver
4 *
5 * Author: Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2007 Freescale Semiconductor, Inc.
8 *
9 * This driver adds support for UART devices via Freescale's QUICC Engine
10 * found on some Freescale SOCs.
11 *
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
14 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
15 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
16 * (e.g. "11" for 1.1).
17 */
18
19 #include <linux/module.h>
20 #include <linux/serial.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/io.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/dma-mapping.h>
30
31 #include <linux/fs_uart_pd.h>
32 #include <soc/fsl/qe/ucc_slow.h>
33
34 #include <linux/firmware.h>
35 #include <soc/fsl/cpm.h>
36
37 #ifdef CONFIG_PPC32
38 #include <asm/reg.h> /* mfspr, SPRN_SVR */
39 #endif
40
41 /*
42 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
43 * but Soft-UART is a hack and we want to keep everything related to it in
44 * this file.
45 */
46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
47
48 /*
49 * soft_uart is 1 if we need to use Soft-UART mode
50 */
51 static int soft_uart;
52 /*
53 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
54 */
55 static int firmware_loaded;
56
57 /* Enable this macro to configure all serial ports in internal loopback
58 mode */
59 /* #define LOOPBACK */
60
61 /* The major and minor device numbers are defined in
62 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
63 * UART, we have major number 204 and minor numbers 46 - 49, which are the
64 * same as for the CPM2. This decision was made because no Freescale part
65 * has both a CPM and a QE.
66 */
67 #define SERIAL_QE_MAJOR 204
68 #define SERIAL_QE_MINOR 46
69
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
71 #define UCC_MAX_UART 4
72
73 /* The number of buffer descriptors for receiving characters. */
74 #define RX_NUM_FIFO 4
75
76 /* The number of buffer descriptors for transmitting characters. */
77 #define TX_NUM_FIFO 4
78
79 /* The maximum size of the character buffer for a single RX BD. */
80 #define RX_BUF_SIZE 32
81
82 /* The maximum size of the character buffer for a single TX BD. */
83 #define TX_BUF_SIZE 32
84
85 /*
86 * The number of jiffies to wait after receiving a close command before the
87 * device is actually closed. This allows the last few characters to be
88 * sent over the wire.
89 */
90 #define UCC_WAIT_CLOSING 100
91
92 struct ucc_uart_pram {
93 struct ucc_slow_pram common;
94 u8 res1[8]; /* reserved */
95 __be16 maxidl; /* Maximum idle chars */
96 __be16 idlc; /* temp idle counter */
97 __be16 brkcr; /* Break count register */
98 __be16 parec; /* receive parity error counter */
99 __be16 frmec; /* receive framing error counter */
100 __be16 nosec; /* receive noise counter */
101 __be16 brkec; /* receive break condition counter */
102 __be16 brkln; /* last received break length */
103 __be16 uaddr[2]; /* UART address character 1 & 2 */
104 __be16 rtemp; /* Temp storage */
105 __be16 toseq; /* Transmit out of sequence char */
106 __be16 cchars[8]; /* control characters 1-8 */
107 __be16 rccm; /* receive control character mask */
108 __be16 rccr; /* receive control character register */
109 __be16 rlbc; /* receive last break character */
110 __be16 res2; /* reserved */
111 __be32 res3; /* reserved, should be cleared */
112 u8 res4; /* reserved, should be cleared */
113 u8 res5[3]; /* reserved, should be cleared */
114 __be32 res6; /* reserved, should be cleared */
115 __be32 res7; /* reserved, should be cleared */
116 __be32 res8; /* reserved, should be cleared */
117 __be32 res9; /* reserved, should be cleared */
118 __be32 res10; /* reserved, should be cleared */
119 __be32 res11; /* reserved, should be cleared */
120 __be32 res12; /* reserved, should be cleared */
121 __be32 res13; /* reserved, should be cleared */
122 /* The rest is for Soft-UART only */
123 __be16 supsmr; /* 0x90, Shadow UPSMR */
124 __be16 res92; /* 0x92, reserved, initialize to 0 */
125 __be32 rx_state; /* 0x94, RX state, initialize to 0 */
126 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
127 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
128 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
129 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
130 u8 res14[0xBC - 0x9F]; /* reserved */
131 __be32 dump_ptr; /* 0xBC, Dump pointer */
132 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
133 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
134 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
135 __be16 tx_state; /* 0xC6, TX state */
136 u8 res15[0xD0 - 0xC8]; /* reserved */
137 __be32 resD0; /* 0xD0, reserved, initialize to 0 */
138 u8 resD4; /* 0xD4, reserved, initialize to 0 */
139 __be16 resD5; /* 0xD5, reserved, initialize to 0 */
140 } __attribute__ ((packed));
141
142 /* SUPSMR definitions, for Soft-UART only */
143 #define UCC_UART_SUPSMR_SL 0x8000
144 #define UCC_UART_SUPSMR_RPM_MASK 0x6000
145 #define UCC_UART_SUPSMR_RPM_ODD 0x0000
146 #define UCC_UART_SUPSMR_RPM_LOW 0x2000
147 #define UCC_UART_SUPSMR_RPM_EVEN 0x4000
148 #define UCC_UART_SUPSMR_RPM_HIGH 0x6000
149 #define UCC_UART_SUPSMR_PEN 0x1000
150 #define UCC_UART_SUPSMR_TPM_MASK 0x0C00
151 #define UCC_UART_SUPSMR_TPM_ODD 0x0000
152 #define UCC_UART_SUPSMR_TPM_LOW 0x0400
153 #define UCC_UART_SUPSMR_TPM_EVEN 0x0800
154 #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
155 #define UCC_UART_SUPSMR_FRZ 0x0100
156 #define UCC_UART_SUPSMR_UM_MASK 0x00c0
157 #define UCC_UART_SUPSMR_UM_NORMAL 0x0000
158 #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
159 #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
160 #define UCC_UART_SUPSMR_CL_MASK 0x0030
161 #define UCC_UART_SUPSMR_CL_8 0x0030
162 #define UCC_UART_SUPSMR_CL_7 0x0020
163 #define UCC_UART_SUPSMR_CL_6 0x0010
164 #define UCC_UART_SUPSMR_CL_5 0x0000
165
166 #define UCC_UART_TX_STATE_AHDLC 0x00
167 #define UCC_UART_TX_STATE_UART 0x01
168 #define UCC_UART_TX_STATE_X1 0x00
169 #define UCC_UART_TX_STATE_X16 0x80
170
171 #define UCC_UART_PRAM_ALIGNMENT 0x100
172
173 #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
174 #define NUM_CONTROL_CHARS 8
175
176 /* Private per-port data structure */
177 struct uart_qe_port {
178 struct uart_port port;
179 struct ucc_slow __iomem *uccp;
180 struct ucc_uart_pram __iomem *uccup;
181 struct ucc_slow_info us_info;
182 struct ucc_slow_private *us_private;
183 struct device_node *np;
184 unsigned int ucc_num; /* First ucc is 0, not 1 */
185
186 u16 rx_nrfifos;
187 u16 rx_fifosize;
188 u16 tx_nrfifos;
189 u16 tx_fifosize;
190 int wait_closing;
191 u32 flags;
192 struct qe_bd *rx_bd_base;
193 struct qe_bd *rx_cur;
194 struct qe_bd *tx_bd_base;
195 struct qe_bd *tx_cur;
196 unsigned char *tx_buf;
197 unsigned char *rx_buf;
198 void *bd_virt; /* virtual address of the BD buffers */
199 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
200 unsigned int bd_size; /* size of BD buffer space */
201 };
202
203 static struct uart_driver ucc_uart_driver = {
204 .owner = THIS_MODULE,
205 .driver_name = "ucc_uart",
206 .dev_name = "ttyQE",
207 .major = SERIAL_QE_MAJOR,
208 .minor = SERIAL_QE_MINOR,
209 .nr = UCC_MAX_UART,
210 };
211
212 /*
213 * Virtual to physical address translation.
214 *
215 * Given the virtual address for a character buffer, this function returns
216 * the physical (DMA) equivalent.
217 */
cpu2qe_addr(void * addr,struct uart_qe_port * qe_port)218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
219 {
220 if (likely((addr >= qe_port->bd_virt)) &&
221 (addr < (qe_port->bd_virt + qe_port->bd_size)))
222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
223
224 /* something nasty happened */
225 printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
226 BUG();
227 return 0;
228 }
229
230 /*
231 * Physical to virtual address translation.
232 *
233 * Given the physical (DMA) address for a character buffer, this function
234 * returns the virtual equivalent.
235 */
qe2cpu_addr(dma_addr_t addr,struct uart_qe_port * qe_port)236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
237 {
238 /* sanity check */
239 if (likely((addr >= qe_port->bd_dma_addr) &&
240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
242
243 /* something nasty happened */
244 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
245 BUG();
246 return NULL;
247 }
248
249 /*
250 * Return 1 if the QE is done transmitting all buffers for this port
251 *
252 * This function scans each BD in sequence. If we find a BD that is not
253 * ready (READY=1), then we return 0 indicating that the QE is still sending
254 * data. If we reach the last BD (WRAP=1), then we know we've scanned
255 * the entire list, and all BDs are done.
256 */
qe_uart_tx_empty(struct uart_port * port)257 static unsigned int qe_uart_tx_empty(struct uart_port *port)
258 {
259 struct uart_qe_port *qe_port =
260 container_of(port, struct uart_qe_port, port);
261 struct qe_bd *bdp = qe_port->tx_bd_base;
262
263 while (1) {
264 if (ioread16be(&bdp->status) & BD_SC_READY)
265 /* This BD is not done, so return "not done" */
266 return 0;
267
268 if (ioread16be(&bdp->status) & BD_SC_WRAP)
269 /*
270 * This BD is done and it's the last one, so return
271 * "done"
272 */
273 return 1;
274
275 bdp++;
276 }
277 }
278
279 /*
280 * Set the modem control lines
281 *
282 * Although the QE can control the modem control lines (e.g. CTS), we
283 * don't need that support. This function must exist, however, otherwise
284 * the kernel will panic.
285 */
qe_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)286 static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 }
289
290 /*
291 * Get the current modem control line status
292 *
293 * Although the QE can control the modem control lines (e.g. CTS), this
294 * driver currently doesn't support that, so we always return Carrier
295 * Detect, Data Set Ready, and Clear To Send.
296 */
qe_uart_get_mctrl(struct uart_port * port)297 static unsigned int qe_uart_get_mctrl(struct uart_port *port)
298 {
299 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
300 }
301
302 /*
303 * Disable the transmit interrupt.
304 *
305 * Although this function is called "stop_tx", it does not actually stop
306 * transmission of data. Instead, it tells the QE to not generate an
307 * interrupt when the UCC is finished sending characters.
308 */
qe_uart_stop_tx(struct uart_port * port)309 static void qe_uart_stop_tx(struct uart_port *port)
310 {
311 struct uart_qe_port *qe_port =
312 container_of(port, struct uart_qe_port, port);
313
314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
315 }
316
317 /*
318 * Transmit as many characters to the HW as possible.
319 *
320 * This function will attempt to stuff of all the characters from the
321 * kernel's transmit buffer into TX BDs.
322 *
323 * A return value of non-zero indicates that it successfully stuffed all
324 * characters from the kernel buffer.
325 *
326 * A return value of zero indicates that there are still characters in the
327 * kernel's buffer that have not been transmitted, but there are no more BDs
328 * available. This function should be called again after a BD has been made
329 * available.
330 */
qe_uart_tx_pump(struct uart_qe_port * qe_port)331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
332 {
333 struct qe_bd *bdp;
334 unsigned char *p;
335 unsigned int count;
336 struct uart_port *port = &qe_port->port;
337 struct circ_buf *xmit = &port->state->xmit;
338
339 /* Handle xon/xoff */
340 if (port->x_char) {
341 /* Pick next descriptor and fill from buffer */
342 bdp = qe_port->tx_cur;
343
344 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
345
346 *p++ = port->x_char;
347 iowrite16be(1, &bdp->length);
348 qe_setbits_be16(&bdp->status, BD_SC_READY);
349 /* Get next BD. */
350 if (ioread16be(&bdp->status) & BD_SC_WRAP)
351 bdp = qe_port->tx_bd_base;
352 else
353 bdp++;
354 qe_port->tx_cur = bdp;
355
356 port->icount.tx++;
357 port->x_char = 0;
358 return 1;
359 }
360
361 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
362 qe_uart_stop_tx(port);
363 return 0;
364 }
365
366 /* Pick next descriptor and fill from buffer */
367 bdp = qe_port->tx_cur;
368
369 while (!(ioread16be(&bdp->status) & BD_SC_READY) &&
370 (xmit->tail != xmit->head)) {
371 count = 0;
372 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
373 while (count < qe_port->tx_fifosize) {
374 *p++ = xmit->buf[xmit->tail];
375 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
376 port->icount.tx++;
377 count++;
378 if (xmit->head == xmit->tail)
379 break;
380 }
381
382 iowrite16be(count, &bdp->length);
383 qe_setbits_be16(&bdp->status, BD_SC_READY);
384
385 /* Get next BD. */
386 if (ioread16be(&bdp->status) & BD_SC_WRAP)
387 bdp = qe_port->tx_bd_base;
388 else
389 bdp++;
390 }
391 qe_port->tx_cur = bdp;
392
393 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
394 uart_write_wakeup(port);
395
396 if (uart_circ_empty(xmit)) {
397 /* The kernel buffer is empty, so turn off TX interrupts. We
398 don't need to be told when the QE is finished transmitting
399 the data. */
400 qe_uart_stop_tx(port);
401 return 0;
402 }
403
404 return 1;
405 }
406
407 /*
408 * Start transmitting data
409 *
410 * This function will start transmitting any available data, if the port
411 * isn't already transmitting data.
412 */
qe_uart_start_tx(struct uart_port * port)413 static void qe_uart_start_tx(struct uart_port *port)
414 {
415 struct uart_qe_port *qe_port =
416 container_of(port, struct uart_qe_port, port);
417
418 /* If we currently are transmitting, then just return */
419 if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
420 return;
421
422 /* Otherwise, pump the port and start transmission */
423 if (qe_uart_tx_pump(qe_port))
424 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
425 }
426
427 /*
428 * Stop transmitting data
429 */
qe_uart_stop_rx(struct uart_port * port)430 static void qe_uart_stop_rx(struct uart_port *port)
431 {
432 struct uart_qe_port *qe_port =
433 container_of(port, struct uart_qe_port, port);
434
435 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
436 }
437
438 /* Start or stop sending break signal
439 *
440 * This function controls the sending of a break signal. If break_state=1,
441 * then we start sending a break signal. If break_state=0, then we stop
442 * sending the break signal.
443 */
qe_uart_break_ctl(struct uart_port * port,int break_state)444 static void qe_uart_break_ctl(struct uart_port *port, int break_state)
445 {
446 struct uart_qe_port *qe_port =
447 container_of(port, struct uart_qe_port, port);
448
449 if (break_state)
450 ucc_slow_stop_tx(qe_port->us_private);
451 else
452 ucc_slow_restart_tx(qe_port->us_private);
453 }
454
455 /* ISR helper function for receiving character.
456 *
457 * This function is called by the ISR to handling receiving characters
458 */
qe_uart_int_rx(struct uart_qe_port * qe_port)459 static void qe_uart_int_rx(struct uart_qe_port *qe_port)
460 {
461 int i;
462 unsigned char ch, *cp;
463 struct uart_port *port = &qe_port->port;
464 struct tty_port *tport = &port->state->port;
465 struct qe_bd *bdp;
466 u16 status;
467 unsigned int flg;
468
469 /* Just loop through the closed BDs and copy the characters into
470 * the buffer.
471 */
472 bdp = qe_port->rx_cur;
473 while (1) {
474 status = ioread16be(&bdp->status);
475
476 /* If this one is empty, then we assume we've read them all */
477 if (status & BD_SC_EMPTY)
478 break;
479
480 /* get number of characters, and check space in RX buffer */
481 i = ioread16be(&bdp->length);
482
483 /* If we don't have enough room in RX buffer for the entire BD,
484 * then we try later, which will be the next RX interrupt.
485 */
486 if (tty_buffer_request_room(tport, i) < i) {
487 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
488 return;
489 }
490
491 /* get pointer */
492 cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
493
494 /* loop through the buffer */
495 while (i-- > 0) {
496 ch = *cp++;
497 port->icount.rx++;
498 flg = TTY_NORMAL;
499
500 if (!i && status &
501 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
502 goto handle_error;
503 if (uart_handle_sysrq_char(port, ch))
504 continue;
505
506 error_return:
507 tty_insert_flip_char(tport, ch, flg);
508
509 }
510
511 /* This BD is ready to be used again. Clear status. get next */
512 qe_clrsetbits_be16(&bdp->status,
513 BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
514 BD_SC_EMPTY);
515 if (ioread16be(&bdp->status) & BD_SC_WRAP)
516 bdp = qe_port->rx_bd_base;
517 else
518 bdp++;
519
520 }
521
522 /* Write back buffer pointer */
523 qe_port->rx_cur = bdp;
524
525 /* Activate BH processing */
526 tty_flip_buffer_push(tport);
527
528 return;
529
530 /* Error processing */
531
532 handle_error:
533 /* Statistics */
534 if (status & BD_SC_BR)
535 port->icount.brk++;
536 if (status & BD_SC_PR)
537 port->icount.parity++;
538 if (status & BD_SC_FR)
539 port->icount.frame++;
540 if (status & BD_SC_OV)
541 port->icount.overrun++;
542
543 /* Mask out ignored conditions */
544 status &= port->read_status_mask;
545
546 /* Handle the remaining ones */
547 if (status & BD_SC_BR)
548 flg = TTY_BREAK;
549 else if (status & BD_SC_PR)
550 flg = TTY_PARITY;
551 else if (status & BD_SC_FR)
552 flg = TTY_FRAME;
553
554 /* Overrun does not affect the current character ! */
555 if (status & BD_SC_OV)
556 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
557 port->sysrq = 0;
558 goto error_return;
559 }
560
561 /* Interrupt handler
562 *
563 * This interrupt handler is called after a BD is processed.
564 */
qe_uart_int(int irq,void * data)565 static irqreturn_t qe_uart_int(int irq, void *data)
566 {
567 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
568 struct ucc_slow __iomem *uccp = qe_port->uccp;
569 u16 events;
570
571 /* Clear the interrupts */
572 events = ioread16be(&uccp->ucce);
573 iowrite16be(events, &uccp->ucce);
574
575 if (events & UCC_UART_UCCE_BRKE)
576 uart_handle_break(&qe_port->port);
577
578 if (events & UCC_UART_UCCE_RX)
579 qe_uart_int_rx(qe_port);
580
581 if (events & UCC_UART_UCCE_TX)
582 qe_uart_tx_pump(qe_port);
583
584 return events ? IRQ_HANDLED : IRQ_NONE;
585 }
586
587 /* Initialize buffer descriptors
588 *
589 * This function initializes all of the RX and TX buffer descriptors.
590 */
qe_uart_initbd(struct uart_qe_port * qe_port)591 static void qe_uart_initbd(struct uart_qe_port *qe_port)
592 {
593 int i;
594 void *bd_virt;
595 struct qe_bd *bdp;
596
597 /* Set the physical address of the host memory buffers in the buffer
598 * descriptors, and the virtual address for us to work with.
599 */
600 bd_virt = qe_port->bd_virt;
601 bdp = qe_port->rx_bd_base;
602 qe_port->rx_cur = qe_port->rx_bd_base;
603 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
604 iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
605 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
606 iowrite16be(0, &bdp->length);
607 bd_virt += qe_port->rx_fifosize;
608 bdp++;
609 }
610
611 /* */
612 iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
613 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
614 iowrite16be(0, &bdp->length);
615
616 /* Set the physical address of the host memory
617 * buffers in the buffer descriptors, and the
618 * virtual address for us to work with.
619 */
620 bd_virt = qe_port->bd_virt +
621 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
622 qe_port->tx_cur = qe_port->tx_bd_base;
623 bdp = qe_port->tx_bd_base;
624 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
625 iowrite16be(BD_SC_INTRPT, &bdp->status);
626 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
627 iowrite16be(0, &bdp->length);
628 bd_virt += qe_port->tx_fifosize;
629 bdp++;
630 }
631
632 /* Loopback requires the preamble bit to be set on the first TX BD */
633 #ifdef LOOPBACK
634 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
635 #endif
636
637 iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
638 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
639 iowrite16be(0, &bdp->length);
640 }
641
642 /*
643 * Initialize a UCC for UART.
644 *
645 * This function configures a given UCC to be used as a UART device. Basic
646 * UCC initialization is handled in qe_uart_request_port(). This function
647 * does all the UART-specific stuff.
648 */
qe_uart_init_ucc(struct uart_qe_port * qe_port)649 static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
650 {
651 u32 cecr_subblock;
652 struct ucc_slow __iomem *uccp = qe_port->uccp;
653 struct ucc_uart_pram *uccup = qe_port->uccup;
654
655 unsigned int i;
656
657 /* First, disable TX and RX in the UCC */
658 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
659
660 /* Program the UCC UART parameter RAM */
661 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
662 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
663 iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
664 iowrite16be(0x10, &uccup->maxidl);
665 iowrite16be(1, &uccup->brkcr);
666 iowrite16be(0, &uccup->parec);
667 iowrite16be(0, &uccup->frmec);
668 iowrite16be(0, &uccup->nosec);
669 iowrite16be(0, &uccup->brkec);
670 iowrite16be(0, &uccup->uaddr[0]);
671 iowrite16be(0, &uccup->uaddr[1]);
672 iowrite16be(0, &uccup->toseq);
673 for (i = 0; i < 8; i++)
674 iowrite16be(0xC000, &uccup->cchars[i]);
675 iowrite16be(0xc0ff, &uccup->rccm);
676
677 /* Configure the GUMR registers for UART */
678 if (soft_uart) {
679 /* Soft-UART requires a 1X multiplier for TX */
680 qe_clrsetbits_be32(&uccp->gumr_l,
681 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
682 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
683
684 qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
685 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
686 } else {
687 qe_clrsetbits_be32(&uccp->gumr_l,
688 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
689 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
690
691 qe_clrsetbits_be32(&uccp->gumr_h,
692 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
693 UCC_SLOW_GUMR_H_RFW);
694 }
695
696 #ifdef LOOPBACK
697 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
698 UCC_SLOW_GUMR_L_DIAG_LOOP);
699 qe_clrsetbits_be32(&uccp->gumr_h,
700 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
701 UCC_SLOW_GUMR_H_CDS);
702 #endif
703
704 /* Disable rx interrupts and clear all pending events. */
705 iowrite16be(0, &uccp->uccm);
706 iowrite16be(0xffff, &uccp->ucce);
707 iowrite16be(0x7e7e, &uccp->udsr);
708
709 /* Initialize UPSMR */
710 iowrite16be(0, &uccp->upsmr);
711
712 if (soft_uart) {
713 iowrite16be(0x30, &uccup->supsmr);
714 iowrite16be(0, &uccup->res92);
715 iowrite32be(0, &uccup->rx_state);
716 iowrite32be(0, &uccup->rx_cnt);
717 iowrite8(0, &uccup->rx_bitmark);
718 iowrite8(10, &uccup->rx_length);
719 iowrite32be(0x4000, &uccup->dump_ptr);
720 iowrite8(0, &uccup->rx_temp_dlst_qe);
721 iowrite32be(0, &uccup->rx_frame_rem);
722 iowrite8(0, &uccup->rx_frame_rem_size);
723 /* Soft-UART requires TX to be 1X */
724 iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
725 &uccup->tx_mode);
726 iowrite16be(0, &uccup->tx_state);
727 iowrite8(0, &uccup->resD4);
728 iowrite16be(0, &uccup->resD5);
729
730 /* Set UART mode.
731 * Enable receive and transmit.
732 */
733
734 /* From the microcode errata:
735 * 1.GUMR_L register, set mode=0010 (QMC).
736 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
737 * 3.Set GUMR_H[19:20] (Transparent mode)
738 * 4.Clear GUMR_H[26] (RFW)
739 * ...
740 * 6.Receiver must use 16x over sampling
741 */
742 qe_clrsetbits_be32(&uccp->gumr_l,
743 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
744 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
745
746 qe_clrsetbits_be32(&uccp->gumr_h,
747 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
748 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
749
750 #ifdef LOOPBACK
751 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
752 UCC_SLOW_GUMR_L_DIAG_LOOP);
753 qe_clrbits_be32(&uccp->gumr_h,
754 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
755 #endif
756
757 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
758 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
759 QE_CR_PROTOCOL_UNSPECIFIED, 0);
760 } else {
761 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
762 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
763 QE_CR_PROTOCOL_UART, 0);
764 }
765 }
766
767 /*
768 * Initialize the port.
769 */
qe_uart_startup(struct uart_port * port)770 static int qe_uart_startup(struct uart_port *port)
771 {
772 struct uart_qe_port *qe_port =
773 container_of(port, struct uart_qe_port, port);
774 int ret;
775
776 /*
777 * If we're using Soft-UART mode, then we need to make sure the
778 * firmware has been uploaded first.
779 */
780 if (soft_uart && !firmware_loaded) {
781 dev_err(port->dev, "Soft-UART firmware not uploaded\n");
782 return -ENODEV;
783 }
784
785 qe_uart_initbd(qe_port);
786 qe_uart_init_ucc(qe_port);
787
788 /* Install interrupt handler. */
789 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
790 qe_port);
791 if (ret) {
792 dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
793 return ret;
794 }
795
796 /* Startup rx-int */
797 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
798 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
799
800 return 0;
801 }
802
803 /*
804 * Shutdown the port.
805 */
qe_uart_shutdown(struct uart_port * port)806 static void qe_uart_shutdown(struct uart_port *port)
807 {
808 struct uart_qe_port *qe_port =
809 container_of(port, struct uart_qe_port, port);
810 struct ucc_slow __iomem *uccp = qe_port->uccp;
811 unsigned int timeout = 20;
812
813 /* Disable RX and TX */
814
815 /* Wait for all the BDs marked sent */
816 while (!qe_uart_tx_empty(port)) {
817 if (!--timeout) {
818 dev_warn(port->dev, "shutdown timeout\n");
819 break;
820 }
821 set_current_state(TASK_UNINTERRUPTIBLE);
822 schedule_timeout(2);
823 }
824
825 if (qe_port->wait_closing) {
826 /* Wait a bit longer */
827 set_current_state(TASK_UNINTERRUPTIBLE);
828 schedule_timeout(qe_port->wait_closing);
829 }
830
831 /* Stop uarts */
832 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
833 qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
834
835 /* Shut them really down and reinit buffer descriptors */
836 ucc_slow_graceful_stop_tx(qe_port->us_private);
837 qe_uart_initbd(qe_port);
838
839 free_irq(port->irq, qe_port);
840 }
841
842 /*
843 * Set the serial port parameters.
844 */
qe_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)845 static void qe_uart_set_termios(struct uart_port *port,
846 struct ktermios *termios,
847 const struct ktermios *old)
848 {
849 struct uart_qe_port *qe_port =
850 container_of(port, struct uart_qe_port, port);
851 struct ucc_slow __iomem *uccp = qe_port->uccp;
852 unsigned int baud;
853 unsigned long flags;
854 u16 upsmr = ioread16be(&uccp->upsmr);
855 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
856 u16 supsmr = ioread16be(&uccup->supsmr);
857
858 /* byte size */
859 upsmr &= UCC_UART_UPSMR_CL_MASK;
860 supsmr &= UCC_UART_SUPSMR_CL_MASK;
861
862 switch (termios->c_cflag & CSIZE) {
863 case CS5:
864 upsmr |= UCC_UART_UPSMR_CL_5;
865 supsmr |= UCC_UART_SUPSMR_CL_5;
866 break;
867 case CS6:
868 upsmr |= UCC_UART_UPSMR_CL_6;
869 supsmr |= UCC_UART_SUPSMR_CL_6;
870 break;
871 case CS7:
872 upsmr |= UCC_UART_UPSMR_CL_7;
873 supsmr |= UCC_UART_SUPSMR_CL_7;
874 break;
875 default: /* case CS8 */
876 upsmr |= UCC_UART_UPSMR_CL_8;
877 supsmr |= UCC_UART_SUPSMR_CL_8;
878 break;
879 }
880
881 /* If CSTOPB is set, we want two stop bits */
882 if (termios->c_cflag & CSTOPB) {
883 upsmr |= UCC_UART_UPSMR_SL;
884 supsmr |= UCC_UART_SUPSMR_SL;
885 }
886
887 if (termios->c_cflag & PARENB) {
888 upsmr |= UCC_UART_UPSMR_PEN;
889 supsmr |= UCC_UART_SUPSMR_PEN;
890
891 if (!(termios->c_cflag & PARODD)) {
892 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
893 UCC_UART_UPSMR_TPM_MASK);
894 upsmr |= UCC_UART_UPSMR_RPM_EVEN |
895 UCC_UART_UPSMR_TPM_EVEN;
896 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
897 UCC_UART_SUPSMR_TPM_MASK);
898 supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
899 UCC_UART_SUPSMR_TPM_EVEN;
900 }
901 }
902
903 /*
904 * Set up parity check flag
905 */
906 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
907 if (termios->c_iflag & INPCK)
908 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
909 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
910 port->read_status_mask |= BD_SC_BR;
911
912 /*
913 * Characters to ignore
914 */
915 port->ignore_status_mask = 0;
916 if (termios->c_iflag & IGNPAR)
917 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
918 if (termios->c_iflag & IGNBRK) {
919 port->ignore_status_mask |= BD_SC_BR;
920 /*
921 * If we're ignore parity and break indicators, ignore
922 * overruns too. (For real raw support).
923 */
924 if (termios->c_iflag & IGNPAR)
925 port->ignore_status_mask |= BD_SC_OV;
926 }
927 /*
928 * !!! ignore all characters if CREAD is not set
929 */
930 if ((termios->c_cflag & CREAD) == 0)
931 port->read_status_mask &= ~BD_SC_EMPTY;
932
933 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
934
935 /* Do we really need a spinlock here? */
936 spin_lock_irqsave(&port->lock, flags);
937
938 /* Update the per-port timeout. */
939 uart_update_timeout(port, termios->c_cflag, baud);
940
941 iowrite16be(upsmr, &uccp->upsmr);
942 if (soft_uart) {
943 iowrite16be(supsmr, &uccup->supsmr);
944 iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length);
945
946 /* Soft-UART requires a 1X multiplier for TX */
947 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
948 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
949 } else {
950 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
951 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
952 }
953
954 spin_unlock_irqrestore(&port->lock, flags);
955 }
956
957 /*
958 * Return a pointer to a string that describes what kind of port this is.
959 */
qe_uart_type(struct uart_port * port)960 static const char *qe_uart_type(struct uart_port *port)
961 {
962 return "QE";
963 }
964
965 /*
966 * Allocate any memory and I/O resources required by the port.
967 */
qe_uart_request_port(struct uart_port * port)968 static int qe_uart_request_port(struct uart_port *port)
969 {
970 int ret;
971 struct uart_qe_port *qe_port =
972 container_of(port, struct uart_qe_port, port);
973 struct ucc_slow_info *us_info = &qe_port->us_info;
974 struct ucc_slow_private *uccs;
975 unsigned int rx_size, tx_size;
976 void *bd_virt;
977 dma_addr_t bd_dma_addr = 0;
978
979 ret = ucc_slow_init(us_info, &uccs);
980 if (ret) {
981 dev_err(port->dev, "could not initialize UCC%u\n",
982 qe_port->ucc_num);
983 return ret;
984 }
985
986 qe_port->us_private = uccs;
987 qe_port->uccp = uccs->us_regs;
988 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
989 qe_port->rx_bd_base = uccs->rx_bd;
990 qe_port->tx_bd_base = uccs->tx_bd;
991
992 /*
993 * Allocate the transmit and receive data buffers.
994 */
995
996 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
997 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
998
999 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1000 GFP_KERNEL);
1001 if (!bd_virt) {
1002 dev_err(port->dev, "could not allocate buffer descriptors\n");
1003 return -ENOMEM;
1004 }
1005
1006 qe_port->bd_virt = bd_virt;
1007 qe_port->bd_dma_addr = bd_dma_addr;
1008 qe_port->bd_size = rx_size + tx_size;
1009
1010 qe_port->rx_buf = bd_virt;
1011 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1012
1013 return 0;
1014 }
1015
1016 /*
1017 * Configure the port.
1018 *
1019 * We say we're a CPM-type port because that's mostly true. Once the device
1020 * is configured, this driver operates almost identically to the CPM serial
1021 * driver.
1022 */
qe_uart_config_port(struct uart_port * port,int flags)1023 static void qe_uart_config_port(struct uart_port *port, int flags)
1024 {
1025 if (flags & UART_CONFIG_TYPE) {
1026 port->type = PORT_CPM;
1027 qe_uart_request_port(port);
1028 }
1029 }
1030
1031 /*
1032 * Release any memory and I/O resources that were allocated in
1033 * qe_uart_request_port().
1034 */
qe_uart_release_port(struct uart_port * port)1035 static void qe_uart_release_port(struct uart_port *port)
1036 {
1037 struct uart_qe_port *qe_port =
1038 container_of(port, struct uart_qe_port, port);
1039 struct ucc_slow_private *uccs = qe_port->us_private;
1040
1041 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1042 qe_port->bd_dma_addr);
1043
1044 ucc_slow_free(uccs);
1045 }
1046
1047 /*
1048 * Verify that the data in serial_struct is suitable for this device.
1049 */
qe_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1050 static int qe_uart_verify_port(struct uart_port *port,
1051 struct serial_struct *ser)
1052 {
1053 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1054 return -EINVAL;
1055
1056 if (ser->irq < 0 || ser->irq >= nr_irqs)
1057 return -EINVAL;
1058
1059 if (ser->baud_base < 9600)
1060 return -EINVAL;
1061
1062 return 0;
1063 }
1064 /* UART operations
1065 *
1066 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1067 */
1068 static const struct uart_ops qe_uart_pops = {
1069 .tx_empty = qe_uart_tx_empty,
1070 .set_mctrl = qe_uart_set_mctrl,
1071 .get_mctrl = qe_uart_get_mctrl,
1072 .stop_tx = qe_uart_stop_tx,
1073 .start_tx = qe_uart_start_tx,
1074 .stop_rx = qe_uart_stop_rx,
1075 .break_ctl = qe_uart_break_ctl,
1076 .startup = qe_uart_startup,
1077 .shutdown = qe_uart_shutdown,
1078 .set_termios = qe_uart_set_termios,
1079 .type = qe_uart_type,
1080 .release_port = qe_uart_release_port,
1081 .request_port = qe_uart_request_port,
1082 .config_port = qe_uart_config_port,
1083 .verify_port = qe_uart_verify_port,
1084 };
1085
1086
1087 #ifdef CONFIG_PPC32
1088 /*
1089 * Obtain the SOC model number and revision level
1090 *
1091 * This function parses the device tree to obtain the SOC model. It then
1092 * reads the SVR register to the revision.
1093 *
1094 * The device tree stores the SOC model two different ways.
1095 *
1096 * The new way is:
1097 *
1098 * cpu@0 {
1099 * compatible = "PowerPC,8323";
1100 * device_type = "cpu";
1101 * ...
1102 *
1103 *
1104 * The old way is:
1105 * PowerPC,8323@0 {
1106 * device_type = "cpu";
1107 * ...
1108 *
1109 * This code first checks the new way, and then the old way.
1110 */
soc_info(unsigned int * rev_h,unsigned int * rev_l)1111 static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1112 {
1113 struct device_node *np;
1114 const char *soc_string;
1115 unsigned int svr;
1116 unsigned int soc;
1117
1118 /* Find the CPU node */
1119 np = of_find_node_by_type(NULL, "cpu");
1120 if (!np)
1121 return 0;
1122 /* Find the compatible property */
1123 soc_string = of_get_property(np, "compatible", NULL);
1124 if (!soc_string)
1125 /* No compatible property, so try the name. */
1126 soc_string = np->name;
1127
1128 of_node_put(np);
1129
1130 /* Extract the SOC number from the "PowerPC," string */
1131 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1132 return 0;
1133
1134 /* Get the revision from the SVR */
1135 svr = mfspr(SPRN_SVR);
1136 *rev_h = (svr >> 4) & 0xf;
1137 *rev_l = svr & 0xf;
1138
1139 return soc;
1140 }
1141
1142 /*
1143 * requst_firmware_nowait() callback function
1144 *
1145 * This function is called by the kernel when a firmware is made available,
1146 * or if it times out waiting for the firmware.
1147 */
uart_firmware_cont(const struct firmware * fw,void * context)1148 static void uart_firmware_cont(const struct firmware *fw, void *context)
1149 {
1150 struct qe_firmware *firmware;
1151 struct device *dev = context;
1152 int ret;
1153
1154 if (!fw) {
1155 dev_err(dev, "firmware not found\n");
1156 return;
1157 }
1158
1159 firmware = (struct qe_firmware *) fw->data;
1160
1161 if (firmware->header.length != fw->size) {
1162 dev_err(dev, "invalid firmware\n");
1163 goto out;
1164 }
1165
1166 ret = qe_upload_firmware(firmware);
1167 if (ret) {
1168 dev_err(dev, "could not load firmware\n");
1169 goto out;
1170 }
1171
1172 firmware_loaded = 1;
1173 out:
1174 release_firmware(fw);
1175 }
1176
soft_uart_init(struct platform_device * ofdev)1177 static int soft_uart_init(struct platform_device *ofdev)
1178 {
1179 struct device_node *np = ofdev->dev.of_node;
1180 struct qe_firmware_info *qe_fw_info;
1181 int ret;
1182
1183 if (of_find_property(np, "soft-uart", NULL)) {
1184 dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1185 soft_uart = 1;
1186 } else {
1187 return 0;
1188 }
1189
1190 qe_fw_info = qe_get_firmware_info();
1191
1192 /* Check if the firmware has been uploaded. */
1193 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1194 firmware_loaded = 1;
1195 } else {
1196 char filename[32];
1197 unsigned int soc;
1198 unsigned int rev_h;
1199 unsigned int rev_l;
1200
1201 soc = soc_info(&rev_h, &rev_l);
1202 if (!soc) {
1203 dev_err(&ofdev->dev, "unknown CPU model\n");
1204 return -ENXIO;
1205 }
1206 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1207 soc, rev_h, rev_l);
1208
1209 dev_info(&ofdev->dev, "waiting for firmware %s\n",
1210 filename);
1211
1212 /*
1213 * We call request_firmware_nowait instead of
1214 * request_firmware so that the driver can load and
1215 * initialize the ports without holding up the rest of
1216 * the kernel. If hotplug support is enabled in the
1217 * kernel, then we use it.
1218 */
1219 ret = request_firmware_nowait(THIS_MODULE,
1220 FW_ACTION_UEVENT, filename, &ofdev->dev,
1221 GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1222 if (ret) {
1223 dev_err(&ofdev->dev,
1224 "could not load firmware %s\n",
1225 filename);
1226 return ret;
1227 }
1228 }
1229 return 0;
1230 }
1231
1232 #else /* !CONFIG_PPC32 */
1233
soft_uart_init(struct platform_device * ofdev)1234 static int soft_uart_init(struct platform_device *ofdev)
1235 {
1236 return 0;
1237 }
1238
1239 #endif
1240
1241
ucc_uart_probe(struct platform_device * ofdev)1242 static int ucc_uart_probe(struct platform_device *ofdev)
1243 {
1244 struct device_node *np = ofdev->dev.of_node;
1245 const char *sprop; /* String OF properties */
1246 struct uart_qe_port *qe_port = NULL;
1247 struct resource res;
1248 u32 val;
1249 int ret;
1250
1251 /*
1252 * Determine if we need Soft-UART mode
1253 */
1254 ret = soft_uart_init(ofdev);
1255 if (ret)
1256 return ret;
1257
1258 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1259 if (!qe_port) {
1260 dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1261 return -ENOMEM;
1262 }
1263
1264 /* Search for IRQ and mapbase */
1265 ret = of_address_to_resource(np, 0, &res);
1266 if (ret) {
1267 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1268 goto out_free;
1269 }
1270 if (!res.start) {
1271 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1272 ret = -EINVAL;
1273 goto out_free;
1274 }
1275 qe_port->port.mapbase = res.start;
1276
1277 /* Get the UCC number (device ID) */
1278 /* UCCs are numbered 1-7 */
1279 if (of_property_read_u32(np, "cell-index", &val)) {
1280 if (of_property_read_u32(np, "device-id", &val)) {
1281 dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
1282 ret = -EINVAL;
1283 goto out_free;
1284 }
1285 }
1286
1287 if (val < 1 || val > UCC_MAX_NUM) {
1288 dev_err(&ofdev->dev, "no support for UCC%u\n", val);
1289 ret = -ENODEV;
1290 goto out_free;
1291 }
1292 qe_port->ucc_num = val - 1;
1293
1294 /*
1295 * In the future, we should not require the BRG to be specified in the
1296 * device tree. If no clock-source is specified, then just pick a BRG
1297 * to use. This requires a new QE library function that manages BRG
1298 * assignments.
1299 */
1300
1301 sprop = of_get_property(np, "rx-clock-name", NULL);
1302 if (!sprop) {
1303 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1304 ret = -ENODEV;
1305 goto out_free;
1306 }
1307
1308 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1309 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1310 (qe_port->us_info.rx_clock > QE_BRG16)) {
1311 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1312 ret = -ENODEV;
1313 goto out_free;
1314 }
1315
1316 #ifdef LOOPBACK
1317 /* In internal loopback mode, TX and RX must use the same clock */
1318 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1319 #else
1320 sprop = of_get_property(np, "tx-clock-name", NULL);
1321 if (!sprop) {
1322 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1323 ret = -ENODEV;
1324 goto out_free;
1325 }
1326 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1327 #endif
1328 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1329 (qe_port->us_info.tx_clock > QE_BRG16)) {
1330 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1331 ret = -ENODEV;
1332 goto out_free;
1333 }
1334
1335 /* Get the port number, numbered 0-3 */
1336 if (of_property_read_u32(np, "port-number", &val)) {
1337 dev_err(&ofdev->dev, "missing port-number in device tree\n");
1338 ret = -EINVAL;
1339 goto out_free;
1340 }
1341 qe_port->port.line = val;
1342 if (qe_port->port.line >= UCC_MAX_UART) {
1343 dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1344 UCC_MAX_UART - 1);
1345 ret = -EINVAL;
1346 goto out_free;
1347 }
1348
1349 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1350 if (qe_port->port.irq == 0) {
1351 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1352 qe_port->ucc_num + 1);
1353 ret = -EINVAL;
1354 goto out_free;
1355 }
1356
1357 /*
1358 * Newer device trees have an "fsl,qe" compatible property for the QE
1359 * node, but we still need to support older device trees.
1360 */
1361 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1362 if (!np) {
1363 np = of_find_node_by_type(NULL, "qe");
1364 if (!np) {
1365 dev_err(&ofdev->dev, "could not find 'qe' node\n");
1366 ret = -EINVAL;
1367 goto out_free;
1368 }
1369 }
1370
1371 if (of_property_read_u32(np, "brg-frequency", &val)) {
1372 dev_err(&ofdev->dev,
1373 "missing brg-frequency in device tree\n");
1374 ret = -EINVAL;
1375 goto out_np;
1376 }
1377
1378 if (val)
1379 qe_port->port.uartclk = val;
1380 else {
1381 if (!IS_ENABLED(CONFIG_PPC32)) {
1382 dev_err(&ofdev->dev,
1383 "invalid brg-frequency in device tree\n");
1384 ret = -EINVAL;
1385 goto out_np;
1386 }
1387
1388 /*
1389 * Older versions of U-Boot do not initialize the brg-frequency
1390 * property, so in this case we assume the BRG frequency is
1391 * half the QE bus frequency.
1392 */
1393 if (of_property_read_u32(np, "bus-frequency", &val)) {
1394 dev_err(&ofdev->dev,
1395 "missing QE bus-frequency in device tree\n");
1396 ret = -EINVAL;
1397 goto out_np;
1398 }
1399 if (val)
1400 qe_port->port.uartclk = val / 2;
1401 else {
1402 dev_err(&ofdev->dev,
1403 "invalid QE bus-frequency in device tree\n");
1404 ret = -EINVAL;
1405 goto out_np;
1406 }
1407 }
1408
1409 spin_lock_init(&qe_port->port.lock);
1410 qe_port->np = np;
1411 qe_port->port.dev = &ofdev->dev;
1412 qe_port->port.ops = &qe_uart_pops;
1413 qe_port->port.iotype = UPIO_MEM;
1414
1415 qe_port->tx_nrfifos = TX_NUM_FIFO;
1416 qe_port->tx_fifosize = TX_BUF_SIZE;
1417 qe_port->rx_nrfifos = RX_NUM_FIFO;
1418 qe_port->rx_fifosize = RX_BUF_SIZE;
1419
1420 qe_port->wait_closing = UCC_WAIT_CLOSING;
1421 qe_port->port.fifosize = 512;
1422 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1423
1424 qe_port->us_info.ucc_num = qe_port->ucc_num;
1425 qe_port->us_info.regs = (phys_addr_t) res.start;
1426 qe_port->us_info.irq = qe_port->port.irq;
1427
1428 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1429 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1430
1431 /* Make sure ucc_slow_init() initializes both TX and RX */
1432 qe_port->us_info.init_tx = 1;
1433 qe_port->us_info.init_rx = 1;
1434
1435 /* Add the port to the uart sub-system. This will cause
1436 * qe_uart_config_port() to be called, so the us_info structure must
1437 * be initialized.
1438 */
1439 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1440 if (ret) {
1441 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1442 qe_port->port.line);
1443 goto out_np;
1444 }
1445
1446 platform_set_drvdata(ofdev, qe_port);
1447
1448 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1449 qe_port->ucc_num + 1, qe_port->port.line);
1450
1451 /* Display the mknod command for this device */
1452 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1453 qe_port->port.line, SERIAL_QE_MAJOR,
1454 SERIAL_QE_MINOR + qe_port->port.line);
1455
1456 return 0;
1457 out_np:
1458 of_node_put(np);
1459 out_free:
1460 kfree(qe_port);
1461 return ret;
1462 }
1463
ucc_uart_remove(struct platform_device * ofdev)1464 static int ucc_uart_remove(struct platform_device *ofdev)
1465 {
1466 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1467
1468 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1469
1470 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1471
1472 kfree(qe_port);
1473
1474 return 0;
1475 }
1476
1477 static const struct of_device_id ucc_uart_match[] = {
1478 {
1479 .type = "serial",
1480 .compatible = "ucc_uart",
1481 },
1482 {
1483 .compatible = "fsl,t1040-ucc-uart",
1484 },
1485 {},
1486 };
1487 MODULE_DEVICE_TABLE(of, ucc_uart_match);
1488
1489 static struct platform_driver ucc_uart_of_driver = {
1490 .driver = {
1491 .name = "ucc_uart",
1492 .of_match_table = ucc_uart_match,
1493 },
1494 .probe = ucc_uart_probe,
1495 .remove = ucc_uart_remove,
1496 };
1497
ucc_uart_init(void)1498 static int __init ucc_uart_init(void)
1499 {
1500 int ret;
1501
1502 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1503 #ifdef LOOPBACK
1504 printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1505 #endif
1506
1507 ret = uart_register_driver(&ucc_uart_driver);
1508 if (ret) {
1509 printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1510 return ret;
1511 }
1512
1513 ret = platform_driver_register(&ucc_uart_of_driver);
1514 if (ret) {
1515 printk(KERN_ERR
1516 "ucc-uart: could not register platform driver\n");
1517 uart_unregister_driver(&ucc_uart_driver);
1518 }
1519
1520 return ret;
1521 }
1522
ucc_uart_exit(void)1523 static void __exit ucc_uart_exit(void)
1524 {
1525 printk(KERN_INFO
1526 "Freescale QUICC Engine UART device driver unloading\n");
1527
1528 platform_driver_unregister(&ucc_uart_of_driver);
1529 uart_unregister_driver(&ucc_uart_driver);
1530 }
1531
1532 module_init(ucc_uart_init);
1533 module_exit(ucc_uart_exit);
1534
1535 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1536 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1537 MODULE_LICENSE("GPL v2");
1538 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1539
1540
