1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * serial_tegra.c
4 *
5 * High-speed serial driver for NVIDIA Tegra SoCs
6 *
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
8 *
9 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pagemap.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/serial_core.h>
30 #include <linux/serial_reg.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
33 #include <linux/termios.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36
37 #define TEGRA_UART_TYPE "TEGRA_UART"
38 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
39 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
40
41 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
42 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
43 #define TEGRA_UART_IER_EORD 0x20
44 #define TEGRA_UART_MCR_RTS_EN 0x40
45 #define TEGRA_UART_MCR_CTS_EN 0x20
46 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
47 UART_LSR_PE | UART_LSR_FE)
48 #define TEGRA_UART_IRDA_CSR 0x08
49 #define TEGRA_UART_SIR_ENABLED 0x80
50
51 #define TEGRA_UART_TX_PIO 1
52 #define TEGRA_UART_TX_DMA 2
53 #define TEGRA_UART_MIN_DMA 16
54 #define TEGRA_UART_FIFO_SIZE 32
55
56 /*
57 * Tx fifo trigger level setting in tegra uart is in
58 * reverse way then conventional uart.
59 */
60 #define TEGRA_UART_TX_TRIG_16B 0x00
61 #define TEGRA_UART_TX_TRIG_8B 0x10
62 #define TEGRA_UART_TX_TRIG_4B 0x20
63 #define TEGRA_UART_TX_TRIG_1B 0x30
64
65 #define TEGRA_UART_MAXIMUM 8
66
67 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
68 #define TEGRA_UART_DEFAULT_BAUD 115200
69 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
70
71 /* Tx transfer mode */
72 #define TEGRA_TX_PIO 1
73 #define TEGRA_TX_DMA 2
74
75 #define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
76
77 /**
78 * tegra_uart_chip_data: SOC specific data.
79 *
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
82 * Tegra30 does not allow this.
83 * @support_clk_src_div: Clock source support the clock divider.
84 */
85 struct tegra_uart_chip_data {
86 bool tx_fifo_full_status;
87 bool allow_txfifo_reset_fifo_mode;
88 bool support_clk_src_div;
89 bool fifo_mode_enable_status;
90 int uart_max_port;
91 int max_dma_burst_bytes;
92 int error_tolerance_low_range;
93 int error_tolerance_high_range;
94 };
95
96 struct tegra_baud_tolerance {
97 u32 lower_range_baud;
98 u32 upper_range_baud;
99 s32 tolerance;
100 };
101
102 struct tegra_uart_port {
103 struct uart_port uport;
104 const struct tegra_uart_chip_data *cdata;
105
106 struct clk *uart_clk;
107 struct reset_control *rst;
108 unsigned int current_baud;
109
110 /* Register shadow */
111 unsigned long fcr_shadow;
112 unsigned long mcr_shadow;
113 unsigned long lcr_shadow;
114 unsigned long ier_shadow;
115 bool rts_active;
116
117 int tx_in_progress;
118 unsigned int tx_bytes;
119
120 bool enable_modem_interrupt;
121
122 bool rx_timeout;
123 int rx_in_progress;
124 int symb_bit;
125
126 struct dma_chan *rx_dma_chan;
127 struct dma_chan *tx_dma_chan;
128 dma_addr_t rx_dma_buf_phys;
129 dma_addr_t tx_dma_buf_phys;
130 unsigned char *rx_dma_buf_virt;
131 unsigned char *tx_dma_buf_virt;
132 struct dma_async_tx_descriptor *tx_dma_desc;
133 struct dma_async_tx_descriptor *rx_dma_desc;
134 dma_cookie_t tx_cookie;
135 dma_cookie_t rx_cookie;
136 unsigned int tx_bytes_requested;
137 unsigned int rx_bytes_requested;
138 struct tegra_baud_tolerance *baud_tolerance;
139 int n_adjustable_baud_rates;
140 int required_rate;
141 int configured_rate;
142 bool use_rx_pio;
143 bool use_tx_pio;
144 };
145
146 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
147 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
148 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
149 bool dma_to_memory);
150
tegra_uart_read(struct tegra_uart_port * tup,unsigned long reg)151 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
152 unsigned long reg)
153 {
154 return readl(tup->uport.membase + (reg << tup->uport.regshift));
155 }
156
tegra_uart_write(struct tegra_uart_port * tup,unsigned val,unsigned long reg)157 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
158 unsigned long reg)
159 {
160 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
161 }
162
to_tegra_uport(struct uart_port * u)163 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
164 {
165 return container_of(u, struct tegra_uart_port, uport);
166 }
167
tegra_uart_get_mctrl(struct uart_port * u)168 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
169 {
170 struct tegra_uart_port *tup = to_tegra_uport(u);
171
172 /*
173 * RI - Ring detector is active
174 * CD/DCD/CAR - Carrier detect is always active. For some reason
175 * linux has different names for carrier detect.
176 * DSR - Data Set ready is active as the hardware doesn't support it.
177 * Don't know if the linux support this yet?
178 * CTS - Clear to send. Always set to active, as the hardware handles
179 * CTS automatically.
180 */
181 if (tup->enable_modem_interrupt)
182 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
183 return TIOCM_CTS;
184 }
185
set_rts(struct tegra_uart_port * tup,bool active)186 static void set_rts(struct tegra_uart_port *tup, bool active)
187 {
188 unsigned long mcr;
189
190 mcr = tup->mcr_shadow;
191 if (active)
192 mcr |= TEGRA_UART_MCR_RTS_EN;
193 else
194 mcr &= ~TEGRA_UART_MCR_RTS_EN;
195 if (mcr != tup->mcr_shadow) {
196 tegra_uart_write(tup, mcr, UART_MCR);
197 tup->mcr_shadow = mcr;
198 }
199 }
200
set_dtr(struct tegra_uart_port * tup,bool active)201 static void set_dtr(struct tegra_uart_port *tup, bool active)
202 {
203 unsigned long mcr;
204
205 mcr = tup->mcr_shadow;
206 if (active)
207 mcr |= UART_MCR_DTR;
208 else
209 mcr &= ~UART_MCR_DTR;
210 if (mcr != tup->mcr_shadow) {
211 tegra_uart_write(tup, mcr, UART_MCR);
212 tup->mcr_shadow = mcr;
213 }
214 }
215
set_loopbk(struct tegra_uart_port * tup,bool active)216 static void set_loopbk(struct tegra_uart_port *tup, bool active)
217 {
218 unsigned long mcr = tup->mcr_shadow;
219
220 if (active)
221 mcr |= UART_MCR_LOOP;
222 else
223 mcr &= ~UART_MCR_LOOP;
224
225 if (mcr != tup->mcr_shadow) {
226 tegra_uart_write(tup, mcr, UART_MCR);
227 tup->mcr_shadow = mcr;
228 }
229 }
230
tegra_uart_set_mctrl(struct uart_port * u,unsigned int mctrl)231 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
232 {
233 struct tegra_uart_port *tup = to_tegra_uport(u);
234 int enable;
235
236 tup->rts_active = !!(mctrl & TIOCM_RTS);
237 set_rts(tup, tup->rts_active);
238
239 enable = !!(mctrl & TIOCM_DTR);
240 set_dtr(tup, enable);
241
242 enable = !!(mctrl & TIOCM_LOOP);
243 set_loopbk(tup, enable);
244 }
245
tegra_uart_break_ctl(struct uart_port * u,int break_ctl)246 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
247 {
248 struct tegra_uart_port *tup = to_tegra_uport(u);
249 unsigned long lcr;
250
251 lcr = tup->lcr_shadow;
252 if (break_ctl)
253 lcr |= UART_LCR_SBC;
254 else
255 lcr &= ~UART_LCR_SBC;
256 tegra_uart_write(tup, lcr, UART_LCR);
257 tup->lcr_shadow = lcr;
258 }
259
260 /**
261 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
262 *
263 * @tup: Tegra serial port data structure.
264 * @cycles: Number of clock periods to wait.
265 *
266 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
267 * clock speed is 16X the current baud rate.
268 */
tegra_uart_wait_cycle_time(struct tegra_uart_port * tup,unsigned int cycles)269 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
270 unsigned int cycles)
271 {
272 if (tup->current_baud)
273 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
274 }
275
276 /* Wait for a symbol-time. */
tegra_uart_wait_sym_time(struct tegra_uart_port * tup,unsigned int syms)277 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
278 unsigned int syms)
279 {
280 if (tup->current_baud)
281 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
282 tup->current_baud));
283 }
284
tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port * tup)285 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
286 {
287 unsigned long iir;
288 unsigned int tmout = 100;
289
290 do {
291 iir = tegra_uart_read(tup, UART_IIR);
292 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN)
293 return 0;
294 udelay(1);
295 } while (--tmout);
296
297 return -ETIMEDOUT;
298 }
299
tegra_uart_fifo_reset(struct tegra_uart_port * tup,u8 fcr_bits)300 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
301 {
302 unsigned long fcr = tup->fcr_shadow;
303 unsigned int lsr, tmout = 10000;
304
305 if (tup->rts_active)
306 set_rts(tup, false);
307
308 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
309 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
310 tegra_uart_write(tup, fcr, UART_FCR);
311 } else {
312 fcr &= ~UART_FCR_ENABLE_FIFO;
313 tegra_uart_write(tup, fcr, UART_FCR);
314 udelay(60);
315 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
316 tegra_uart_write(tup, fcr, UART_FCR);
317 fcr |= UART_FCR_ENABLE_FIFO;
318 tegra_uart_write(tup, fcr, UART_FCR);
319 if (tup->cdata->fifo_mode_enable_status)
320 tegra_uart_wait_fifo_mode_enabled(tup);
321 }
322
323 /* Dummy read to ensure the write is posted */
324 tegra_uart_read(tup, UART_SCR);
325
326 /*
327 * For all tegra devices (up to t210), there is a hardware issue that
328 * requires software to wait for 32 UART clock periods for the flush
329 * to propagate, otherwise data could be lost.
330 */
331 tegra_uart_wait_cycle_time(tup, 32);
332
333 do {
334 lsr = tegra_uart_read(tup, UART_LSR);
335 if ((lsr | UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
336 break;
337 udelay(1);
338 } while (--tmout);
339
340 if (tup->rts_active)
341 set_rts(tup, true);
342 }
343
tegra_get_tolerance_rate(struct tegra_uart_port * tup,unsigned int baud,long rate)344 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
345 unsigned int baud, long rate)
346 {
347 int i;
348
349 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
350 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
351 baud <= tup->baud_tolerance[i].upper_range_baud)
352 return (rate + (rate *
353 tup->baud_tolerance[i].tolerance) / 10000);
354 }
355
356 return rate;
357 }
358
tegra_check_rate_in_range(struct tegra_uart_port * tup)359 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
360 {
361 long diff;
362
363 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
364 / tup->required_rate;
365 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
366 diff > (tup->cdata->error_tolerance_high_range * 100)) {
367 dev_err(tup->uport.dev,
368 "configured baud rate is out of range by %ld", diff);
369 return -EIO;
370 }
371
372 return 0;
373 }
374
tegra_set_baudrate(struct tegra_uart_port * tup,unsigned int baud)375 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
376 {
377 unsigned long rate;
378 unsigned int divisor;
379 unsigned long lcr;
380 unsigned long flags;
381 int ret;
382
383 if (tup->current_baud == baud)
384 return 0;
385
386 if (tup->cdata->support_clk_src_div) {
387 rate = baud * 16;
388 tup->required_rate = rate;
389
390 if (tup->n_adjustable_baud_rates)
391 rate = tegra_get_tolerance_rate(tup, baud, rate);
392
393 ret = clk_set_rate(tup->uart_clk, rate);
394 if (ret < 0) {
395 dev_err(tup->uport.dev,
396 "clk_set_rate() failed for rate %lu\n", rate);
397 return ret;
398 }
399 tup->configured_rate = clk_get_rate(tup->uart_clk);
400 divisor = 1;
401 ret = tegra_check_rate_in_range(tup);
402 if (ret < 0)
403 return ret;
404 } else {
405 rate = clk_get_rate(tup->uart_clk);
406 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
407 }
408
409 spin_lock_irqsave(&tup->uport.lock, flags);
410 lcr = tup->lcr_shadow;
411 lcr |= UART_LCR_DLAB;
412 tegra_uart_write(tup, lcr, UART_LCR);
413
414 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
415 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
416
417 lcr &= ~UART_LCR_DLAB;
418 tegra_uart_write(tup, lcr, UART_LCR);
419
420 /* Dummy read to ensure the write is posted */
421 tegra_uart_read(tup, UART_SCR);
422 spin_unlock_irqrestore(&tup->uport.lock, flags);
423
424 tup->current_baud = baud;
425
426 /* wait two character intervals at new rate */
427 tegra_uart_wait_sym_time(tup, 2);
428 return 0;
429 }
430
tegra_uart_decode_rx_error(struct tegra_uart_port * tup,unsigned long lsr)431 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
432 unsigned long lsr)
433 {
434 char flag = TTY_NORMAL;
435
436 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
437 if (lsr & UART_LSR_OE) {
438 /* Overrrun error */
439 flag = TTY_OVERRUN;
440 tup->uport.icount.overrun++;
441 dev_err(tup->uport.dev, "Got overrun errors\n");
442 } else if (lsr & UART_LSR_PE) {
443 /* Parity error */
444 flag = TTY_PARITY;
445 tup->uport.icount.parity++;
446 dev_err(tup->uport.dev, "Got Parity errors\n");
447 } else if (lsr & UART_LSR_FE) {
448 flag = TTY_FRAME;
449 tup->uport.icount.frame++;
450 dev_err(tup->uport.dev, "Got frame errors\n");
451 } else if (lsr & UART_LSR_BI) {
452 /*
453 * Break error
454 * If FIFO read error without any data, reset Rx FIFO
455 */
456 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
457 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
458 if (tup->uport.ignore_status_mask & UART_LSR_BI)
459 return TTY_BREAK;
460 flag = TTY_BREAK;
461 tup->uport.icount.brk++;
462 dev_dbg(tup->uport.dev, "Got Break\n");
463 }
464 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
465 }
466
467 return flag;
468 }
469
tegra_uart_request_port(struct uart_port * u)470 static int tegra_uart_request_port(struct uart_port *u)
471 {
472 return 0;
473 }
474
tegra_uart_release_port(struct uart_port * u)475 static void tegra_uart_release_port(struct uart_port *u)
476 {
477 /* Nothing to do here */
478 }
479
tegra_uart_fill_tx_fifo(struct tegra_uart_port * tup,int max_bytes)480 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
481 {
482 struct circ_buf *xmit = &tup->uport.state->xmit;
483 int i;
484
485 for (i = 0; i < max_bytes; i++) {
486 BUG_ON(uart_circ_empty(xmit));
487 if (tup->cdata->tx_fifo_full_status) {
488 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
489 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
490 break;
491 }
492 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
493 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
494 tup->uport.icount.tx++;
495 }
496 }
497
tegra_uart_start_pio_tx(struct tegra_uart_port * tup,unsigned int bytes)498 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
499 unsigned int bytes)
500 {
501 if (bytes > TEGRA_UART_MIN_DMA)
502 bytes = TEGRA_UART_MIN_DMA;
503
504 tup->tx_in_progress = TEGRA_UART_TX_PIO;
505 tup->tx_bytes = bytes;
506 tup->ier_shadow |= UART_IER_THRI;
507 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
508 }
509
tegra_uart_tx_dma_complete(void * args)510 static void tegra_uart_tx_dma_complete(void *args)
511 {
512 struct tegra_uart_port *tup = args;
513 struct circ_buf *xmit = &tup->uport.state->xmit;
514 struct dma_tx_state state;
515 unsigned long flags;
516 unsigned int count;
517
518 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
519 count = tup->tx_bytes_requested - state.residue;
520 async_tx_ack(tup->tx_dma_desc);
521 spin_lock_irqsave(&tup->uport.lock, flags);
522 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
523 tup->tx_in_progress = 0;
524 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
525 uart_write_wakeup(&tup->uport);
526 tegra_uart_start_next_tx(tup);
527 spin_unlock_irqrestore(&tup->uport.lock, flags);
528 }
529
tegra_uart_start_tx_dma(struct tegra_uart_port * tup,unsigned long count)530 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
531 unsigned long count)
532 {
533 struct circ_buf *xmit = &tup->uport.state->xmit;
534 dma_addr_t tx_phys_addr;
535
536 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
537 UART_XMIT_SIZE, DMA_TO_DEVICE);
538
539 tup->tx_bytes = count & ~(0xF);
540 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
541 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
542 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
543 DMA_PREP_INTERRUPT);
544 if (!tup->tx_dma_desc) {
545 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
546 return -EIO;
547 }
548
549 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
550 tup->tx_dma_desc->callback_param = tup;
551 tup->tx_in_progress = TEGRA_UART_TX_DMA;
552 tup->tx_bytes_requested = tup->tx_bytes;
553 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
554 dma_async_issue_pending(tup->tx_dma_chan);
555 return 0;
556 }
557
tegra_uart_start_next_tx(struct tegra_uart_port * tup)558 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
559 {
560 unsigned long tail;
561 unsigned long count;
562 struct circ_buf *xmit = &tup->uport.state->xmit;
563
564 if (!tup->current_baud)
565 return;
566
567 tail = (unsigned long)&xmit->buf[xmit->tail];
568 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
569 if (!count)
570 return;
571
572 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
573 tegra_uart_start_pio_tx(tup, count);
574 else if (BYTES_TO_ALIGN(tail) > 0)
575 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
576 else
577 tegra_uart_start_tx_dma(tup, count);
578 }
579
580 /* Called by serial core driver with u->lock taken. */
tegra_uart_start_tx(struct uart_port * u)581 static void tegra_uart_start_tx(struct uart_port *u)
582 {
583 struct tegra_uart_port *tup = to_tegra_uport(u);
584 struct circ_buf *xmit = &u->state->xmit;
585
586 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
587 tegra_uart_start_next_tx(tup);
588 }
589
tegra_uart_tx_empty(struct uart_port * u)590 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
591 {
592 struct tegra_uart_port *tup = to_tegra_uport(u);
593 unsigned int ret = 0;
594 unsigned long flags;
595
596 spin_lock_irqsave(&u->lock, flags);
597 if (!tup->tx_in_progress) {
598 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
599 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
600 ret = TIOCSER_TEMT;
601 }
602 spin_unlock_irqrestore(&u->lock, flags);
603 return ret;
604 }
605
tegra_uart_stop_tx(struct uart_port * u)606 static void tegra_uart_stop_tx(struct uart_port *u)
607 {
608 struct tegra_uart_port *tup = to_tegra_uport(u);
609 struct circ_buf *xmit = &tup->uport.state->xmit;
610 struct dma_tx_state state;
611 unsigned int count;
612
613 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
614 return;
615
616 dmaengine_terminate_all(tup->tx_dma_chan);
617 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
618 count = tup->tx_bytes_requested - state.residue;
619 async_tx_ack(tup->tx_dma_desc);
620 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
621 tup->tx_in_progress = 0;
622 }
623
tegra_uart_handle_tx_pio(struct tegra_uart_port * tup)624 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
625 {
626 struct circ_buf *xmit = &tup->uport.state->xmit;
627
628 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
629 tup->tx_in_progress = 0;
630 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
631 uart_write_wakeup(&tup->uport);
632 tegra_uart_start_next_tx(tup);
633 }
634
tegra_uart_handle_rx_pio(struct tegra_uart_port * tup,struct tty_port * tty)635 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
636 struct tty_port *tty)
637 {
638 do {
639 char flag = TTY_NORMAL;
640 unsigned long lsr = 0;
641 unsigned char ch;
642
643 lsr = tegra_uart_read(tup, UART_LSR);
644 if (!(lsr & UART_LSR_DR))
645 break;
646
647 flag = tegra_uart_decode_rx_error(tup, lsr);
648 if (flag != TTY_NORMAL)
649 continue;
650
651 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
652 tup->uport.icount.rx++;
653
654 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
655 tty_insert_flip_char(tty, ch, flag);
656
657 if (tup->uport.ignore_status_mask & UART_LSR_DR)
658 continue;
659 } while (1);
660 }
661
tegra_uart_copy_rx_to_tty(struct tegra_uart_port * tup,struct tty_port * tty,unsigned int count)662 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
663 struct tty_port *tty,
664 unsigned int count)
665 {
666 int copied;
667
668 /* If count is zero, then there is no data to be copied */
669 if (!count)
670 return;
671
672 tup->uport.icount.rx += count;
673 if (!tty) {
674 dev_err(tup->uport.dev, "No tty port\n");
675 return;
676 }
677
678 if (tup->uport.ignore_status_mask & UART_LSR_DR)
679 return;
680
681 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
682 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
683 copied = tty_insert_flip_string(tty,
684 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
685 if (copied != count) {
686 WARN_ON(1);
687 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
688 }
689 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
690 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
691 }
692
tegra_uart_rx_buffer_push(struct tegra_uart_port * tup,unsigned int residue)693 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
694 unsigned int residue)
695 {
696 struct tty_port *port = &tup->uport.state->port;
697 struct tty_struct *tty = tty_port_tty_get(port);
698 unsigned int count;
699
700 async_tx_ack(tup->rx_dma_desc);
701 count = tup->rx_bytes_requested - residue;
702
703 /* If we are here, DMA is stopped */
704 tegra_uart_copy_rx_to_tty(tup, port, count);
705
706 tegra_uart_handle_rx_pio(tup, port);
707 if (tty) {
708 tty_flip_buffer_push(port);
709 tty_kref_put(tty);
710 }
711 }
712
tegra_uart_rx_dma_complete(void * args)713 static void tegra_uart_rx_dma_complete(void *args)
714 {
715 struct tegra_uart_port *tup = args;
716 struct uart_port *u = &tup->uport;
717 unsigned long flags;
718 struct dma_tx_state state;
719 enum dma_status status;
720
721 spin_lock_irqsave(&u->lock, flags);
722
723 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
724
725 if (status == DMA_IN_PROGRESS) {
726 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
727 goto done;
728 }
729
730 /* Deactivate flow control to stop sender */
731 if (tup->rts_active)
732 set_rts(tup, false);
733
734 tegra_uart_rx_buffer_push(tup, 0);
735 tegra_uart_start_rx_dma(tup);
736
737 /* Activate flow control to start transfer */
738 if (tup->rts_active)
739 set_rts(tup, true);
740
741 done:
742 spin_unlock_irqrestore(&u->lock, flags);
743 }
744
tegra_uart_handle_rx_dma(struct tegra_uart_port * tup)745 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
746 {
747 struct dma_tx_state state;
748
749 /* Deactivate flow control to stop sender */
750 if (tup->rts_active)
751 set_rts(tup, false);
752
753 dmaengine_terminate_all(tup->rx_dma_chan);
754 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
755 tegra_uart_rx_buffer_push(tup, state.residue);
756 tegra_uart_start_rx_dma(tup);
757
758 if (tup->rts_active)
759 set_rts(tup, true);
760 }
761
tegra_uart_start_rx_dma(struct tegra_uart_port * tup)762 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
763 {
764 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
765
766 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
767 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
768 DMA_PREP_INTERRUPT);
769 if (!tup->rx_dma_desc) {
770 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
771 return -EIO;
772 }
773
774 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
775 tup->rx_dma_desc->callback_param = tup;
776 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
777 count, DMA_TO_DEVICE);
778 tup->rx_bytes_requested = count;
779 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
780 dma_async_issue_pending(tup->rx_dma_chan);
781 return 0;
782 }
783
tegra_uart_handle_modem_signal_change(struct uart_port * u)784 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
785 {
786 struct tegra_uart_port *tup = to_tegra_uport(u);
787 unsigned long msr;
788
789 msr = tegra_uart_read(tup, UART_MSR);
790 if (!(msr & UART_MSR_ANY_DELTA))
791 return;
792
793 if (msr & UART_MSR_TERI)
794 tup->uport.icount.rng++;
795 if (msr & UART_MSR_DDSR)
796 tup->uport.icount.dsr++;
797 /* We may only get DDCD when HW init and reset */
798 if (msr & UART_MSR_DDCD)
799 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
800 /* Will start/stop_tx accordingly */
801 if (msr & UART_MSR_DCTS)
802 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
803 }
804
do_handle_rx_pio(struct tegra_uart_port * tup)805 static void do_handle_rx_pio(struct tegra_uart_port *tup)
806 {
807 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
808 struct tty_port *port = &tup->uport.state->port;
809
810 tegra_uart_handle_rx_pio(tup, port);
811 if (tty) {
812 tty_flip_buffer_push(port);
813 tty_kref_put(tty);
814 }
815 }
816
tegra_uart_isr(int irq,void * data)817 static irqreturn_t tegra_uart_isr(int irq, void *data)
818 {
819 struct tegra_uart_port *tup = data;
820 struct uart_port *u = &tup->uport;
821 unsigned long iir;
822 unsigned long ier;
823 bool is_rx_int = false;
824 unsigned long flags;
825
826 spin_lock_irqsave(&u->lock, flags);
827 while (1) {
828 iir = tegra_uart_read(tup, UART_IIR);
829 if (iir & UART_IIR_NO_INT) {
830 if (!tup->use_rx_pio && is_rx_int) {
831 tegra_uart_handle_rx_dma(tup);
832 if (tup->rx_in_progress) {
833 ier = tup->ier_shadow;
834 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
835 TEGRA_UART_IER_EORD);
836 tup->ier_shadow = ier;
837 tegra_uart_write(tup, ier, UART_IER);
838 }
839 }
840 spin_unlock_irqrestore(&u->lock, flags);
841 return IRQ_HANDLED;
842 }
843
844 switch ((iir >> 1) & 0x7) {
845 case 0: /* Modem signal change interrupt */
846 tegra_uart_handle_modem_signal_change(u);
847 break;
848
849 case 1: /* Transmit interrupt only triggered when using PIO */
850 tup->ier_shadow &= ~UART_IER_THRI;
851 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
852 tegra_uart_handle_tx_pio(tup);
853 break;
854
855 case 4: /* End of data */
856 case 6: /* Rx timeout */
857 case 2: /* Receive */
858 if (!tup->use_rx_pio && !is_rx_int) {
859 is_rx_int = true;
860 /* Disable Rx interrupts */
861 ier = tup->ier_shadow;
862 ier |= UART_IER_RDI;
863 tegra_uart_write(tup, ier, UART_IER);
864 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
865 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
866 tup->ier_shadow = ier;
867 tegra_uart_write(tup, ier, UART_IER);
868 } else {
869 do_handle_rx_pio(tup);
870 }
871 break;
872
873 case 3: /* Receive error */
874 tegra_uart_decode_rx_error(tup,
875 tegra_uart_read(tup, UART_LSR));
876 break;
877
878 case 5: /* break nothing to handle */
879 case 7: /* break nothing to handle */
880 break;
881 }
882 }
883 }
884
tegra_uart_stop_rx(struct uart_port * u)885 static void tegra_uart_stop_rx(struct uart_port *u)
886 {
887 struct tegra_uart_port *tup = to_tegra_uport(u);
888 struct tty_port *port = &tup->uport.state->port;
889 struct dma_tx_state state;
890 unsigned long ier;
891
892 if (tup->rts_active)
893 set_rts(tup, false);
894
895 if (!tup->rx_in_progress)
896 return;
897
898 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
899
900 ier = tup->ier_shadow;
901 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
902 TEGRA_UART_IER_EORD);
903 tup->ier_shadow = ier;
904 tegra_uart_write(tup, ier, UART_IER);
905 tup->rx_in_progress = 0;
906 if (tup->rx_dma_chan && !tup->use_rx_pio) {
907 dmaengine_terminate_all(tup->rx_dma_chan);
908 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
909 tegra_uart_rx_buffer_push(tup, state.residue);
910 } else {
911 tegra_uart_handle_rx_pio(tup, port);
912 }
913 }
914
tegra_uart_hw_deinit(struct tegra_uart_port * tup)915 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
916 {
917 unsigned long flags;
918 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
919 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
920 unsigned long wait_time;
921 unsigned long lsr;
922 unsigned long msr;
923 unsigned long mcr;
924
925 /* Disable interrupts */
926 tegra_uart_write(tup, 0, UART_IER);
927
928 lsr = tegra_uart_read(tup, UART_LSR);
929 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
930 msr = tegra_uart_read(tup, UART_MSR);
931 mcr = tegra_uart_read(tup, UART_MCR);
932 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
933 dev_err(tup->uport.dev,
934 "Tx Fifo not empty, CTS disabled, waiting\n");
935
936 /* Wait for Tx fifo to be empty */
937 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
938 wait_time = min(fifo_empty_time, 100lu);
939 udelay(wait_time);
940 fifo_empty_time -= wait_time;
941 if (!fifo_empty_time) {
942 msr = tegra_uart_read(tup, UART_MSR);
943 mcr = tegra_uart_read(tup, UART_MCR);
944 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
945 (msr & UART_MSR_CTS))
946 dev_err(tup->uport.dev,
947 "Slave not ready\n");
948 break;
949 }
950 lsr = tegra_uart_read(tup, UART_LSR);
951 }
952 }
953
954 spin_lock_irqsave(&tup->uport.lock, flags);
955 /* Reset the Rx and Tx FIFOs */
956 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
957 tup->current_baud = 0;
958 spin_unlock_irqrestore(&tup->uport.lock, flags);
959
960 tup->rx_in_progress = 0;
961 tup->tx_in_progress = 0;
962
963 if (!tup->use_rx_pio)
964 tegra_uart_dma_channel_free(tup, true);
965 if (!tup->use_tx_pio)
966 tegra_uart_dma_channel_free(tup, false);
967
968 clk_disable_unprepare(tup->uart_clk);
969 }
970
tegra_uart_hw_init(struct tegra_uart_port * tup)971 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
972 {
973 int ret;
974
975 tup->fcr_shadow = 0;
976 tup->mcr_shadow = 0;
977 tup->lcr_shadow = 0;
978 tup->ier_shadow = 0;
979 tup->current_baud = 0;
980
981 clk_prepare_enable(tup->uart_clk);
982
983 /* Reset the UART controller to clear all previous status.*/
984 reset_control_assert(tup->rst);
985 udelay(10);
986 reset_control_deassert(tup->rst);
987
988 tup->rx_in_progress = 0;
989 tup->tx_in_progress = 0;
990
991 /*
992 * Set the trigger level
993 *
994 * For PIO mode:
995 *
996 * For receive, this will interrupt the CPU after that many number of
997 * bytes are received, for the remaining bytes the receive timeout
998 * interrupt is received. Rx high watermark is set to 4.
999 *
1000 * For transmit, if the trasnmit interrupt is enabled, this will
1001 * interrupt the CPU when the number of entries in the FIFO reaches the
1002 * low watermark. Tx low watermark is set to 16 bytes.
1003 *
1004 * For DMA mode:
1005 *
1006 * Set the Tx trigger to 16. This should match the DMA burst size that
1007 * programmed in the DMA registers.
1008 */
1009 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1010
1011 if (tup->use_rx_pio) {
1012 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1013 } else {
1014 if (tup->cdata->max_dma_burst_bytes == 8)
1015 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1016 else
1017 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1018 }
1019
1020 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1021 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1022
1023 /* Dummy read to ensure the write is posted */
1024 tegra_uart_read(tup, UART_SCR);
1025
1026 if (tup->cdata->fifo_mode_enable_status) {
1027 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1028 dev_err(tup->uport.dev, "FIFO mode not enabled\n");
1029 if (ret < 0)
1030 return ret;
1031 } else {
1032 /*
1033 * For all tegra devices (up to t210), there is a hardware
1034 * issue that requires software to wait for 3 UART clock
1035 * periods after enabling the TX fifo, otherwise data could
1036 * be lost.
1037 */
1038 tegra_uart_wait_cycle_time(tup, 3);
1039 }
1040
1041 /*
1042 * Initialize the UART with default configuration
1043 * (115200, N, 8, 1) so that the receive DMA buffer may be
1044 * enqueued
1045 */
1046 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1047 if (ret < 0) {
1048 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1049 return ret;
1050 }
1051 if (!tup->use_rx_pio) {
1052 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1053 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1054 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1055
1056 ret = tegra_uart_start_rx_dma(tup);
1057 if (ret < 0) {
1058 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
1059 return ret;
1060 }
1061 } else {
1062 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1063 }
1064 tup->rx_in_progress = 1;
1065
1066 /*
1067 * Enable IE_RXS for the receive status interrupts like line errros.
1068 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1069 *
1070 * If using DMA mode, enable EORD instead of receive interrupt which
1071 * will interrupt after the UART is done with the receive instead of
1072 * the interrupt when the FIFO "threshold" is reached.
1073 *
1074 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1075 * the DATA is sitting in the FIFO and couldn't be transferred to the
1076 * DMA as the DMA size alignment (4 bytes) is not met. EORD will be
1077 * triggered when there is a pause of the incomming data stream for 4
1078 * characters long.
1079 *
1080 * For pauses in the data which is not aligned to 4 bytes, we get
1081 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1082 * then the EORD.
1083 */
1084 if (!tup->use_rx_pio)
1085 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE |
1086 TEGRA_UART_IER_EORD;
1087 else
1088 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1089
1090 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1091 return 0;
1092 }
1093
tegra_uart_dma_channel_free(struct tegra_uart_port * tup,bool dma_to_memory)1094 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1095 bool dma_to_memory)
1096 {
1097 if (dma_to_memory) {
1098 dmaengine_terminate_all(tup->rx_dma_chan);
1099 dma_release_channel(tup->rx_dma_chan);
1100 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1101 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1102 tup->rx_dma_chan = NULL;
1103 tup->rx_dma_buf_phys = 0;
1104 tup->rx_dma_buf_virt = NULL;
1105 } else {
1106 dmaengine_terminate_all(tup->tx_dma_chan);
1107 dma_release_channel(tup->tx_dma_chan);
1108 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1109 UART_XMIT_SIZE, DMA_TO_DEVICE);
1110 tup->tx_dma_chan = NULL;
1111 tup->tx_dma_buf_phys = 0;
1112 tup->tx_dma_buf_virt = NULL;
1113 }
1114 }
1115
tegra_uart_dma_channel_allocate(struct tegra_uart_port * tup,bool dma_to_memory)1116 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1117 bool dma_to_memory)
1118 {
1119 struct dma_chan *dma_chan;
1120 unsigned char *dma_buf;
1121 dma_addr_t dma_phys;
1122 int ret;
1123 struct dma_slave_config dma_sconfig;
1124
1125 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
1126 dma_to_memory ? "rx" : "tx");
1127 if (IS_ERR(dma_chan)) {
1128 ret = PTR_ERR(dma_chan);
1129 dev_err(tup->uport.dev,
1130 "DMA channel alloc failed: %d\n", ret);
1131 return ret;
1132 }
1133
1134 if (dma_to_memory) {
1135 dma_buf = dma_alloc_coherent(tup->uport.dev,
1136 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1137 &dma_phys, GFP_KERNEL);
1138 if (!dma_buf) {
1139 dev_err(tup->uport.dev,
1140 "Not able to allocate the dma buffer\n");
1141 dma_release_channel(dma_chan);
1142 return -ENOMEM;
1143 }
1144 dma_sconfig.src_addr = tup->uport.mapbase;
1145 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1146 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1147 tup->rx_dma_chan = dma_chan;
1148 tup->rx_dma_buf_virt = dma_buf;
1149 tup->rx_dma_buf_phys = dma_phys;
1150 } else {
1151 dma_phys = dma_map_single(tup->uport.dev,
1152 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1153 DMA_TO_DEVICE);
1154 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1155 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1156 dma_release_channel(dma_chan);
1157 return -ENOMEM;
1158 }
1159 dma_buf = tup->uport.state->xmit.buf;
1160 dma_sconfig.dst_addr = tup->uport.mapbase;
1161 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162 dma_sconfig.dst_maxburst = 16;
1163 tup->tx_dma_chan = dma_chan;
1164 tup->tx_dma_buf_virt = dma_buf;
1165 tup->tx_dma_buf_phys = dma_phys;
1166 }
1167
1168 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1169 if (ret < 0) {
1170 dev_err(tup->uport.dev,
1171 "Dma slave config failed, err = %d\n", ret);
1172 tegra_uart_dma_channel_free(tup, dma_to_memory);
1173 return ret;
1174 }
1175
1176 return 0;
1177 }
1178
tegra_uart_startup(struct uart_port * u)1179 static int tegra_uart_startup(struct uart_port *u)
1180 {
1181 struct tegra_uart_port *tup = to_tegra_uport(u);
1182 int ret;
1183
1184 if (!tup->use_tx_pio) {
1185 ret = tegra_uart_dma_channel_allocate(tup, false);
1186 if (ret < 0) {
1187 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1188 ret);
1189 return ret;
1190 }
1191 }
1192
1193 if (!tup->use_rx_pio) {
1194 ret = tegra_uart_dma_channel_allocate(tup, true);
1195 if (ret < 0) {
1196 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1197 ret);
1198 goto fail_rx_dma;
1199 }
1200 }
1201
1202 ret = tegra_uart_hw_init(tup);
1203 if (ret < 0) {
1204 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1205 goto fail_hw_init;
1206 }
1207
1208 ret = request_irq(u->irq, tegra_uart_isr, 0,
1209 dev_name(u->dev), tup);
1210 if (ret < 0) {
1211 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1212 goto fail_hw_init;
1213 }
1214 return 0;
1215
1216 fail_hw_init:
1217 if (!tup->use_rx_pio)
1218 tegra_uart_dma_channel_free(tup, true);
1219 fail_rx_dma:
1220 if (!tup->use_tx_pio)
1221 tegra_uart_dma_channel_free(tup, false);
1222 return ret;
1223 }
1224
1225 /*
1226 * Flush any TX data submitted for DMA and PIO. Called when the
1227 * TX circular buffer is reset.
1228 */
tegra_uart_flush_buffer(struct uart_port * u)1229 static void tegra_uart_flush_buffer(struct uart_port *u)
1230 {
1231 struct tegra_uart_port *tup = to_tegra_uport(u);
1232
1233 tup->tx_bytes = 0;
1234 if (tup->tx_dma_chan)
1235 dmaengine_terminate_all(tup->tx_dma_chan);
1236 }
1237
tegra_uart_shutdown(struct uart_port * u)1238 static void tegra_uart_shutdown(struct uart_port *u)
1239 {
1240 struct tegra_uart_port *tup = to_tegra_uport(u);
1241
1242 tegra_uart_hw_deinit(tup);
1243 free_irq(u->irq, tup);
1244 }
1245
tegra_uart_enable_ms(struct uart_port * u)1246 static void tegra_uart_enable_ms(struct uart_port *u)
1247 {
1248 struct tegra_uart_port *tup = to_tegra_uport(u);
1249
1250 if (tup->enable_modem_interrupt) {
1251 tup->ier_shadow |= UART_IER_MSI;
1252 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1253 }
1254 }
1255
tegra_uart_set_termios(struct uart_port * u,struct ktermios * termios,struct ktermios * oldtermios)1256 static void tegra_uart_set_termios(struct uart_port *u,
1257 struct ktermios *termios, struct ktermios *oldtermios)
1258 {
1259 struct tegra_uart_port *tup = to_tegra_uport(u);
1260 unsigned int baud;
1261 unsigned long flags;
1262 unsigned int lcr;
1263 int symb_bit = 1;
1264 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1265 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1266 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1267 int ret;
1268
1269 max_divider *= 16;
1270 spin_lock_irqsave(&u->lock, flags);
1271
1272 /* Changing configuration, it is safe to stop any rx now */
1273 if (tup->rts_active)
1274 set_rts(tup, false);
1275
1276 /* Clear all interrupts as configuration is going to be changed */
1277 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1278 tegra_uart_read(tup, UART_IER);
1279 tegra_uart_write(tup, 0, UART_IER);
1280 tegra_uart_read(tup, UART_IER);
1281
1282 /* Parity */
1283 lcr = tup->lcr_shadow;
1284 lcr &= ~UART_LCR_PARITY;
1285
1286 /* CMSPAR isn't supported by this driver */
1287 termios->c_cflag &= ~CMSPAR;
1288
1289 if ((termios->c_cflag & PARENB) == PARENB) {
1290 symb_bit++;
1291 if (termios->c_cflag & PARODD) {
1292 lcr |= UART_LCR_PARITY;
1293 lcr &= ~UART_LCR_EPAR;
1294 lcr &= ~UART_LCR_SPAR;
1295 } else {
1296 lcr |= UART_LCR_PARITY;
1297 lcr |= UART_LCR_EPAR;
1298 lcr &= ~UART_LCR_SPAR;
1299 }
1300 }
1301
1302 lcr &= ~UART_LCR_WLEN8;
1303 switch (termios->c_cflag & CSIZE) {
1304 case CS5:
1305 lcr |= UART_LCR_WLEN5;
1306 symb_bit += 5;
1307 break;
1308 case CS6:
1309 lcr |= UART_LCR_WLEN6;
1310 symb_bit += 6;
1311 break;
1312 case CS7:
1313 lcr |= UART_LCR_WLEN7;
1314 symb_bit += 7;
1315 break;
1316 default:
1317 lcr |= UART_LCR_WLEN8;
1318 symb_bit += 8;
1319 break;
1320 }
1321
1322 /* Stop bits */
1323 if (termios->c_cflag & CSTOPB) {
1324 lcr |= UART_LCR_STOP;
1325 symb_bit += 2;
1326 } else {
1327 lcr &= ~UART_LCR_STOP;
1328 symb_bit++;
1329 }
1330
1331 tegra_uart_write(tup, lcr, UART_LCR);
1332 tup->lcr_shadow = lcr;
1333 tup->symb_bit = symb_bit;
1334
1335 /* Baud rate. */
1336 baud = uart_get_baud_rate(u, termios, oldtermios,
1337 parent_clk_rate/max_divider,
1338 parent_clk_rate/16);
1339 spin_unlock_irqrestore(&u->lock, flags);
1340 ret = tegra_set_baudrate(tup, baud);
1341 if (ret < 0) {
1342 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1343 return;
1344 }
1345 if (tty_termios_baud_rate(termios))
1346 tty_termios_encode_baud_rate(termios, baud, baud);
1347 spin_lock_irqsave(&u->lock, flags);
1348
1349 /* Flow control */
1350 if (termios->c_cflag & CRTSCTS) {
1351 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1352 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1353 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1354 /* if top layer has asked to set rts active then do so here */
1355 if (tup->rts_active)
1356 set_rts(tup, true);
1357 } else {
1358 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1359 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1360 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1361 }
1362
1363 /* update the port timeout based on new settings */
1364 uart_update_timeout(u, termios->c_cflag, baud);
1365
1366 /* Make sure all writes have completed */
1367 tegra_uart_read(tup, UART_IER);
1368
1369 /* Re-enable interrupt */
1370 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1371 tegra_uart_read(tup, UART_IER);
1372
1373 tup->uport.ignore_status_mask = 0;
1374 /* Ignore all characters if CREAD is not set */
1375 if ((termios->c_cflag & CREAD) == 0)
1376 tup->uport.ignore_status_mask |= UART_LSR_DR;
1377 if (termios->c_iflag & IGNBRK)
1378 tup->uport.ignore_status_mask |= UART_LSR_BI;
1379
1380 spin_unlock_irqrestore(&u->lock, flags);
1381 }
1382
tegra_uart_type(struct uart_port * u)1383 static const char *tegra_uart_type(struct uart_port *u)
1384 {
1385 return TEGRA_UART_TYPE;
1386 }
1387
1388 static const struct uart_ops tegra_uart_ops = {
1389 .tx_empty = tegra_uart_tx_empty,
1390 .set_mctrl = tegra_uart_set_mctrl,
1391 .get_mctrl = tegra_uart_get_mctrl,
1392 .stop_tx = tegra_uart_stop_tx,
1393 .start_tx = tegra_uart_start_tx,
1394 .stop_rx = tegra_uart_stop_rx,
1395 .flush_buffer = tegra_uart_flush_buffer,
1396 .enable_ms = tegra_uart_enable_ms,
1397 .break_ctl = tegra_uart_break_ctl,
1398 .startup = tegra_uart_startup,
1399 .shutdown = tegra_uart_shutdown,
1400 .set_termios = tegra_uart_set_termios,
1401 .type = tegra_uart_type,
1402 .request_port = tegra_uart_request_port,
1403 .release_port = tegra_uart_release_port,
1404 };
1405
1406 static struct uart_driver tegra_uart_driver = {
1407 .owner = THIS_MODULE,
1408 .driver_name = "tegra_hsuart",
1409 .dev_name = "ttyTHS",
1410 .cons = NULL,
1411 .nr = TEGRA_UART_MAXIMUM,
1412 };
1413
tegra_uart_parse_dt(struct platform_device * pdev,struct tegra_uart_port * tup)1414 static int tegra_uart_parse_dt(struct platform_device *pdev,
1415 struct tegra_uart_port *tup)
1416 {
1417 struct device_node *np = pdev->dev.of_node;
1418 int port;
1419 int ret;
1420 int index;
1421 u32 pval;
1422 int count;
1423 int n_entries;
1424
1425 port = of_alias_get_id(np, "serial");
1426 if (port < 0) {
1427 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1428 return port;
1429 }
1430 tup->uport.line = port;
1431
1432 tup->enable_modem_interrupt = of_property_read_bool(np,
1433 "nvidia,enable-modem-interrupt");
1434
1435 index = of_property_match_string(np, "dma-names", "rx");
1436 if (index < 0) {
1437 tup->use_rx_pio = true;
1438 dev_info(&pdev->dev, "RX in PIO mode\n");
1439 }
1440 index = of_property_match_string(np, "dma-names", "tx");
1441 if (index < 0) {
1442 tup->use_tx_pio = true;
1443 dev_info(&pdev->dev, "TX in PIO mode\n");
1444 }
1445
1446 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1447 if (n_entries > 0) {
1448 tup->n_adjustable_baud_rates = n_entries / 3;
1449 tup->baud_tolerance =
1450 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1451 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1452 if (!tup->baud_tolerance)
1453 return -ENOMEM;
1454 for (count = 0, index = 0; count < n_entries; count += 3,
1455 index++) {
1456 ret =
1457 of_property_read_u32_index(np,
1458 "nvidia,adjust-baud-rates",
1459 count, &pval);
1460 if (!ret)
1461 tup->baud_tolerance[index].lower_range_baud =
1462 pval;
1463 ret =
1464 of_property_read_u32_index(np,
1465 "nvidia,adjust-baud-rates",
1466 count + 1, &pval);
1467 if (!ret)
1468 tup->baud_tolerance[index].upper_range_baud =
1469 pval;
1470 ret =
1471 of_property_read_u32_index(np,
1472 "nvidia,adjust-baud-rates",
1473 count + 2, &pval);
1474 if (!ret)
1475 tup->baud_tolerance[index].tolerance =
1476 (s32)pval;
1477 }
1478 } else {
1479 tup->n_adjustable_baud_rates = 0;
1480 }
1481
1482 return 0;
1483 }
1484
1485 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1486 .tx_fifo_full_status = false,
1487 .allow_txfifo_reset_fifo_mode = true,
1488 .support_clk_src_div = false,
1489 .fifo_mode_enable_status = false,
1490 .uart_max_port = 5,
1491 .max_dma_burst_bytes = 4,
1492 .error_tolerance_low_range = 0,
1493 .error_tolerance_high_range = 4,
1494 };
1495
1496 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1497 .tx_fifo_full_status = true,
1498 .allow_txfifo_reset_fifo_mode = false,
1499 .support_clk_src_div = true,
1500 .fifo_mode_enable_status = false,
1501 .uart_max_port = 5,
1502 .max_dma_burst_bytes = 4,
1503 .error_tolerance_low_range = 0,
1504 .error_tolerance_high_range = 4,
1505 };
1506
1507 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1508 .tx_fifo_full_status = true,
1509 .allow_txfifo_reset_fifo_mode = false,
1510 .support_clk_src_div = true,
1511 .fifo_mode_enable_status = true,
1512 .uart_max_port = 8,
1513 .max_dma_burst_bytes = 8,
1514 .error_tolerance_low_range = 0,
1515 .error_tolerance_high_range = 4,
1516 };
1517
1518 static struct tegra_uart_chip_data tegra194_uart_chip_data = {
1519 .tx_fifo_full_status = true,
1520 .allow_txfifo_reset_fifo_mode = false,
1521 .support_clk_src_div = true,
1522 .fifo_mode_enable_status = true,
1523 .uart_max_port = 8,
1524 .max_dma_burst_bytes = 8,
1525 .error_tolerance_low_range = -2,
1526 .error_tolerance_high_range = 2,
1527 };
1528
1529 static const struct of_device_id tegra_uart_of_match[] = {
1530 {
1531 .compatible = "nvidia,tegra30-hsuart",
1532 .data = &tegra30_uart_chip_data,
1533 }, {
1534 .compatible = "nvidia,tegra20-hsuart",
1535 .data = &tegra20_uart_chip_data,
1536 }, {
1537 .compatible = "nvidia,tegra186-hsuart",
1538 .data = &tegra186_uart_chip_data,
1539 }, {
1540 .compatible = "nvidia,tegra194-hsuart",
1541 .data = &tegra194_uart_chip_data,
1542 }, {
1543 },
1544 };
1545 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1546
tegra_uart_probe(struct platform_device * pdev)1547 static int tegra_uart_probe(struct platform_device *pdev)
1548 {
1549 struct tegra_uart_port *tup;
1550 struct uart_port *u;
1551 struct resource *resource;
1552 int ret;
1553 const struct tegra_uart_chip_data *cdata;
1554 const struct of_device_id *match;
1555
1556 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1557 if (!match) {
1558 dev_err(&pdev->dev, "Error: No device match found\n");
1559 return -ENODEV;
1560 }
1561 cdata = match->data;
1562
1563 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1564 if (!tup) {
1565 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1566 return -ENOMEM;
1567 }
1568
1569 ret = tegra_uart_parse_dt(pdev, tup);
1570 if (ret < 0)
1571 return ret;
1572
1573 u = &tup->uport;
1574 u->dev = &pdev->dev;
1575 u->ops = &tegra_uart_ops;
1576 u->type = PORT_TEGRA;
1577 u->fifosize = 32;
1578 tup->cdata = cdata;
1579
1580 platform_set_drvdata(pdev, tup);
1581 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1582 if (!resource) {
1583 dev_err(&pdev->dev, "No IO memory resource\n");
1584 return -ENODEV;
1585 }
1586
1587 u->mapbase = resource->start;
1588 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1589 if (IS_ERR(u->membase))
1590 return PTR_ERR(u->membase);
1591
1592 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1593 if (IS_ERR(tup->uart_clk)) {
1594 dev_err(&pdev->dev, "Couldn't get the clock\n");
1595 return PTR_ERR(tup->uart_clk);
1596 }
1597
1598 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1599 if (IS_ERR(tup->rst)) {
1600 dev_err(&pdev->dev, "Couldn't get the reset\n");
1601 return PTR_ERR(tup->rst);
1602 }
1603
1604 u->iotype = UPIO_MEM32;
1605 ret = platform_get_irq(pdev, 0);
1606 if (ret < 0)
1607 return ret;
1608 u->irq = ret;
1609 u->regshift = 2;
1610 ret = uart_add_one_port(&tegra_uart_driver, u);
1611 if (ret < 0) {
1612 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1613 return ret;
1614 }
1615 return ret;
1616 }
1617
tegra_uart_remove(struct platform_device * pdev)1618 static int tegra_uart_remove(struct platform_device *pdev)
1619 {
1620 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1621 struct uart_port *u = &tup->uport;
1622
1623 uart_remove_one_port(&tegra_uart_driver, u);
1624 return 0;
1625 }
1626
1627 #ifdef CONFIG_PM_SLEEP
tegra_uart_suspend(struct device * dev)1628 static int tegra_uart_suspend(struct device *dev)
1629 {
1630 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1631 struct uart_port *u = &tup->uport;
1632
1633 return uart_suspend_port(&tegra_uart_driver, u);
1634 }
1635
tegra_uart_resume(struct device * dev)1636 static int tegra_uart_resume(struct device *dev)
1637 {
1638 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1639 struct uart_port *u = &tup->uport;
1640
1641 return uart_resume_port(&tegra_uart_driver, u);
1642 }
1643 #endif
1644
1645 static const struct dev_pm_ops tegra_uart_pm_ops = {
1646 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1647 };
1648
1649 static struct platform_driver tegra_uart_platform_driver = {
1650 .probe = tegra_uart_probe,
1651 .remove = tegra_uart_remove,
1652 .driver = {
1653 .name = "serial-tegra",
1654 .of_match_table = tegra_uart_of_match,
1655 .pm = &tegra_uart_pm_ops,
1656 },
1657 };
1658
tegra_uart_init(void)1659 static int __init tegra_uart_init(void)
1660 {
1661 int ret;
1662 struct device_node *node;
1663 const struct of_device_id *match = NULL;
1664 const struct tegra_uart_chip_data *cdata = NULL;
1665
1666 node = of_find_matching_node(NULL, tegra_uart_of_match);
1667 if (node)
1668 match = of_match_node(tegra_uart_of_match, node);
1669 if (match)
1670 cdata = match->data;
1671 if (cdata)
1672 tegra_uart_driver.nr = cdata->uart_max_port;
1673
1674 ret = uart_register_driver(&tegra_uart_driver);
1675 if (ret < 0) {
1676 pr_err("Could not register %s driver\n",
1677 tegra_uart_driver.driver_name);
1678 return ret;
1679 }
1680
1681 ret = platform_driver_register(&tegra_uart_platform_driver);
1682 if (ret < 0) {
1683 pr_err("Uart platform driver register failed, e = %d\n", ret);
1684 uart_unregister_driver(&tegra_uart_driver);
1685 return ret;
1686 }
1687 return 0;
1688 }
1689
tegra_uart_exit(void)1690 static void __exit tegra_uart_exit(void)
1691 {
1692 pr_info("Unloading tegra uart driver\n");
1693 platform_driver_unregister(&tegra_uart_platform_driver);
1694 uart_unregister_driver(&tegra_uart_driver);
1695 }
1696
1697 module_init(tegra_uart_init);
1698 module_exit(tegra_uart_exit);
1699
1700 MODULE_ALIAS("platform:serial-tegra");
1701 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1702 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1703 MODULE_LICENSE("GPL v2");
1704
