1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2021-2022 Linaro Ltd
5 * Author: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, based on
6 * previous work of Thara Gopinath and msm-4.9 downstream sources.
7 */
8
9 #include <linux/err.h>
10 #include <linux/interconnect.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/sizes.h>
20
21 /*
22 * The BWMON samples data throughput within 'sample_ms' time. With three
23 * configurable thresholds (Low, Medium and High) gives four windows (called
24 * zones) of current bandwidth:
25 *
26 * Zone 0: byte count < THRES_LO
27 * Zone 1: THRES_LO < byte count < THRES_MED
28 * Zone 2: THRES_MED < byte count < THRES_HIGH
29 * Zone 3: THRES_HIGH < byte count
30 *
31 * Zones 0 and 2 are not used by this driver.
32 */
33
34 /* Internal sampling clock frequency */
35 #define HW_TIMER_HZ 19200000
36
37 #define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008
38 #define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c
39 /*
40 * All values here and further are matching regmap fields, so without absolute
41 * register offsets.
42 */
43 #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0)
44
45 #define BWMON_V4_IRQ_STATUS 0x100
46 #define BWMON_V4_IRQ_CLEAR 0x108
47
48 #define BWMON_V4_IRQ_ENABLE 0x10c
49 #define BWMON_IRQ_ENABLE_MASK (BIT(1) | BIT(3))
50 #define BWMON_V5_IRQ_STATUS 0x000
51 #define BWMON_V5_IRQ_CLEAR 0x008
52 #define BWMON_V5_IRQ_ENABLE 0x00c
53
54 #define BWMON_V4_ENABLE 0x2a0
55 #define BWMON_V5_ENABLE 0x010
56 #define BWMON_ENABLE_ENABLE BIT(0)
57
58 #define BWMON_V4_CLEAR 0x2a4
59 #define BWMON_V5_CLEAR 0x014
60 #define BWMON_CLEAR_CLEAR BIT(0)
61 #define BWMON_CLEAR_CLEAR_ALL BIT(1)
62
63 #define BWMON_V4_SAMPLE_WINDOW 0x2a8
64 #define BWMON_V5_SAMPLE_WINDOW 0x020
65
66 #define BWMON_V4_THRESHOLD_HIGH 0x2ac
67 #define BWMON_V4_THRESHOLD_MED 0x2b0
68 #define BWMON_V4_THRESHOLD_LOW 0x2b4
69 #define BWMON_V5_THRESHOLD_HIGH 0x024
70 #define BWMON_V5_THRESHOLD_MED 0x028
71 #define BWMON_V5_THRESHOLD_LOW 0x02c
72
73 #define BWMON_V4_ZONE_ACTIONS 0x2b8
74 #define BWMON_V5_ZONE_ACTIONS 0x030
75 /*
76 * Actions to perform on some zone 'z' when current zone hits the threshold:
77 * Increment counter of zone 'z'
78 */
79 #define BWMON_ZONE_ACTIONS_INCREMENT(z) (0x2 << ((z) * 2))
80 /* Clear counter of zone 'z' */
81 #define BWMON_ZONE_ACTIONS_CLEAR(z) (0x1 << ((z) * 2))
82
83 /* Zone 0 threshold hit: Clear zone count */
84 #define BWMON_ZONE_ACTIONS_ZONE0 (BWMON_ZONE_ACTIONS_CLEAR(0))
85
86 /* Zone 1 threshold hit: Increment zone count & clear lower zones */
87 #define BWMON_ZONE_ACTIONS_ZONE1 (BWMON_ZONE_ACTIONS_INCREMENT(1) | \
88 BWMON_ZONE_ACTIONS_CLEAR(0))
89
90 /* Zone 2 threshold hit: Increment zone count & clear lower zones */
91 #define BWMON_ZONE_ACTIONS_ZONE2 (BWMON_ZONE_ACTIONS_INCREMENT(2) | \
92 BWMON_ZONE_ACTIONS_CLEAR(1) | \
93 BWMON_ZONE_ACTIONS_CLEAR(0))
94
95 /* Zone 3 threshold hit: Increment zone count & clear lower zones */
96 #define BWMON_ZONE_ACTIONS_ZONE3 (BWMON_ZONE_ACTIONS_INCREMENT(3) | \
97 BWMON_ZONE_ACTIONS_CLEAR(2) | \
98 BWMON_ZONE_ACTIONS_CLEAR(1) | \
99 BWMON_ZONE_ACTIONS_CLEAR(0))
100
101 /*
102 * There is no clear documentation/explanation of BWMON_V4_THRESHOLD_COUNT
103 * register. Based on observations, this is number of times one threshold has to
104 * be reached, to trigger interrupt in given zone.
105 *
106 * 0xff are maximum values meant to ignore the zones 0 and 2.
107 */
108 #define BWMON_V4_THRESHOLD_COUNT 0x2bc
109 #define BWMON_V5_THRESHOLD_COUNT 0x034
110 #define BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT 0xff
111 #define BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT 0xff
112
113 #define BWMON_V4_ZONE_MAX(zone) (0x2e0 + 4 * (zone))
114 #define BWMON_V5_ZONE_MAX(zone) (0x044 + 4 * (zone))
115
116 /* Quirks for specific BWMON types */
117 #define BWMON_HAS_GLOBAL_IRQ BIT(0)
118 #define BWMON_NEEDS_FORCE_CLEAR BIT(1)
119
120 enum bwmon_fields {
121 F_GLOBAL_IRQ_CLEAR,
122 F_GLOBAL_IRQ_ENABLE,
123 F_IRQ_STATUS,
124 F_IRQ_CLEAR,
125 F_IRQ_ENABLE,
126 F_ENABLE,
127 F_CLEAR,
128 F_SAMPLE_WINDOW,
129 F_THRESHOLD_HIGH,
130 F_THRESHOLD_MED,
131 F_THRESHOLD_LOW,
132 F_ZONE_ACTIONS_ZONE0,
133 F_ZONE_ACTIONS_ZONE1,
134 F_ZONE_ACTIONS_ZONE2,
135 F_ZONE_ACTIONS_ZONE3,
136 F_THRESHOLD_COUNT_ZONE0,
137 F_THRESHOLD_COUNT_ZONE1,
138 F_THRESHOLD_COUNT_ZONE2,
139 F_THRESHOLD_COUNT_ZONE3,
140 F_ZONE0_MAX,
141 F_ZONE1_MAX,
142 F_ZONE2_MAX,
143 F_ZONE3_MAX,
144
145 F_NUM_FIELDS
146 };
147
148 struct icc_bwmon_data {
149 unsigned int sample_ms;
150 unsigned int count_unit_kb; /* kbytes */
151 unsigned int default_highbw_kbps;
152 unsigned int default_medbw_kbps;
153 unsigned int default_lowbw_kbps;
154 u8 zone1_thres_count;
155 u8 zone3_thres_count;
156 unsigned int quirks;
157
158 const struct regmap_config *regmap_cfg;
159 const struct reg_field *regmap_fields;
160 };
161
162 struct icc_bwmon {
163 struct device *dev;
164 const struct icc_bwmon_data *data;
165 int irq;
166
167 struct regmap *regmap;
168 struct regmap_field *regs[F_NUM_FIELDS];
169
170 unsigned int max_bw_kbps;
171 unsigned int min_bw_kbps;
172 unsigned int target_kbps;
173 unsigned int current_kbps;
174 };
175
176 /* BWMON v4 */
177 static const struct reg_field msm8998_bwmon_reg_fields[] = {
178 [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0),
179 [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0),
180 [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7),
181 [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7),
182 [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7),
183 /* F_ENABLE covers entire register to disable other features */
184 [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31),
185 [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1),
186 [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23),
187 [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11),
188 [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11),
189 [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11),
190 [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7),
191 [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15),
192 [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23),
193 [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31),
194 [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7),
195 [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15),
196 [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23),
197 [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31),
198 [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11),
199 [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11),
200 [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11),
201 [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11),
202 };
203
204 static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = {
205 regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR),
206 regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR),
207 regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR),
208 };
209
210 static const struct regmap_access_table msm8998_bwmon_reg_read_table = {
211 .no_ranges = msm8998_bwmon_reg_noread_ranges,
212 .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_reg_noread_ranges),
213 };
214
215 static const struct regmap_range msm8998_bwmon_reg_volatile_ranges[] = {
216 regmap_reg_range(BWMON_V4_IRQ_STATUS, BWMON_V4_IRQ_STATUS),
217 regmap_reg_range(BWMON_V4_ZONE_MAX(0), BWMON_V4_ZONE_MAX(3)),
218 };
219
220 static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = {
221 .yes_ranges = msm8998_bwmon_reg_volatile_ranges,
222 .n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges),
223 };
224
225 /*
226 * Fill the cache for non-readable registers only as rest does not really
227 * matter and can be read from the device.
228 */
229 static const struct reg_default msm8998_bwmon_reg_defaults[] = {
230 { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 },
231 { BWMON_V4_IRQ_CLEAR, 0x0 },
232 { BWMON_V4_CLEAR, 0x0 },
233 };
234
235 static const struct regmap_config msm8998_bwmon_regmap_cfg = {
236 .reg_bits = 32,
237 .reg_stride = 4,
238 .val_bits = 32,
239 /*
240 * No concurrent access expected - driver has one interrupt handler,
241 * regmap is not shared, no driver or user-space API.
242 */
243 .disable_locking = true,
244 .rd_table = &msm8998_bwmon_reg_read_table,
245 .volatile_table = &msm8998_bwmon_reg_volatile_table,
246 .reg_defaults = msm8998_bwmon_reg_defaults,
247 .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_reg_defaults),
248 /*
249 * Cache is necessary for using regmap fields with non-readable
250 * registers.
251 */
252 .cache_type = REGCACHE_RBTREE,
253 };
254
255 /* BWMON v5 */
256 static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = {
257 [F_GLOBAL_IRQ_CLEAR] = {},
258 [F_GLOBAL_IRQ_ENABLE] = {},
259 [F_IRQ_STATUS] = REG_FIELD(BWMON_V5_IRQ_STATUS, 0, 3),
260 [F_IRQ_CLEAR] = REG_FIELD(BWMON_V5_IRQ_CLEAR, 0, 3),
261 [F_IRQ_ENABLE] = REG_FIELD(BWMON_V5_IRQ_ENABLE, 0, 3),
262 /* F_ENABLE covers entire register to disable other features */
263 [F_ENABLE] = REG_FIELD(BWMON_V5_ENABLE, 0, 31),
264 [F_CLEAR] = REG_FIELD(BWMON_V5_CLEAR, 0, 1),
265 [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V5_SAMPLE_WINDOW, 0, 19),
266 [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V5_THRESHOLD_HIGH, 0, 11),
267 [F_THRESHOLD_MED] = REG_FIELD(BWMON_V5_THRESHOLD_MED, 0, 11),
268 [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V5_THRESHOLD_LOW, 0, 11),
269 [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 0, 7),
270 [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 8, 15),
271 [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 16, 23),
272 [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V5_ZONE_ACTIONS, 24, 31),
273 [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 0, 7),
274 [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 8, 15),
275 [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 16, 23),
276 [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V5_THRESHOLD_COUNT, 24, 31),
277 [F_ZONE0_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(0), 0, 11),
278 [F_ZONE1_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(1), 0, 11),
279 [F_ZONE2_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(2), 0, 11),
280 [F_ZONE3_MAX] = REG_FIELD(BWMON_V5_ZONE_MAX(3), 0, 11),
281 };
282
283 static const struct regmap_range sdm845_llcc_bwmon_reg_noread_ranges[] = {
284 regmap_reg_range(BWMON_V5_IRQ_CLEAR, BWMON_V5_IRQ_CLEAR),
285 regmap_reg_range(BWMON_V5_CLEAR, BWMON_V5_CLEAR),
286 };
287
288 static const struct regmap_access_table sdm845_llcc_bwmon_reg_read_table = {
289 .no_ranges = sdm845_llcc_bwmon_reg_noread_ranges,
290 .n_no_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_noread_ranges),
291 };
292
293 static const struct regmap_range sdm845_llcc_bwmon_reg_volatile_ranges[] = {
294 regmap_reg_range(BWMON_V5_IRQ_STATUS, BWMON_V5_IRQ_STATUS),
295 regmap_reg_range(BWMON_V5_ZONE_MAX(0), BWMON_V5_ZONE_MAX(3)),
296 };
297
298 static const struct regmap_access_table sdm845_llcc_bwmon_reg_volatile_table = {
299 .yes_ranges = sdm845_llcc_bwmon_reg_volatile_ranges,
300 .n_yes_ranges = ARRAY_SIZE(sdm845_llcc_bwmon_reg_volatile_ranges),
301 };
302
303 /*
304 * Fill the cache for non-readable registers only as rest does not really
305 * matter and can be read from the device.
306 */
307 static const struct reg_default sdm845_llcc_bwmon_reg_defaults[] = {
308 { BWMON_V5_IRQ_CLEAR, 0x0 },
309 { BWMON_V5_CLEAR, 0x0 },
310 };
311
312 static const struct regmap_config sdm845_llcc_bwmon_regmap_cfg = {
313 .reg_bits = 32,
314 .reg_stride = 4,
315 .val_bits = 32,
316 /*
317 * No concurrent access expected - driver has one interrupt handler,
318 * regmap is not shared, no driver or user-space API.
319 */
320 .disable_locking = true,
321 .rd_table = &sdm845_llcc_bwmon_reg_read_table,
322 .volatile_table = &sdm845_llcc_bwmon_reg_volatile_table,
323 .reg_defaults = sdm845_llcc_bwmon_reg_defaults,
324 .num_reg_defaults = ARRAY_SIZE(sdm845_llcc_bwmon_reg_defaults),
325 /*
326 * Cache is necessary for using regmap fields with non-readable
327 * registers.
328 */
329 .cache_type = REGCACHE_RBTREE,
330 };
331
bwmon_clear_counters(struct icc_bwmon * bwmon,bool clear_all)332 static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all)
333 {
334 unsigned int val = BWMON_CLEAR_CLEAR;
335
336 if (clear_all)
337 val |= BWMON_CLEAR_CLEAR_ALL;
338 /*
339 * Clear counters. The order and barriers are
340 * important. Quoting downstream Qualcomm msm-4.9 tree:
341 *
342 * The counter clear and IRQ clear bits are not in the same 4KB
343 * region. So, we need to make sure the counter clear is completed
344 * before we try to clear the IRQ or do any other counter operations.
345 */
346 regmap_field_force_write(bwmon->regs[F_CLEAR], val);
347 if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR)
348 regmap_field_force_write(bwmon->regs[F_CLEAR], 0);
349 }
350
bwmon_clear_irq(struct icc_bwmon * bwmon)351 static void bwmon_clear_irq(struct icc_bwmon *bwmon)
352 {
353 /*
354 * Clear zone and global interrupts. The order and barriers are
355 * important. Quoting downstream Qualcomm msm-4.9 tree:
356 *
357 * Synchronize the local interrupt clear in mon_irq_clear()
358 * with the global interrupt clear here. Otherwise, the CPU
359 * may reorder the two writes and clear the global interrupt
360 * before the local interrupt, causing the global interrupt
361 * to be retriggered by the local interrupt still being high.
362 *
363 * Similarly, because the global registers are in a different
364 * region than the local registers, we need to ensure any register
365 * writes to enable the monitor after this call are ordered with the
366 * clearing here so that local writes don't happen before the
367 * interrupt is cleared.
368 */
369 regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], BWMON_IRQ_ENABLE_MASK);
370 if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR)
371 regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0);
372 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
373 regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR],
374 BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE);
375 }
376
bwmon_disable(struct icc_bwmon * bwmon)377 static void bwmon_disable(struct icc_bwmon *bwmon)
378 {
379 /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */
380 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
381 regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0);
382 regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0);
383
384 /*
385 * Disable bwmon. Must happen before bwmon_clear_irq() to avoid spurious
386 * IRQ.
387 */
388 regmap_field_write(bwmon->regs[F_ENABLE], 0x0);
389 }
390
bwmon_enable(struct icc_bwmon * bwmon,unsigned int irq_enable)391 static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable)
392 {
393 /* Enable interrupts */
394 if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ)
395 regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE],
396 BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE);
397 regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable);
398
399 /* Enable bwmon */
400 regmap_field_write(bwmon->regs[F_ENABLE], BWMON_ENABLE_ENABLE);
401 }
402
bwmon_kbps_to_count(struct icc_bwmon * bwmon,unsigned int kbps)403 static unsigned int bwmon_kbps_to_count(struct icc_bwmon *bwmon,
404 unsigned int kbps)
405 {
406 return kbps / bwmon->data->count_unit_kb;
407 }
408
bwmon_set_threshold(struct icc_bwmon * bwmon,struct regmap_field * reg,unsigned int kbps)409 static void bwmon_set_threshold(struct icc_bwmon *bwmon,
410 struct regmap_field *reg, unsigned int kbps)
411 {
412 unsigned int thres;
413
414 thres = mult_frac(bwmon_kbps_to_count(bwmon, kbps),
415 bwmon->data->sample_ms, MSEC_PER_SEC);
416 regmap_field_write(reg, thres);
417 }
418
bwmon_start(struct icc_bwmon * bwmon)419 static void bwmon_start(struct icc_bwmon *bwmon)
420 {
421 const struct icc_bwmon_data *data = bwmon->data;
422 int window;
423
424 bwmon_clear_counters(bwmon, true);
425
426 window = mult_frac(bwmon->data->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC);
427 /* Maximum sampling window: 0xffffff for v4 and 0xfffff for v5 */
428 regmap_field_write(bwmon->regs[F_SAMPLE_WINDOW], window);
429
430 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH],
431 data->default_highbw_kbps);
432 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED],
433 data->default_medbw_kbps);
434 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW],
435 data->default_lowbw_kbps);
436
437 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE0],
438 BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT);
439 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE1],
440 data->zone1_thres_count);
441 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE2],
442 BWMON_THRESHOLD_COUNT_ZONE2_DEFAULT);
443 regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE3],
444 data->zone3_thres_count);
445
446 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE0],
447 BWMON_ZONE_ACTIONS_ZONE0);
448 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE1],
449 BWMON_ZONE_ACTIONS_ZONE1);
450 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE2],
451 BWMON_ZONE_ACTIONS_ZONE2);
452 regmap_field_write(bwmon->regs[F_ZONE_ACTIONS_ZONE3],
453 BWMON_ZONE_ACTIONS_ZONE3);
454
455 bwmon_clear_irq(bwmon);
456 bwmon_enable(bwmon, BWMON_IRQ_ENABLE_MASK);
457 }
458
bwmon_intr(int irq,void * dev_id)459 static irqreturn_t bwmon_intr(int irq, void *dev_id)
460 {
461 struct icc_bwmon *bwmon = dev_id;
462 unsigned int status, max;
463 int zone;
464
465 if (regmap_field_read(bwmon->regs[F_IRQ_STATUS], &status))
466 return IRQ_NONE;
467
468 status &= BWMON_IRQ_ENABLE_MASK;
469 if (!status) {
470 /*
471 * Only zone 1 and zone 3 interrupts are enabled but zone 2
472 * threshold could be hit and trigger interrupt even if not
473 * enabled.
474 * Such spurious interrupt might come with valuable max count or
475 * not, so solution would be to always check all
476 * BWMON_ZONE_MAX() registers to find the highest value.
477 * Such case is currently ignored.
478 */
479 return IRQ_NONE;
480 }
481
482 bwmon_disable(bwmon);
483
484 zone = get_bitmask_order(status) - 1;
485 /*
486 * Zone max bytes count register returns count units within sampling
487 * window. Downstream kernel for BWMONv4 (called BWMON type 2 in
488 * downstream) always increments the max bytes count by one.
489 */
490 if (regmap_field_read(bwmon->regs[F_ZONE0_MAX + zone], &max))
491 return IRQ_NONE;
492
493 max += 1;
494 max *= bwmon->data->count_unit_kb;
495 bwmon->target_kbps = mult_frac(max, MSEC_PER_SEC, bwmon->data->sample_ms);
496
497 return IRQ_WAKE_THREAD;
498 }
499
bwmon_intr_thread(int irq,void * dev_id)500 static irqreturn_t bwmon_intr_thread(int irq, void *dev_id)
501 {
502 struct icc_bwmon *bwmon = dev_id;
503 unsigned int irq_enable = 0;
504 struct dev_pm_opp *opp, *target_opp;
505 unsigned int bw_kbps, up_kbps, down_kbps;
506
507 bw_kbps = bwmon->target_kbps;
508
509 target_opp = dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_kbps, 0);
510 if (IS_ERR(target_opp) && PTR_ERR(target_opp) == -ERANGE)
511 target_opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0);
512
513 bwmon->target_kbps = bw_kbps;
514
515 bw_kbps--;
516 opp = dev_pm_opp_find_bw_floor(bwmon->dev, &bw_kbps, 0);
517 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
518 down_kbps = bwmon->target_kbps;
519 else
520 down_kbps = bw_kbps;
521
522 up_kbps = bwmon->target_kbps + 1;
523
524 if (bwmon->target_kbps >= bwmon->max_bw_kbps)
525 irq_enable = BIT(1);
526 else if (bwmon->target_kbps <= bwmon->min_bw_kbps)
527 irq_enable = BIT(3);
528 else
529 irq_enable = BWMON_IRQ_ENABLE_MASK;
530
531 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH],
532 up_kbps);
533 bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED],
534 down_kbps);
535 bwmon_clear_counters(bwmon, false);
536 bwmon_clear_irq(bwmon);
537 bwmon_enable(bwmon, irq_enable);
538
539 if (bwmon->target_kbps == bwmon->current_kbps)
540 goto out;
541
542 dev_pm_opp_set_opp(bwmon->dev, target_opp);
543 bwmon->current_kbps = bwmon->target_kbps;
544
545 out:
546 dev_pm_opp_put(target_opp);
547 if (!IS_ERR(opp))
548 dev_pm_opp_put(opp);
549
550 return IRQ_HANDLED;
551 }
552
bwmon_init_regmap(struct platform_device * pdev,struct icc_bwmon * bwmon)553 static int bwmon_init_regmap(struct platform_device *pdev,
554 struct icc_bwmon *bwmon)
555 {
556 struct device *dev = &pdev->dev;
557 void __iomem *base;
558 struct regmap *map;
559
560 base = devm_platform_ioremap_resource(pdev, 0);
561 if (IS_ERR(base))
562 return dev_err_probe(dev, PTR_ERR(base),
563 "failed to map bwmon registers\n");
564
565 map = devm_regmap_init_mmio(dev, base, bwmon->data->regmap_cfg);
566 if (IS_ERR(map))
567 return dev_err_probe(dev, PTR_ERR(map),
568 "failed to initialize regmap\n");
569
570 BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS);
571 BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS);
572
573 return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs,
574 bwmon->data->regmap_fields,
575 F_NUM_FIELDS);
576 }
577
bwmon_probe(struct platform_device * pdev)578 static int bwmon_probe(struct platform_device *pdev)
579 {
580 struct device *dev = &pdev->dev;
581 struct dev_pm_opp *opp;
582 struct icc_bwmon *bwmon;
583 int ret;
584
585 bwmon = devm_kzalloc(dev, sizeof(*bwmon), GFP_KERNEL);
586 if (!bwmon)
587 return -ENOMEM;
588
589 bwmon->data = of_device_get_match_data(dev);
590
591 ret = bwmon_init_regmap(pdev, bwmon);
592 if (ret)
593 return ret;
594
595 bwmon->irq = platform_get_irq(pdev, 0);
596 if (bwmon->irq < 0)
597 return bwmon->irq;
598
599 ret = devm_pm_opp_of_add_table(dev);
600 if (ret)
601 return dev_err_probe(dev, ret, "failed to add OPP table\n");
602
603 bwmon->max_bw_kbps = UINT_MAX;
604 opp = dev_pm_opp_find_bw_floor(dev, &bwmon->max_bw_kbps, 0);
605 if (IS_ERR(opp))
606 return dev_err_probe(dev, ret, "failed to find max peak bandwidth\n");
607
608 bwmon->min_bw_kbps = 0;
609 opp = dev_pm_opp_find_bw_ceil(dev, &bwmon->min_bw_kbps, 0);
610 if (IS_ERR(opp))
611 return dev_err_probe(dev, ret, "failed to find min peak bandwidth\n");
612
613 bwmon->dev = dev;
614
615 bwmon_disable(bwmon);
616 ret = devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr,
617 bwmon_intr_thread,
618 IRQF_ONESHOT, dev_name(dev), bwmon);
619 if (ret)
620 return dev_err_probe(dev, ret, "failed to request IRQ\n");
621
622 platform_set_drvdata(pdev, bwmon);
623 bwmon_start(bwmon);
624
625 return 0;
626 }
627
bwmon_remove(struct platform_device * pdev)628 static int bwmon_remove(struct platform_device *pdev)
629 {
630 struct icc_bwmon *bwmon = platform_get_drvdata(pdev);
631
632 bwmon_disable(bwmon);
633
634 return 0;
635 }
636
637 static const struct icc_bwmon_data msm8998_bwmon_data = {
638 .sample_ms = 4,
639 .count_unit_kb = 64,
640 .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
641 .default_medbw_kbps = 512 * 1024, /* 512 MBps */
642 .default_lowbw_kbps = 0,
643 .zone1_thres_count = 16,
644 .zone3_thres_count = 1,
645 .quirks = BWMON_HAS_GLOBAL_IRQ,
646 .regmap_fields = msm8998_bwmon_reg_fields,
647 .regmap_cfg = &msm8998_bwmon_regmap_cfg,
648 };
649
650 static const struct icc_bwmon_data sdm845_llcc_bwmon_data = {
651 .sample_ms = 4,
652 .count_unit_kb = 1024,
653 .default_highbw_kbps = 800 * 1024, /* 800 MBps */
654 .default_medbw_kbps = 256 * 1024, /* 256 MBps */
655 .default_lowbw_kbps = 0,
656 .zone1_thres_count = 16,
657 .zone3_thres_count = 1,
658 .regmap_fields = sdm845_llcc_bwmon_reg_fields,
659 .regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg,
660 };
661
662 static const struct icc_bwmon_data sc7280_llcc_bwmon_data = {
663 .sample_ms = 4,
664 .count_unit_kb = 64,
665 .default_highbw_kbps = 800 * 1024, /* 800 MBps */
666 .default_medbw_kbps = 256 * 1024, /* 256 MBps */
667 .default_lowbw_kbps = 0,
668 .zone1_thres_count = 16,
669 .zone3_thres_count = 1,
670 .quirks = BWMON_NEEDS_FORCE_CLEAR,
671 .regmap_fields = sdm845_llcc_bwmon_reg_fields,
672 .regmap_cfg = &sdm845_llcc_bwmon_regmap_cfg,
673 };
674
675 static const struct of_device_id bwmon_of_match[] = {
676 {
677 .compatible = "qcom,msm8998-bwmon",
678 .data = &msm8998_bwmon_data
679 }, {
680 .compatible = "qcom,sdm845-llcc-bwmon",
681 .data = &sdm845_llcc_bwmon_data
682 }, {
683 .compatible = "qcom,sc7280-llcc-bwmon",
684 .data = &sc7280_llcc_bwmon_data
685 },
686 {}
687 };
688 MODULE_DEVICE_TABLE(of, bwmon_of_match);
689
690 static struct platform_driver bwmon_driver = {
691 .probe = bwmon_probe,
692 .remove = bwmon_remove,
693 .driver = {
694 .name = "qcom-bwmon",
695 .of_match_table = bwmon_of_match,
696 },
697 };
698 module_platform_driver(bwmon_driver);
699
700 MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
701 MODULE_DESCRIPTION("QCOM BWMON driver");
702 MODULE_LICENSE("GPL");
703
