1 /*
2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
3 * chips.
4 *
5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
7 *
8 * References:
9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
12 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/bcd.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/rtc.h>
27 #include <linux/workqueue.h>
28
29 #include <linux/rtc/ds1685.h>
30
31 #ifdef CONFIG_PROC_FS
32 #include <linux/proc_fs.h>
33 #endif
34
35
36 /* ----------------------------------------------------------------------- */
37 /* Standard read/write functions if platform does not provide overrides */
38
39 /**
40 * ds1685_read - read a value from an rtc register.
41 * @rtc: pointer to the ds1685 rtc structure.
42 * @reg: the register address to read.
43 */
44 static u8
ds1685_read(struct ds1685_priv * rtc,int reg)45 ds1685_read(struct ds1685_priv *rtc, int reg)
46 {
47 return readb((u8 __iomem *)rtc->regs +
48 (reg * rtc->regstep));
49 }
50
51 /**
52 * ds1685_write - write a value to an rtc register.
53 * @rtc: pointer to the ds1685 rtc structure.
54 * @reg: the register address to write.
55 * @value: value to write to the register.
56 */
57 static void
ds1685_write(struct ds1685_priv * rtc,int reg,u8 value)58 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
59 {
60 writeb(value, ((u8 __iomem *)rtc->regs +
61 (reg * rtc->regstep)));
62 }
63 /* ----------------------------------------------------------------------- */
64
65
66 /* ----------------------------------------------------------------------- */
67 /* Inlined functions */
68
69 /**
70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
71 * @rtc: pointer to the ds1685 rtc structure.
72 * @val: u8 time value to consider converting.
73 * @bcd_mask: u8 mask value if BCD mode is used.
74 * @bin_mask: u8 mask value if BIN mode is used.
75 *
76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
77 */
78 static inline u8
ds1685_rtc_bcd2bin(struct ds1685_priv * rtc,u8 val,u8 bcd_mask,u8 bin_mask)79 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
80 {
81 if (rtc->bcd_mode)
82 return (bcd2bin(val) & bcd_mask);
83
84 return (val & bin_mask);
85 }
86
87 /**
88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
89 * @rtc: pointer to the ds1685 rtc structure.
90 * @val: u8 time value to consider converting.
91 * @bin_mask: u8 mask value if BIN mode is used.
92 * @bcd_mask: u8 mask value if BCD mode is used.
93 *
94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
95 */
96 static inline u8
ds1685_rtc_bin2bcd(struct ds1685_priv * rtc,u8 val,u8 bin_mask,u8 bcd_mask)97 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
98 {
99 if (rtc->bcd_mode)
100 return (bin2bcd(val) & bcd_mask);
101
102 return (val & bin_mask);
103 }
104
105 /**
106 * s1685_rtc_check_mday - check validity of the day of month.
107 * @rtc: pointer to the ds1685 rtc structure.
108 * @mday: day of month.
109 *
110 * Returns -EDOM if the day of month is not within 1..31 range.
111 */
112 static inline int
ds1685_rtc_check_mday(struct ds1685_priv * rtc,u8 mday)113 ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
114 {
115 if (rtc->bcd_mode) {
116 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
117 return -EDOM;
118 } else {
119 if (mday < 1 || mday > 31)
120 return -EDOM;
121 }
122 return 0;
123 }
124
125 /**
126 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
127 * @rtc: pointer to the ds1685 rtc structure.
128 */
129 static inline void
ds1685_rtc_switch_to_bank0(struct ds1685_priv * rtc)130 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
131 {
132 rtc->write(rtc, RTC_CTRL_A,
133 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
134 }
135
136 /**
137 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
138 * @rtc: pointer to the ds1685 rtc structure.
139 */
140 static inline void
ds1685_rtc_switch_to_bank1(struct ds1685_priv * rtc)141 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
142 {
143 rtc->write(rtc, RTC_CTRL_A,
144 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
145 }
146
147 /**
148 * ds1685_rtc_begin_data_access - prepare the rtc for data access.
149 * @rtc: pointer to the ds1685 rtc structure.
150 *
151 * This takes several steps to prepare the rtc for access to get/set time
152 * and alarm values from the rtc registers:
153 * - Sets the SET bit in Control Register B.
154 * - Reads Ext Control Register 4A and checks the INCR bit.
155 * - If INCR is active, a short delay is added before Ext Control Register 4A
156 * is read again in a loop until INCR is inactive.
157 * - Switches the rtc to bank 1. This allows access to all relevant
158 * data for normal rtc operation, as bank 0 contains only the nvram.
159 */
160 static inline void
ds1685_rtc_begin_data_access(struct ds1685_priv * rtc)161 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
162 {
163 /* Set the SET bit in Ctrl B */
164 rtc->write(rtc, RTC_CTRL_B,
165 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
166
167 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
168 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
169 cpu_relax();
170
171 /* Switch to Bank 1 */
172 ds1685_rtc_switch_to_bank1(rtc);
173 }
174
175 /**
176 * ds1685_rtc_end_data_access - end data access on the rtc.
177 * @rtc: pointer to the ds1685 rtc structure.
178 *
179 * This ends what was started by ds1685_rtc_begin_data_access:
180 * - Switches the rtc back to bank 0.
181 * - Clears the SET bit in Control Register B.
182 */
183 static inline void
ds1685_rtc_end_data_access(struct ds1685_priv * rtc)184 ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
185 {
186 /* Switch back to Bank 0 */
187 ds1685_rtc_switch_to_bank1(rtc);
188
189 /* Clear the SET bit in Ctrl B */
190 rtc->write(rtc, RTC_CTRL_B,
191 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
192 }
193
194 /**
195 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
196 * @rtc: pointer to the ds1685 rtc structure.
197 * @flags: irq flags variable for spin_lock_irqsave.
198 *
199 * This takes several steps to prepare the rtc for access to read just the
200 * control registers:
201 * - Sets a spinlock on the rtc IRQ.
202 * - Switches the rtc to bank 1. This allows access to the two extended
203 * control registers.
204 *
205 * Only use this where you are certain another lock will not be held.
206 */
207 static inline void
ds1685_rtc_begin_ctrl_access(struct ds1685_priv * rtc,unsigned long * flags)208 ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags)
209 {
210 spin_lock_irqsave(&rtc->lock, *flags);
211 ds1685_rtc_switch_to_bank1(rtc);
212 }
213
214 /**
215 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
216 * @rtc: pointer to the ds1685 rtc structure.
217 * @flags: irq flags variable for spin_unlock_irqrestore.
218 *
219 * This ends what was started by ds1685_rtc_begin_ctrl_access:
220 * - Switches the rtc back to bank 0.
221 * - Unsets the spinlock on the rtc IRQ.
222 */
223 static inline void
ds1685_rtc_end_ctrl_access(struct ds1685_priv * rtc,unsigned long flags)224 ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
225 {
226 ds1685_rtc_switch_to_bank0(rtc);
227 spin_unlock_irqrestore(&rtc->lock, flags);
228 }
229
230 /**
231 * ds1685_rtc_get_ssn - retrieve the silicon serial number.
232 * @rtc: pointer to the ds1685 rtc structure.
233 * @ssn: u8 array to hold the bits of the silicon serial number.
234 *
235 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
236 * first byte is the model number, the next six bytes are the serial number
237 * digits, and the final byte is a CRC check byte. Together, they form the
238 * silicon serial number.
239 *
240 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
241 * called first before calling this function, else data will be read out of
242 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
243 */
244 static inline void
ds1685_rtc_get_ssn(struct ds1685_priv * rtc,u8 * ssn)245 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
246 {
247 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
248 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
249 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
250 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
251 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
252 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
253 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
254 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
255 }
256 /* ----------------------------------------------------------------------- */
257
258
259 /* ----------------------------------------------------------------------- */
260 /* Read/Set Time & Alarm functions */
261
262 /**
263 * ds1685_rtc_read_time - reads the time registers.
264 * @dev: pointer to device structure.
265 * @tm: pointer to rtc_time structure.
266 */
267 static int
ds1685_rtc_read_time(struct device * dev,struct rtc_time * tm)268 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
269 {
270 struct ds1685_priv *rtc = dev_get_drvdata(dev);
271 u8 ctrlb, century;
272 u8 seconds, minutes, hours, wday, mday, month, years;
273
274 /* Fetch the time info from the RTC registers. */
275 ds1685_rtc_begin_data_access(rtc);
276 seconds = rtc->read(rtc, RTC_SECS);
277 minutes = rtc->read(rtc, RTC_MINS);
278 hours = rtc->read(rtc, RTC_HRS);
279 wday = rtc->read(rtc, RTC_WDAY);
280 mday = rtc->read(rtc, RTC_MDAY);
281 month = rtc->read(rtc, RTC_MONTH);
282 years = rtc->read(rtc, RTC_YEAR);
283 century = rtc->read(rtc, RTC_CENTURY);
284 ctrlb = rtc->read(rtc, RTC_CTRL_B);
285 ds1685_rtc_end_data_access(rtc);
286
287 /* bcd2bin if needed, perform fixups, and store to rtc_time. */
288 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
289 RTC_YEAR_BIN_MASK);
290 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
291 RTC_CENTURY_MASK);
292 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
293 RTC_SECS_BIN_MASK);
294 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
295 RTC_MINS_BIN_MASK);
296 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
297 RTC_HRS_24_BIN_MASK);
298 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
299 RTC_WDAY_MASK) - 1);
300 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
301 RTC_MDAY_BIN_MASK);
302 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
303 RTC_MONTH_BIN_MASK) - 1);
304 tm->tm_year = ((years + (century * 100)) - 1900);
305 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
306 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
307
308 return 0;
309 }
310
311 /**
312 * ds1685_rtc_set_time - sets the time registers.
313 * @dev: pointer to device structure.
314 * @tm: pointer to rtc_time structure.
315 */
316 static int
ds1685_rtc_set_time(struct device * dev,struct rtc_time * tm)317 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
318 {
319 struct ds1685_priv *rtc = dev_get_drvdata(dev);
320 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
321
322 /* Fetch the time info from rtc_time. */
323 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
324 RTC_SECS_BCD_MASK);
325 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
326 RTC_MINS_BCD_MASK);
327 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
328 RTC_HRS_24_BCD_MASK);
329 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
330 RTC_WDAY_MASK);
331 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
332 RTC_MDAY_BCD_MASK);
333 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
334 RTC_MONTH_BCD_MASK);
335 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
336 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
337 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
338 RTC_CENTURY_MASK, RTC_CENTURY_MASK);
339
340 /*
341 * Perform Sanity Checks:
342 * - Months: !> 12, Month Day != 0.
343 * - Month Day !> Max days in current month.
344 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
345 */
346 if ((tm->tm_mon > 11) || (mday == 0))
347 return -EDOM;
348
349 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
350 return -EDOM;
351
352 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
353 (tm->tm_sec >= 60) || (wday > 7))
354 return -EDOM;
355
356 /*
357 * Set the data mode to use and store the time values in the
358 * RTC registers.
359 */
360 ds1685_rtc_begin_data_access(rtc);
361 ctrlb = rtc->read(rtc, RTC_CTRL_B);
362 if (rtc->bcd_mode)
363 ctrlb &= ~(RTC_CTRL_B_DM);
364 else
365 ctrlb |= RTC_CTRL_B_DM;
366 rtc->write(rtc, RTC_CTRL_B, ctrlb);
367 rtc->write(rtc, RTC_SECS, seconds);
368 rtc->write(rtc, RTC_MINS, minutes);
369 rtc->write(rtc, RTC_HRS, hours);
370 rtc->write(rtc, RTC_WDAY, wday);
371 rtc->write(rtc, RTC_MDAY, mday);
372 rtc->write(rtc, RTC_MONTH, month);
373 rtc->write(rtc, RTC_YEAR, years);
374 rtc->write(rtc, RTC_CENTURY, century);
375 ds1685_rtc_end_data_access(rtc);
376
377 return 0;
378 }
379
380 /**
381 * ds1685_rtc_read_alarm - reads the alarm registers.
382 * @dev: pointer to device structure.
383 * @alrm: pointer to rtc_wkalrm structure.
384 *
385 * There are three primary alarm registers: seconds, minutes, and hours.
386 * A fourth alarm register for the month date is also available in bank1 for
387 * kickstart/wakeup features. The DS1685/DS1687 manual states that a
388 * "don't care" value ranging from 0xc0 to 0xff may be written into one or
389 * more of the three alarm bytes to act as a wildcard value. The fourth
390 * byte doesn't support a "don't care" value.
391 */
392 static int
ds1685_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)393 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
394 {
395 struct ds1685_priv *rtc = dev_get_drvdata(dev);
396 u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
397 int ret;
398
399 /* Fetch the alarm info from the RTC alarm registers. */
400 ds1685_rtc_begin_data_access(rtc);
401 seconds = rtc->read(rtc, RTC_SECS_ALARM);
402 minutes = rtc->read(rtc, RTC_MINS_ALARM);
403 hours = rtc->read(rtc, RTC_HRS_ALARM);
404 mday = rtc->read(rtc, RTC_MDAY_ALARM);
405 ctrlb = rtc->read(rtc, RTC_CTRL_B);
406 ctrlc = rtc->read(rtc, RTC_CTRL_C);
407 ds1685_rtc_end_data_access(rtc);
408
409 /* Check the month date for validity. */
410 ret = ds1685_rtc_check_mday(rtc, mday);
411 if (ret)
412 return ret;
413
414 /*
415 * Check the three alarm bytes.
416 *
417 * The Linux RTC system doesn't support the "don't care" capability
418 * of this RTC chip. We check for it anyways in case support is
419 * added in the future and only assign when we care.
420 */
421 if (likely(seconds < 0xc0))
422 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
423 RTC_SECS_BCD_MASK,
424 RTC_SECS_BIN_MASK);
425
426 if (likely(minutes < 0xc0))
427 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
428 RTC_MINS_BCD_MASK,
429 RTC_MINS_BIN_MASK);
430
431 if (likely(hours < 0xc0))
432 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
433 RTC_HRS_24_BCD_MASK,
434 RTC_HRS_24_BIN_MASK);
435
436 /* Write the data to rtc_wkalrm. */
437 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
438 RTC_MDAY_BIN_MASK);
439 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
440 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
441
442 return 0;
443 }
444
445 /**
446 * ds1685_rtc_set_alarm - sets the alarm in registers.
447 * @dev: pointer to device structure.
448 * @alrm: pointer to rtc_wkalrm structure.
449 */
450 static int
ds1685_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)451 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
452 {
453 struct ds1685_priv *rtc = dev_get_drvdata(dev);
454 u8 ctrlb, seconds, minutes, hours, mday;
455 int ret;
456
457 /* Fetch the alarm info and convert to BCD. */
458 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
459 RTC_SECS_BIN_MASK,
460 RTC_SECS_BCD_MASK);
461 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
462 RTC_MINS_BIN_MASK,
463 RTC_MINS_BCD_MASK);
464 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
465 RTC_HRS_24_BIN_MASK,
466 RTC_HRS_24_BCD_MASK);
467 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
468 RTC_MDAY_BIN_MASK,
469 RTC_MDAY_BCD_MASK);
470
471 /* Check the month date for validity. */
472 ret = ds1685_rtc_check_mday(rtc, mday);
473 if (ret)
474 return ret;
475
476 /*
477 * Check the three alarm bytes.
478 *
479 * The Linux RTC system doesn't support the "don't care" capability
480 * of this RTC chip because rtc_valid_tm tries to validate every
481 * field, and we only support four fields. We put the support
482 * here anyways for the future.
483 */
484 if (unlikely(seconds >= 0xc0))
485 seconds = 0xff;
486
487 if (unlikely(minutes >= 0xc0))
488 minutes = 0xff;
489
490 if (unlikely(hours >= 0xc0))
491 hours = 0xff;
492
493 alrm->time.tm_mon = -1;
494 alrm->time.tm_year = -1;
495 alrm->time.tm_wday = -1;
496 alrm->time.tm_yday = -1;
497 alrm->time.tm_isdst = -1;
498
499 /* Disable the alarm interrupt first. */
500 ds1685_rtc_begin_data_access(rtc);
501 ctrlb = rtc->read(rtc, RTC_CTRL_B);
502 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
503
504 /* Read ctrlc to clear RTC_CTRL_C_AF. */
505 rtc->read(rtc, RTC_CTRL_C);
506
507 /*
508 * Set the data mode to use and store the time values in the
509 * RTC registers.
510 */
511 ctrlb = rtc->read(rtc, RTC_CTRL_B);
512 if (rtc->bcd_mode)
513 ctrlb &= ~(RTC_CTRL_B_DM);
514 else
515 ctrlb |= RTC_CTRL_B_DM;
516 rtc->write(rtc, RTC_CTRL_B, ctrlb);
517 rtc->write(rtc, RTC_SECS_ALARM, seconds);
518 rtc->write(rtc, RTC_MINS_ALARM, minutes);
519 rtc->write(rtc, RTC_HRS_ALARM, hours);
520 rtc->write(rtc, RTC_MDAY_ALARM, mday);
521
522 /* Re-enable the alarm if needed. */
523 if (alrm->enabled) {
524 ctrlb = rtc->read(rtc, RTC_CTRL_B);
525 ctrlb |= RTC_CTRL_B_AIE;
526 rtc->write(rtc, RTC_CTRL_B, ctrlb);
527 }
528
529 /* Done! */
530 ds1685_rtc_end_data_access(rtc);
531
532 return 0;
533 }
534 /* ----------------------------------------------------------------------- */
535
536
537 /* ----------------------------------------------------------------------- */
538 /* /dev/rtcX Interface functions */
539
540 /**
541 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
542 * @dev: pointer to device structure.
543 * @enabled: flag indicating whether to enable or disable.
544 */
545 static int
ds1685_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)546 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
547 {
548 struct ds1685_priv *rtc = dev_get_drvdata(dev);
549 unsigned long flags = 0;
550
551 /* Enable/disable the Alarm IRQ-Enable flag. */
552 spin_lock_irqsave(&rtc->lock, flags);
553
554 /* Flip the requisite interrupt-enable bit. */
555 if (enabled)
556 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
557 RTC_CTRL_B_AIE));
558 else
559 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
560 ~(RTC_CTRL_B_AIE)));
561
562 /* Read Control C to clear all the flag bits. */
563 rtc->read(rtc, RTC_CTRL_C);
564 spin_unlock_irqrestore(&rtc->lock, flags);
565
566 return 0;
567 }
568 /* ----------------------------------------------------------------------- */
569
570
571 /* ----------------------------------------------------------------------- */
572 /* IRQ handler & workqueue. */
573
574 /**
575 * ds1685_rtc_irq_handler - IRQ handler.
576 * @irq: IRQ number.
577 * @dev_id: platform device pointer.
578 */
579 static irqreturn_t
ds1685_rtc_irq_handler(int irq,void * dev_id)580 ds1685_rtc_irq_handler(int irq, void *dev_id)
581 {
582 struct platform_device *pdev = dev_id;
583 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
584 u8 ctrlb, ctrlc;
585 unsigned long events = 0;
586 u8 num_irqs = 0;
587
588 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
589 if (unlikely(!rtc))
590 return IRQ_HANDLED;
591
592 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
593 spin_lock(&rtc->lock);
594 ctrlb = rtc->read(rtc, RTC_CTRL_B);
595 ctrlc = rtc->read(rtc, RTC_CTRL_C);
596
597 /* Is the IRQF bit set? */
598 if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
599 /*
600 * We need to determine if it was one of the standard
601 * events: PF, AF, or UF. If so, we handle them and
602 * update the RTC core.
603 */
604 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
605 events = RTC_IRQF;
606
607 /* Check for a periodic interrupt. */
608 if ((ctrlb & RTC_CTRL_B_PIE) &&
609 (ctrlc & RTC_CTRL_C_PF)) {
610 events |= RTC_PF;
611 num_irqs++;
612 }
613
614 /* Check for an alarm interrupt. */
615 if ((ctrlb & RTC_CTRL_B_AIE) &&
616 (ctrlc & RTC_CTRL_C_AF)) {
617 events |= RTC_AF;
618 num_irqs++;
619 }
620
621 /* Check for an update interrupt. */
622 if ((ctrlb & RTC_CTRL_B_UIE) &&
623 (ctrlc & RTC_CTRL_C_UF)) {
624 events |= RTC_UF;
625 num_irqs++;
626 }
627
628 rtc_update_irq(rtc->dev, num_irqs, events);
629 } else {
630 /*
631 * One of the "extended" interrupts was received that
632 * is not recognized by the RTC core. These need to
633 * be handled in task context as they can call other
634 * functions and the time spent in irq context needs
635 * to be minimized. Schedule them into a workqueue
636 * and inform the RTC core that the IRQs were handled.
637 */
638 spin_unlock(&rtc->lock);
639 schedule_work(&rtc->work);
640 rtc_update_irq(rtc->dev, 0, 0);
641 return IRQ_HANDLED;
642 }
643 }
644 spin_unlock(&rtc->lock);
645
646 return events ? IRQ_HANDLED : IRQ_NONE;
647 }
648
649 /**
650 * ds1685_rtc_work_queue - work queue handler.
651 * @work: work_struct containing data to work on in task context.
652 */
653 static void
ds1685_rtc_work_queue(struct work_struct * work)654 ds1685_rtc_work_queue(struct work_struct *work)
655 {
656 struct ds1685_priv *rtc = container_of(work,
657 struct ds1685_priv, work);
658 struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
659 struct mutex *rtc_mutex = &rtc->dev->ops_lock;
660 u8 ctrl4a, ctrl4b;
661
662 mutex_lock(rtc_mutex);
663
664 ds1685_rtc_switch_to_bank1(rtc);
665 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
666 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
667
668 /*
669 * Check for a kickstart interrupt. With Vcc applied, this
670 * typically means that the power button was pressed, so we
671 * begin the shutdown sequence.
672 */
673 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
674 /* Briefly disable kickstarts to debounce button presses. */
675 rtc->write(rtc, RTC_EXT_CTRL_4B,
676 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
677 ~(RTC_CTRL_4B_KSE)));
678
679 /* Clear the kickstart flag. */
680 rtc->write(rtc, RTC_EXT_CTRL_4A,
681 (ctrl4a & ~(RTC_CTRL_4A_KF)));
682
683
684 /*
685 * Sleep 500ms before re-enabling kickstarts. This allows
686 * adequate time to avoid reading signal jitter as additional
687 * button presses.
688 */
689 msleep(500);
690 rtc->write(rtc, RTC_EXT_CTRL_4B,
691 (rtc->read(rtc, RTC_EXT_CTRL_4B) |
692 RTC_CTRL_4B_KSE));
693
694 /* Call the platform pre-poweroff function. Else, shutdown. */
695 if (rtc->prepare_poweroff != NULL)
696 rtc->prepare_poweroff();
697 else
698 ds1685_rtc_poweroff(pdev);
699 }
700
701 /*
702 * Check for a wake-up interrupt. With Vcc applied, this is
703 * essentially a second alarm interrupt, except it takes into
704 * account the 'date' register in bank1 in addition to the
705 * standard three alarm registers.
706 */
707 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
708 rtc->write(rtc, RTC_EXT_CTRL_4A,
709 (ctrl4a & ~(RTC_CTRL_4A_WF)));
710
711 /* Call the platform wake_alarm function if defined. */
712 if (rtc->wake_alarm != NULL)
713 rtc->wake_alarm();
714 else
715 dev_warn(&pdev->dev,
716 "Wake Alarm IRQ just occurred!\n");
717 }
718
719 /*
720 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
721 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
722 * each byte to a logic 1. This has no effect on any extended
723 * NV-SRAM that might be present, nor on the time/calendar/alarm
724 * registers. After a ram-clear is completed, there is a minimum
725 * recovery time of ~150ms in which all reads/writes are locked out.
726 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
727 * catch this scenario.
728 */
729 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
730 rtc->write(rtc, RTC_EXT_CTRL_4A,
731 (ctrl4a & ~(RTC_CTRL_4A_RF)));
732 msleep(150);
733
734 /* Call the platform post_ram_clear function if defined. */
735 if (rtc->post_ram_clear != NULL)
736 rtc->post_ram_clear();
737 else
738 dev_warn(&pdev->dev,
739 "RAM-Clear IRQ just occurred!\n");
740 }
741 ds1685_rtc_switch_to_bank0(rtc);
742
743 mutex_unlock(rtc_mutex);
744 }
745 /* ----------------------------------------------------------------------- */
746
747
748 /* ----------------------------------------------------------------------- */
749 /* ProcFS interface */
750
751 #ifdef CONFIG_PROC_FS
752 #define NUM_REGS 6 /* Num of control registers. */
753 #define NUM_BITS 8 /* Num bits per register. */
754 #define NUM_SPACES 4 /* Num spaces between each bit. */
755
756 /*
757 * Periodic Interrupt Rates.
758 */
759 static const char *ds1685_rtc_pirq_rate[16] = {
760 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
761 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
762 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
763 };
764
765 /*
766 * Square-Wave Output Frequencies.
767 */
768 static const char *ds1685_rtc_sqw_freq[16] = {
769 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
770 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
771 };
772
773 #ifdef CONFIG_RTC_DS1685_PROC_REGS
774 /**
775 * ds1685_rtc_print_regs - helper function to print register values.
776 * @hex: hex byte to convert into binary bits.
777 * @dest: destination char array.
778 *
779 * This is basically a hex->binary function, just with extra spacing between
780 * the digits. It only works on 1-byte values (8 bits).
781 */
782 static char*
ds1685_rtc_print_regs(u8 hex,char * dest)783 ds1685_rtc_print_regs(u8 hex, char *dest)
784 {
785 u32 i, j;
786 char *tmp = dest;
787
788 for (i = 0; i < NUM_BITS; i++) {
789 *tmp++ = ((hex & 0x80) != 0 ? '1' : '0');
790 for (j = 0; j < NUM_SPACES; j++)
791 *tmp++ = ' ';
792 hex <<= 1;
793 }
794 *tmp++ = '\0';
795
796 return dest;
797 }
798 #endif
799
800 /**
801 * ds1685_rtc_proc - procfs access function.
802 * @dev: pointer to device structure.
803 * @seq: pointer to seq_file structure.
804 */
805 static int
ds1685_rtc_proc(struct device * dev,struct seq_file * seq)806 ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
807 {
808 struct platform_device *pdev = to_platform_device(dev);
809 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
810 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
811 char *model;
812 #ifdef CONFIG_RTC_DS1685_PROC_REGS
813 char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
814 #endif
815
816 /* Read all the relevant data from the control registers. */
817 ds1685_rtc_switch_to_bank1(rtc);
818 ds1685_rtc_get_ssn(rtc, ssn);
819 ctrla = rtc->read(rtc, RTC_CTRL_A);
820 ctrlb = rtc->read(rtc, RTC_CTRL_B);
821 ctrlc = rtc->read(rtc, RTC_CTRL_C);
822 ctrld = rtc->read(rtc, RTC_CTRL_D);
823 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
824 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
825 ds1685_rtc_switch_to_bank0(rtc);
826
827 /* Determine the RTC model. */
828 switch (ssn[0]) {
829 case RTC_MODEL_DS1685:
830 model = "DS1685/DS1687\0";
831 break;
832 case RTC_MODEL_DS1689:
833 model = "DS1689/DS1693\0";
834 break;
835 case RTC_MODEL_DS17285:
836 model = "DS17285/DS17287\0";
837 break;
838 case RTC_MODEL_DS17485:
839 model = "DS17485/DS17487\0";
840 break;
841 case RTC_MODEL_DS17885:
842 model = "DS17885/DS17887\0";
843 break;
844 default:
845 model = "Unknown\0";
846 break;
847 }
848
849 /* Print out the information. */
850 seq_printf(seq,
851 "Model\t\t: %s\n"
852 "Oscillator\t: %s\n"
853 "12/24hr\t\t: %s\n"
854 "DST\t\t: %s\n"
855 "Data mode\t: %s\n"
856 "Battery\t\t: %s\n"
857 "Aux batt\t: %s\n"
858 "Update IRQ\t: %s\n"
859 "Periodic IRQ\t: %s\n"
860 "Periodic Rate\t: %s\n"
861 "SQW Freq\t: %s\n"
862 #ifdef CONFIG_RTC_DS1685_PROC_REGS
863 "Serial #\t: %8phC\n"
864 "Register Status\t:\n"
865 " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
866 "\t\t: %s\n"
867 " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
868 "\t\t: %s\n"
869 " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
870 "\t\t: %s\n"
871 " Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
872 "\t\t: %s\n"
873 #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
874 " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
875 #else
876 " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
877 #endif
878 "\t\t: %s\n"
879 " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
880 "\t\t: %s\n",
881 #else
882 "Serial #\t: %8phC\n",
883 #endif
884 model,
885 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
886 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
887 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
888 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
889 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
890 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
891 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
892 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
893 (!(ctrl4b & RTC_CTRL_4B_E32K) ?
894 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
895 (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
896 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
897 #ifdef CONFIG_RTC_DS1685_PROC_REGS
898 ssn,
899 ds1685_rtc_print_regs(ctrla, bits[0]),
900 ds1685_rtc_print_regs(ctrlb, bits[1]),
901 ds1685_rtc_print_regs(ctrlc, bits[2]),
902 ds1685_rtc_print_regs(ctrld, bits[3]),
903 ds1685_rtc_print_regs(ctrl4a, bits[4]),
904 ds1685_rtc_print_regs(ctrl4b, bits[5]));
905 #else
906 ssn);
907 #endif
908 return 0;
909 }
910 #else
911 #define ds1685_rtc_proc NULL
912 #endif /* CONFIG_PROC_FS */
913 /* ----------------------------------------------------------------------- */
914
915
916 /* ----------------------------------------------------------------------- */
917 /* RTC Class operations */
918
919 static const struct rtc_class_ops
920 ds1685_rtc_ops = {
921 .proc = ds1685_rtc_proc,
922 .read_time = ds1685_rtc_read_time,
923 .set_time = ds1685_rtc_set_time,
924 .read_alarm = ds1685_rtc_read_alarm,
925 .set_alarm = ds1685_rtc_set_alarm,
926 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
927 };
928 /* ----------------------------------------------------------------------- */
929
930
931 /* ----------------------------------------------------------------------- */
932 /* SysFS interface */
933
934 #ifdef CONFIG_SYSFS
935 /**
936 * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs.
937 * @file: pointer to file structure.
938 * @kobj: pointer to kobject structure.
939 * @bin_attr: pointer to bin_attribute structure.
940 * @buf: pointer to char array to hold the output.
941 * @pos: current file position pointer.
942 * @size: size of the data to read.
943 */
944 static ssize_t
ds1685_rtc_sysfs_nvram_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t pos,size_t size)945 ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj,
946 struct bin_attribute *bin_attr, char *buf,
947 loff_t pos, size_t size)
948 {
949 struct platform_device *pdev =
950 to_platform_device(container_of(kobj, struct device, kobj));
951 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
952 ssize_t count;
953 unsigned long flags = 0;
954
955 spin_lock_irqsave(&rtc->lock, flags);
956 ds1685_rtc_switch_to_bank0(rtc);
957
958 /* Read NVRAM in time and bank0 registers. */
959 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
960 count++, size--) {
961 if (count < NVRAM_SZ_TIME)
962 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
963 else
964 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
965 }
966
967 #ifndef CONFIG_RTC_DRV_DS1689
968 if (size > 0) {
969 ds1685_rtc_switch_to_bank1(rtc);
970
971 #ifndef CONFIG_RTC_DRV_DS1685
972 /* Enable burst-mode on DS17x85/DS17x87 */
973 rtc->write(rtc, RTC_EXT_CTRL_4A,
974 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
975 RTC_CTRL_4A_BME));
976
977 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
978 * reading with burst-mode */
979 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
980 (pos - NVRAM_TOTAL_SZ_BANK0));
981 #endif
982
983 /* Read NVRAM in bank1 registers. */
984 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
985 count++, size--) {
986 #ifdef CONFIG_RTC_DRV_DS1685
987 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
988 * before each read. */
989 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
990 (pos - NVRAM_TOTAL_SZ_BANK0));
991 #endif
992 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
993 pos++;
994 }
995
996 #ifndef CONFIG_RTC_DRV_DS1685
997 /* Disable burst-mode on DS17x85/DS17x87 */
998 rtc->write(rtc, RTC_EXT_CTRL_4A,
999 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1000 ~(RTC_CTRL_4A_BME)));
1001 #endif
1002 ds1685_rtc_switch_to_bank0(rtc);
1003 }
1004 #endif /* !CONFIG_RTC_DRV_DS1689 */
1005 spin_unlock_irqrestore(&rtc->lock, flags);
1006
1007 /*
1008 * XXX: Bug? this appears to cause the function to get executed
1009 * several times in succession. But it's the only way to actually get
1010 * data written out to a file.
1011 */
1012 return count;
1013 }
1014
1015 /**
1016 * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs.
1017 * @file: pointer to file structure.
1018 * @kobj: pointer to kobject structure.
1019 * @bin_attr: pointer to bin_attribute structure.
1020 * @buf: pointer to char array to hold the input.
1021 * @pos: current file position pointer.
1022 * @size: size of the data to write.
1023 */
1024 static ssize_t
ds1685_rtc_sysfs_nvram_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t pos,size_t size)1025 ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj,
1026 struct bin_attribute *bin_attr, char *buf,
1027 loff_t pos, size_t size)
1028 {
1029 struct platform_device *pdev =
1030 to_platform_device(container_of(kobj, struct device, kobj));
1031 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1032 ssize_t count;
1033 unsigned long flags = 0;
1034
1035 spin_lock_irqsave(&rtc->lock, flags);
1036 ds1685_rtc_switch_to_bank0(rtc);
1037
1038 /* Write NVRAM in time and bank0 registers. */
1039 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
1040 count++, size--)
1041 if (count < NVRAM_SZ_TIME)
1042 rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
1043 *buf++);
1044 else
1045 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
1046
1047 #ifndef CONFIG_RTC_DRV_DS1689
1048 if (size > 0) {
1049 ds1685_rtc_switch_to_bank1(rtc);
1050
1051 #ifndef CONFIG_RTC_DRV_DS1685
1052 /* Enable burst-mode on DS17x85/DS17x87 */
1053 rtc->write(rtc, RTC_EXT_CTRL_4A,
1054 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
1055 RTC_CTRL_4A_BME));
1056
1057 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
1058 * writing with burst-mode */
1059 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
1060 (pos - NVRAM_TOTAL_SZ_BANK0));
1061 #endif
1062
1063 /* Write NVRAM in bank1 registers. */
1064 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
1065 count++, size--) {
1066 #ifdef CONFIG_RTC_DRV_DS1685
1067 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
1068 * before each read. */
1069 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
1070 (pos - NVRAM_TOTAL_SZ_BANK0));
1071 #endif
1072 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
1073 pos++;
1074 }
1075
1076 #ifndef CONFIG_RTC_DRV_DS1685
1077 /* Disable burst-mode on DS17x85/DS17x87 */
1078 rtc->write(rtc, RTC_EXT_CTRL_4A,
1079 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1080 ~(RTC_CTRL_4A_BME)));
1081 #endif
1082 ds1685_rtc_switch_to_bank0(rtc);
1083 }
1084 #endif /* !CONFIG_RTC_DRV_DS1689 */
1085 spin_unlock_irqrestore(&rtc->lock, flags);
1086
1087 return count;
1088 }
1089
1090 /**
1091 * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram.
1092 * @attr: nvram attributes.
1093 * @read: nvram read function.
1094 * @write: nvram write function.
1095 * @size: nvram total size (bank0 + extended).
1096 */
1097 static struct bin_attribute
1098 ds1685_rtc_sysfs_nvram_attr = {
1099 .attr = {
1100 .name = "nvram",
1101 .mode = S_IRUGO | S_IWUSR,
1102 },
1103 .read = ds1685_rtc_sysfs_nvram_read,
1104 .write = ds1685_rtc_sysfs_nvram_write,
1105 .size = NVRAM_TOTAL_SZ
1106 };
1107
1108 /**
1109 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
1110 * @dev: pointer to device structure.
1111 * @attr: pointer to device_attribute structure.
1112 * @buf: pointer to char array to hold the output.
1113 */
1114 static ssize_t
ds1685_rtc_sysfs_battery_show(struct device * dev,struct device_attribute * attr,char * buf)1115 ds1685_rtc_sysfs_battery_show(struct device *dev,
1116 struct device_attribute *attr, char *buf)
1117 {
1118 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1119 u8 ctrld;
1120
1121 ctrld = rtc->read(rtc, RTC_CTRL_D);
1122
1123 return sprintf(buf, "%s\n",
1124 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1125 }
1126 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1127
1128 /**
1129 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1130 * @dev: pointer to device structure.
1131 * @attr: pointer to device_attribute structure.
1132 * @buf: pointer to char array to hold the output.
1133 */
1134 static ssize_t
ds1685_rtc_sysfs_auxbatt_show(struct device * dev,struct device_attribute * attr,char * buf)1135 ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1136 struct device_attribute *attr, char *buf)
1137 {
1138 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1139 u8 ctrl4a;
1140
1141 ds1685_rtc_switch_to_bank1(rtc);
1142 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1143 ds1685_rtc_switch_to_bank0(rtc);
1144
1145 return sprintf(buf, "%s\n",
1146 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1147 }
1148 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1149
1150 /**
1151 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1152 * @dev: pointer to device structure.
1153 * @attr: pointer to device_attribute structure.
1154 * @buf: pointer to char array to hold the output.
1155 */
1156 static ssize_t
ds1685_rtc_sysfs_serial_show(struct device * dev,struct device_attribute * attr,char * buf)1157 ds1685_rtc_sysfs_serial_show(struct device *dev,
1158 struct device_attribute *attr, char *buf)
1159 {
1160 struct ds1685_priv *rtc = dev_get_drvdata(dev);
1161 u8 ssn[8];
1162
1163 ds1685_rtc_switch_to_bank1(rtc);
1164 ds1685_rtc_get_ssn(rtc, ssn);
1165 ds1685_rtc_switch_to_bank0(rtc);
1166
1167 return sprintf(buf, "%8phC\n", ssn);
1168 }
1169 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1170
1171 /**
1172 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1173 */
1174 static struct attribute*
1175 ds1685_rtc_sysfs_misc_attrs[] = {
1176 &dev_attr_battery.attr,
1177 &dev_attr_auxbatt.attr,
1178 &dev_attr_serial.attr,
1179 NULL,
1180 };
1181
1182 /**
1183 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1184 */
1185 static const struct attribute_group
1186 ds1685_rtc_sysfs_misc_grp = {
1187 .name = "misc",
1188 .attrs = ds1685_rtc_sysfs_misc_attrs,
1189 };
1190
1191 /**
1192 * ds1685_rtc_sysfs_register - register sysfs files.
1193 * @dev: pointer to device structure.
1194 */
1195 static int
ds1685_rtc_sysfs_register(struct device * dev)1196 ds1685_rtc_sysfs_register(struct device *dev)
1197 {
1198 int ret = 0;
1199
1200 sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr);
1201 ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1202 if (ret)
1203 return ret;
1204
1205 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1206 if (ret)
1207 return ret;
1208
1209 return 0;
1210 }
1211
1212 /**
1213 * ds1685_rtc_sysfs_unregister - unregister sysfs files.
1214 * @dev: pointer to device structure.
1215 */
1216 static int
ds1685_rtc_sysfs_unregister(struct device * dev)1217 ds1685_rtc_sysfs_unregister(struct device *dev)
1218 {
1219 sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr);
1220 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1221
1222 return 0;
1223 }
1224 #endif /* CONFIG_SYSFS */
1225
1226
1227
1228 /* ----------------------------------------------------------------------- */
1229 /* Driver Probe/Removal */
1230
1231 /**
1232 * ds1685_rtc_probe - initializes rtc driver.
1233 * @pdev: pointer to platform_device structure.
1234 */
1235 static int
ds1685_rtc_probe(struct platform_device * pdev)1236 ds1685_rtc_probe(struct platform_device *pdev)
1237 {
1238 struct rtc_device *rtc_dev;
1239 struct resource *res;
1240 struct ds1685_priv *rtc;
1241 struct ds1685_rtc_platform_data *pdata;
1242 u8 ctrla, ctrlb, hours;
1243 unsigned char am_pm;
1244 int ret = 0;
1245
1246 /* Get the platform data. */
1247 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1248 if (!pdata)
1249 return -ENODEV;
1250
1251 /* Allocate memory for the rtc device. */
1252 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1253 if (!rtc)
1254 return -ENOMEM;
1255
1256 /*
1257 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all
1258 * platforms put the RTC in an easy-access place. Like the SGI Octane,
1259 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1260 * that sits behind the IOC3 PCI metadevice.
1261 */
1262 if (pdata->alloc_io_resources) {
1263 /* Get the platform resources. */
1264 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1265 if (!res)
1266 return -ENXIO;
1267 rtc->size = resource_size(res);
1268
1269 /* Request a memory region. */
1270 /* XXX: mmio-only for now. */
1271 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1272 pdev->name))
1273 return -EBUSY;
1274
1275 /*
1276 * Set the base address for the rtc, and ioremap its
1277 * registers.
1278 */
1279 rtc->baseaddr = res->start;
1280 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1281 if (!rtc->regs)
1282 return -ENOMEM;
1283 }
1284 rtc->alloc_io_resources = pdata->alloc_io_resources;
1285
1286 /* Get the register step size. */
1287 if (pdata->regstep > 0)
1288 rtc->regstep = pdata->regstep;
1289 else
1290 rtc->regstep = 1;
1291
1292 /* Platform read function, else default if mmio setup */
1293 if (pdata->plat_read)
1294 rtc->read = pdata->plat_read;
1295 else
1296 if (pdata->alloc_io_resources)
1297 rtc->read = ds1685_read;
1298 else
1299 return -ENXIO;
1300
1301 /* Platform write function, else default if mmio setup */
1302 if (pdata->plat_write)
1303 rtc->write = pdata->plat_write;
1304 else
1305 if (pdata->alloc_io_resources)
1306 rtc->write = ds1685_write;
1307 else
1308 return -ENXIO;
1309
1310 /* Platform pre-shutdown function, if defined. */
1311 if (pdata->plat_prepare_poweroff)
1312 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1313
1314 /* Platform wake_alarm function, if defined. */
1315 if (pdata->plat_wake_alarm)
1316 rtc->wake_alarm = pdata->plat_wake_alarm;
1317
1318 /* Platform post_ram_clear function, if defined. */
1319 if (pdata->plat_post_ram_clear)
1320 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1321
1322 /* Init the spinlock, workqueue, & set the driver data. */
1323 spin_lock_init(&rtc->lock);
1324 INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1325 platform_set_drvdata(pdev, rtc);
1326
1327 /* Turn the oscillator on if is not already on (DV1 = 1). */
1328 ctrla = rtc->read(rtc, RTC_CTRL_A);
1329 if (!(ctrla & RTC_CTRL_A_DV1))
1330 ctrla |= RTC_CTRL_A_DV1;
1331
1332 /* Enable the countdown chain (DV2 = 0) */
1333 ctrla &= ~(RTC_CTRL_A_DV2);
1334
1335 /* Clear RS3-RS0 in Control A. */
1336 ctrla &= ~(RTC_CTRL_A_RS_MASK);
1337
1338 /*
1339 * All done with Control A. Switch to Bank 1 for the remainder of
1340 * the RTC setup so we have access to the extended functions.
1341 */
1342 ctrla |= RTC_CTRL_A_DV0;
1343 rtc->write(rtc, RTC_CTRL_A, ctrla);
1344
1345 /* Default to 32768kHz output. */
1346 rtc->write(rtc, RTC_EXT_CTRL_4B,
1347 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1348
1349 /* Set the SET bit in Control B so we can do some housekeeping. */
1350 rtc->write(rtc, RTC_CTRL_B,
1351 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1352
1353 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1354 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1355 cpu_relax();
1356
1357 /*
1358 * If the platform supports BCD mode, then set DM=0 in Control B.
1359 * Otherwise, set DM=1 for BIN mode.
1360 */
1361 ctrlb = rtc->read(rtc, RTC_CTRL_B);
1362 if (pdata->bcd_mode)
1363 ctrlb &= ~(RTC_CTRL_B_DM);
1364 else
1365 ctrlb |= RTC_CTRL_B_DM;
1366 rtc->bcd_mode = pdata->bcd_mode;
1367
1368 /*
1369 * Disable Daylight Savings Time (DSE = 0).
1370 * The RTC has hardcoded timezone information that is rendered
1371 * obselete. We'll let the OS deal with DST settings instead.
1372 */
1373 if (ctrlb & RTC_CTRL_B_DSE)
1374 ctrlb &= ~(RTC_CTRL_B_DSE);
1375
1376 /* Force 24-hour mode (2412 = 1). */
1377 if (!(ctrlb & RTC_CTRL_B_2412)) {
1378 /* Reinitialize the time hours. */
1379 hours = rtc->read(rtc, RTC_HRS);
1380 am_pm = hours & RTC_HRS_AMPM_MASK;
1381 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1382 RTC_HRS_12_BIN_MASK);
1383 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1384
1385 /* Enable 24-hour mode. */
1386 ctrlb |= RTC_CTRL_B_2412;
1387
1388 /* Write back to Control B, including DM & DSE bits. */
1389 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1390
1391 /* Write the time hours back. */
1392 rtc->write(rtc, RTC_HRS,
1393 ds1685_rtc_bin2bcd(rtc, hours,
1394 RTC_HRS_24_BIN_MASK,
1395 RTC_HRS_24_BCD_MASK));
1396
1397 /* Reinitialize the alarm hours. */
1398 hours = rtc->read(rtc, RTC_HRS_ALARM);
1399 am_pm = hours & RTC_HRS_AMPM_MASK;
1400 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1401 RTC_HRS_12_BIN_MASK);
1402 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1403
1404 /* Write the alarm hours back. */
1405 rtc->write(rtc, RTC_HRS_ALARM,
1406 ds1685_rtc_bin2bcd(rtc, hours,
1407 RTC_HRS_24_BIN_MASK,
1408 RTC_HRS_24_BCD_MASK));
1409 } else {
1410 /* 24-hour mode is already set, so write Control B back. */
1411 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1412 }
1413
1414 /* Unset the SET bit in Control B so the RTC can update. */
1415 rtc->write(rtc, RTC_CTRL_B,
1416 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
1417
1418 /* Check the main battery. */
1419 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
1420 dev_warn(&pdev->dev,
1421 "Main battery is exhausted! RTC may be invalid!\n");
1422
1423 /* Check the auxillary battery. It is optional. */
1424 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
1425 dev_warn(&pdev->dev,
1426 "Aux battery is exhausted or not available.\n");
1427
1428 /* Read Ctrl B and clear PIE/AIE/UIE. */
1429 rtc->write(rtc, RTC_CTRL_B,
1430 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
1431
1432 /* Reading Ctrl C auto-clears PF/AF/UF. */
1433 rtc->read(rtc, RTC_CTRL_C);
1434
1435 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1436 rtc->write(rtc, RTC_EXT_CTRL_4B,
1437 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
1438
1439 /* Clear RF/WF/KF in Ctrl 4A. */
1440 rtc->write(rtc, RTC_EXT_CTRL_4A,
1441 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
1442
1443 /*
1444 * Re-enable KSE to handle power button events. We do not enable
1445 * WIE or RIE by default.
1446 */
1447 rtc->write(rtc, RTC_EXT_CTRL_4B,
1448 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
1449
1450 rtc_dev = devm_rtc_allocate_device(&pdev->dev);
1451 if (IS_ERR(rtc_dev))
1452 return PTR_ERR(rtc_dev);
1453
1454 rtc_dev->ops = &ds1685_rtc_ops;
1455
1456 /* Century bit is useless because leap year fails in 1900 and 2100 */
1457 rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
1458 rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
1459
1460 /* Maximum periodic rate is 8192Hz (0.122070ms). */
1461 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
1462
1463 /* See if the platform doesn't support UIE. */
1464 if (pdata->uie_unsupported)
1465 rtc_dev->uie_unsupported = 1;
1466 rtc->uie_unsupported = pdata->uie_unsupported;
1467
1468 rtc->dev = rtc_dev;
1469
1470 /*
1471 * Fetch the IRQ and setup the interrupt handler.
1472 *
1473 * Not all platforms have the IRQF pin tied to something. If not, the
1474 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
1475 * there won't be an automatic way of notifying the kernel about it,
1476 * unless ctrlc is explicitly polled.
1477 */
1478 if (!pdata->no_irq) {
1479 ret = platform_get_irq(pdev, 0);
1480 if (ret > 0) {
1481 rtc->irq_num = ret;
1482
1483 /* Request an IRQ. */
1484 ret = devm_request_irq(&pdev->dev, rtc->irq_num,
1485 ds1685_rtc_irq_handler,
1486 IRQF_SHARED, pdev->name, pdev);
1487
1488 /* Check to see if something came back. */
1489 if (unlikely(ret)) {
1490 dev_warn(&pdev->dev,
1491 "RTC interrupt not available\n");
1492 rtc->irq_num = 0;
1493 }
1494 } else
1495 return ret;
1496 }
1497 rtc->no_irq = pdata->no_irq;
1498
1499 /* Setup complete. */
1500 ds1685_rtc_switch_to_bank0(rtc);
1501
1502 #ifdef CONFIG_SYSFS
1503 ret = ds1685_rtc_sysfs_register(&pdev->dev);
1504 if (ret)
1505 return ret;
1506 #endif
1507
1508 return rtc_register_device(rtc_dev);
1509 }
1510
1511 /**
1512 * ds1685_rtc_remove - removes rtc driver.
1513 * @pdev: pointer to platform_device structure.
1514 */
1515 static int
ds1685_rtc_remove(struct platform_device * pdev)1516 ds1685_rtc_remove(struct platform_device *pdev)
1517 {
1518 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1519
1520 #ifdef CONFIG_SYSFS
1521 ds1685_rtc_sysfs_unregister(&pdev->dev);
1522 #endif
1523
1524 /* Read Ctrl B and clear PIE/AIE/UIE. */
1525 rtc->write(rtc, RTC_CTRL_B,
1526 (rtc->read(rtc, RTC_CTRL_B) &
1527 ~(RTC_CTRL_B_PAU_MASK)));
1528
1529 /* Reading Ctrl C auto-clears PF/AF/UF. */
1530 rtc->read(rtc, RTC_CTRL_C);
1531
1532 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1533 rtc->write(rtc, RTC_EXT_CTRL_4B,
1534 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
1535 ~(RTC_CTRL_4B_RWK_MASK)));
1536
1537 /* Manually clear RF/WF/KF in Ctrl 4A. */
1538 rtc->write(rtc, RTC_EXT_CTRL_4A,
1539 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1540 ~(RTC_CTRL_4A_RWK_MASK)));
1541
1542 cancel_work_sync(&rtc->work);
1543
1544 return 0;
1545 }
1546
1547 /**
1548 * ds1685_rtc_driver - rtc driver properties.
1549 */
1550 static struct platform_driver ds1685_rtc_driver = {
1551 .driver = {
1552 .name = "rtc-ds1685",
1553 },
1554 .probe = ds1685_rtc_probe,
1555 .remove = ds1685_rtc_remove,
1556 };
1557 module_platform_driver(ds1685_rtc_driver);
1558 /* ----------------------------------------------------------------------- */
1559
1560
1561 /* ----------------------------------------------------------------------- */
1562 /* Poweroff function */
1563
1564 /**
1565 * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
1566 * @pdev: pointer to platform_device structure.
1567 */
1568 void __noreturn
ds1685_rtc_poweroff(struct platform_device * pdev)1569 ds1685_rtc_poweroff(struct platform_device *pdev)
1570 {
1571 u8 ctrla, ctrl4a, ctrl4b;
1572 struct ds1685_priv *rtc;
1573
1574 /* Check for valid RTC data, else, spin forever. */
1575 if (unlikely(!pdev)) {
1576 pr_emerg("platform device data not available, spinning forever ...\n");
1577 while(1);
1578 unreachable();
1579 } else {
1580 /* Get the rtc data. */
1581 rtc = platform_get_drvdata(pdev);
1582
1583 /*
1584 * Disable our IRQ. We're powering down, so we're not
1585 * going to worry about cleaning up. Most of that should
1586 * have been taken care of by the shutdown scripts and this
1587 * is the final function call.
1588 */
1589 if (!rtc->no_irq)
1590 disable_irq_nosync(rtc->irq_num);
1591
1592 /* Oscillator must be on and the countdown chain enabled. */
1593 ctrla = rtc->read(rtc, RTC_CTRL_A);
1594 ctrla |= RTC_CTRL_A_DV1;
1595 ctrla &= ~(RTC_CTRL_A_DV2);
1596 rtc->write(rtc, RTC_CTRL_A, ctrla);
1597
1598 /*
1599 * Read Control 4A and check the status of the auxillary
1600 * battery. This must be present and working (VRT2 = 1)
1601 * for wakeup and kickstart functionality to be useful.
1602 */
1603 ds1685_rtc_switch_to_bank1(rtc);
1604 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1605 if (ctrl4a & RTC_CTRL_4A_VRT2) {
1606 /* Clear all of the interrupt flags on Control 4A. */
1607 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
1608 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
1609
1610 /*
1611 * The auxillary battery is present and working.
1612 * Enable extended functions (ABE=1), enable
1613 * wake-up (WIE=1), and enable kickstart (KSE=1)
1614 * in Control 4B.
1615 */
1616 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
1617 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
1618 RTC_CTRL_4B_KSE);
1619 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
1620 }
1621
1622 /* Set PAB to 1 in Control 4A to power the system down. */
1623 dev_warn(&pdev->dev, "Powerdown.\n");
1624 msleep(20);
1625 rtc->write(rtc, RTC_EXT_CTRL_4A,
1626 (ctrl4a | RTC_CTRL_4A_PAB));
1627
1628 /* Spin ... we do not switch back to bank0. */
1629 while(1);
1630 unreachable();
1631 }
1632 }
1633 EXPORT_SYMBOL(ds1685_rtc_poweroff);
1634 /* ----------------------------------------------------------------------- */
1635
1636
1637 MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
1638 MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
1639 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
1640 MODULE_LICENSE("GPL");
1641 MODULE_ALIAS("platform:rtc-ds1685");
1642
