1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <gerald.baeza@st.com>
6 *
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/mfd/stm32-timers.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
18
19 #define CCMR_CHANNEL_SHIFT 8
20 #define CCMR_CHANNEL_MASK 0xFF
21 #define MAX_BREAKINPUT 2
22
23 struct stm32_breakinput {
24 u32 index;
25 u32 level;
26 u32 filter;
27 };
28
29 struct stm32_pwm {
30 struct pwm_chip chip;
31 struct mutex lock; /* protect pwm config/enable */
32 struct clk *clk;
33 struct regmap *regmap;
34 u32 max_arr;
35 bool have_complementary_output;
36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37 unsigned int num_breakinputs;
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
39 };
40
to_stm32_pwm_dev(struct pwm_chip * chip)41 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42 {
43 return container_of(chip, struct stm32_pwm, chip);
44 }
45
active_channels(struct stm32_pwm * dev)46 static u32 active_channels(struct stm32_pwm *dev)
47 {
48 u32 ccer;
49
50 regmap_read(dev->regmap, TIM_CCER, &ccer);
51
52 return ccer & TIM_CCER_CCXE;
53 }
54
write_ccrx(struct stm32_pwm * dev,int ch,u32 value)55 static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
56 {
57 switch (ch) {
58 case 0:
59 return regmap_write(dev->regmap, TIM_CCR1, value);
60 case 1:
61 return regmap_write(dev->regmap, TIM_CCR2, value);
62 case 2:
63 return regmap_write(dev->regmap, TIM_CCR3, value);
64 case 3:
65 return regmap_write(dev->regmap, TIM_CCR4, value);
66 }
67 return -EINVAL;
68 }
69
70 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
71 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
72 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
73 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
74
75 /*
76 * Capture using PWM input mode:
77 * ___ ___
78 * TI[1, 2, 3 or 4]: ........._| |________|
79 * ^0 ^1 ^2
80 * . . .
81 * . . XXXXX
82 * . . XXXXX |
83 * . XXXXX . |
84 * XXXXX . . |
85 * COUNTER: ______XXXXX . . . |_XXX
86 * start^ . . . ^stop
87 * . . . .
88 * v v . v
89 * v
90 * CCR1/CCR3: tx..........t0...........t2
91 * CCR2/CCR4: tx..............t1.........
92 *
93 * DMA burst transfer: | |
94 * v v
95 * DMA buffer: { t0, tx } { t2, t1 }
96 * DMA done: ^
97 *
98 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
99 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
100 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
101 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
102 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
103 *
104 * DMA done, compute:
105 * - Period = t2 - t0
106 * - Duty cycle = t1 - t0
107 */
stm32_pwm_raw_capture(struct stm32_pwm * priv,struct pwm_device * pwm,unsigned long tmo_ms,u32 * raw_prd,u32 * raw_dty)108 static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
109 unsigned long tmo_ms, u32 *raw_prd,
110 u32 *raw_dty)
111 {
112 struct device *parent = priv->chip.dev->parent;
113 enum stm32_timers_dmas dma_id;
114 u32 ccen, ccr;
115 int ret;
116
117 /* Ensure registers have been updated, enable counter and capture */
118 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
119 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
120
121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
125 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
126
127 /*
128 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
129 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
130 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
131 * or { CCR3, CCR4 }, { CCR3, CCR4 }
132 */
133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
134 2, tmo_ms);
135 if (ret)
136 goto stop;
137
138 /* Period: t2 - t0 (take care of counter overflow) */
139 if (priv->capture[0] <= priv->capture[2])
140 *raw_prd = priv->capture[2] - priv->capture[0];
141 else
142 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
143
144 /* Duty cycle capture requires at least two capture units */
145 if (pwm->chip->npwm < 2)
146 *raw_dty = 0;
147 else if (priv->capture[0] <= priv->capture[3])
148 *raw_dty = priv->capture[3] - priv->capture[0];
149 else
150 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
151
152 if (*raw_dty > *raw_prd) {
153 /*
154 * Race beetween PWM input and DMA: it may happen
155 * falling edge triggers new capture on TI2/4 before DMA
156 * had a chance to read CCR2/4. It means capture[1]
157 * contains period + duty_cycle. So, subtract period.
158 */
159 *raw_dty -= *raw_prd;
160 }
161
162 stop:
163 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
164 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
165
166 return ret;
167 }
168
stm32_pwm_capture(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_capture * result,unsigned long tmo_ms)169 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
170 struct pwm_capture *result, unsigned long tmo_ms)
171 {
172 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
173 unsigned long long prd, div, dty;
174 unsigned long rate;
175 unsigned int psc = 0, icpsc, scale;
176 u32 raw_prd = 0, raw_dty = 0;
177 int ret = 0;
178
179 mutex_lock(&priv->lock);
180
181 if (active_channels(priv)) {
182 ret = -EBUSY;
183 goto unlock;
184 }
185
186 ret = clk_enable(priv->clk);
187 if (ret) {
188 dev_err(priv->chip.dev, "failed to enable counter clock\n");
189 goto unlock;
190 }
191
192 rate = clk_get_rate(priv->clk);
193 if (!rate) {
194 ret = -EINVAL;
195 goto clk_dis;
196 }
197
198 /* prescaler: fit timeout window provided by upper layer */
199 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
200 do_div(div, MSEC_PER_SEC);
201 prd = div;
202 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
203 psc++;
204 div = prd;
205 do_div(div, psc + 1);
206 }
207 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
208 regmap_write(priv->regmap, TIM_PSC, psc);
209
210 /* Reset input selector to its default input and disable slave mode */
211 regmap_write(priv->regmap, TIM_TISEL, 0x0);
212 regmap_write(priv->regmap, TIM_SMCR, 0x0);
213
214 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
215 regmap_update_bits(priv->regmap,
216 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
217 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
218 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
219 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
220
221 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
222 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
223 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
224 TIM_CCER_CC2P : TIM_CCER_CC4P);
225
226 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
227 if (ret)
228 goto stop;
229
230 /*
231 * Got a capture. Try to improve accuracy at high rates:
232 * - decrease counter clock prescaler, scale up to max rate.
233 * - use input prescaler, capture once every /2 /4 or /8 edges.
234 */
235 if (raw_prd) {
236 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
237
238 scale = max_arr / min(max_arr, raw_prd);
239 } else {
240 scale = priv->max_arr; /* bellow resolution, use max scale */
241 }
242
243 if (psc && scale > 1) {
244 /* 2nd measure with new scale */
245 psc /= scale;
246 regmap_write(priv->regmap, TIM_PSC, psc);
247 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
248 &raw_dty);
249 if (ret)
250 goto stop;
251 }
252
253 /* Compute intermediate period not to exceed timeout at low rates */
254 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
255 do_div(prd, rate);
256
257 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
258 /* input prescaler: also keep arbitrary margin */
259 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
260 break;
261 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
262 break;
263 }
264
265 if (!icpsc)
266 goto done;
267
268 /* Last chance to improve period accuracy, using input prescaler */
269 regmap_update_bits(priv->regmap,
270 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
271 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
272 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
273 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
274
275 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
276 if (ret)
277 goto stop;
278
279 if (raw_dty >= (raw_prd >> icpsc)) {
280 /*
281 * We may fall here using input prescaler, when input
282 * capture starts on high side (before falling edge).
283 * Example with icpsc to capture on each 4 events:
284 *
285 * start 1st capture 2nd capture
286 * v v v
287 * ___ _____ _____ _____ _____ ____
288 * TI1..4 |__| |__| |__| |__| |__|
289 * v v . . . . . v v
290 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
291 * icpsc2/4: 0 1 2 3 0
292 * v v v v
293 * CCR1/3 ......t0..............................t2
294 * CCR2/4 ..t1..............................t1'...
295 * . . .
296 * Capture0: .<----------------------------->.
297 * Capture1: .<-------------------------->. .
298 * . . .
299 * Period: .<------> . .
300 * Low side: .<>.
301 *
302 * Result:
303 * - Period = Capture0 / icpsc
304 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
305 */
306 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
307 }
308
309 done:
310 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
311 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
312 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
313 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
314 stop:
315 regmap_write(priv->regmap, TIM_CCER, 0);
316 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
317 regmap_write(priv->regmap, TIM_PSC, 0);
318 clk_dis:
319 clk_disable(priv->clk);
320 unlock:
321 mutex_unlock(&priv->lock);
322
323 return ret;
324 }
325
stm32_pwm_config(struct stm32_pwm * priv,int ch,int duty_ns,int period_ns)326 static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
327 int duty_ns, int period_ns)
328 {
329 unsigned long long prd, div, dty;
330 unsigned int prescaler = 0;
331 u32 ccmr, mask, shift;
332
333 /* Period and prescaler values depends on clock rate */
334 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
335
336 do_div(div, NSEC_PER_SEC);
337 prd = div;
338
339 while (div > priv->max_arr) {
340 prescaler++;
341 div = prd;
342 do_div(div, prescaler + 1);
343 }
344
345 prd = div;
346
347 if (prescaler > MAX_TIM_PSC)
348 return -EINVAL;
349
350 /*
351 * All channels share the same prescaler and counter so when two
352 * channels are active at the same time we can't change them
353 */
354 if (active_channels(priv) & ~(1 << ch * 4)) {
355 u32 psc, arr;
356
357 regmap_read(priv->regmap, TIM_PSC, &psc);
358 regmap_read(priv->regmap, TIM_ARR, &arr);
359
360 if ((psc != prescaler) || (arr != prd - 1))
361 return -EBUSY;
362 }
363
364 regmap_write(priv->regmap, TIM_PSC, prescaler);
365 regmap_write(priv->regmap, TIM_ARR, prd - 1);
366 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
367
368 /* Calculate the duty cycles */
369 dty = prd * duty_ns;
370 do_div(dty, period_ns);
371
372 write_ccrx(priv, ch, dty);
373
374 /* Configure output mode */
375 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
376 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
377 mask = CCMR_CHANNEL_MASK << shift;
378
379 if (ch < 2)
380 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
381 else
382 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
383
384 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
385
386 return 0;
387 }
388
stm32_pwm_set_polarity(struct stm32_pwm * priv,int ch,enum pwm_polarity polarity)389 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
390 enum pwm_polarity polarity)
391 {
392 u32 mask;
393
394 mask = TIM_CCER_CC1P << (ch * 4);
395 if (priv->have_complementary_output)
396 mask |= TIM_CCER_CC1NP << (ch * 4);
397
398 regmap_update_bits(priv->regmap, TIM_CCER, mask,
399 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
400
401 return 0;
402 }
403
stm32_pwm_enable(struct stm32_pwm * priv,int ch)404 static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
405 {
406 u32 mask;
407 int ret;
408
409 ret = clk_enable(priv->clk);
410 if (ret)
411 return ret;
412
413 /* Enable channel */
414 mask = TIM_CCER_CC1E << (ch * 4);
415 if (priv->have_complementary_output)
416 mask |= TIM_CCER_CC1NE << (ch * 4);
417
418 regmap_set_bits(priv->regmap, TIM_CCER, mask);
419
420 /* Make sure that registers are updated */
421 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
422
423 /* Enable controller */
424 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
425
426 return 0;
427 }
428
stm32_pwm_disable(struct stm32_pwm * priv,int ch)429 static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
430 {
431 u32 mask;
432
433 /* Disable channel */
434 mask = TIM_CCER_CC1E << (ch * 4);
435 if (priv->have_complementary_output)
436 mask |= TIM_CCER_CC1NE << (ch * 4);
437
438 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
439
440 /* When all channels are disabled, we can disable the controller */
441 if (!active_channels(priv))
442 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
443
444 clk_disable(priv->clk);
445 }
446
stm32_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)447 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
448 const struct pwm_state *state)
449 {
450 bool enabled;
451 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
452 int ret;
453
454 enabled = pwm->state.enabled;
455
456 if (enabled && !state->enabled) {
457 stm32_pwm_disable(priv, pwm->hwpwm);
458 return 0;
459 }
460
461 if (state->polarity != pwm->state.polarity)
462 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
463
464 ret = stm32_pwm_config(priv, pwm->hwpwm,
465 state->duty_cycle, state->period);
466 if (ret)
467 return ret;
468
469 if (!enabled && state->enabled)
470 ret = stm32_pwm_enable(priv, pwm->hwpwm);
471
472 return ret;
473 }
474
stm32_pwm_apply_locked(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)475 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
476 const struct pwm_state *state)
477 {
478 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
479 int ret;
480
481 /* protect common prescaler for all active channels */
482 mutex_lock(&priv->lock);
483 ret = stm32_pwm_apply(chip, pwm, state);
484 mutex_unlock(&priv->lock);
485
486 return ret;
487 }
488
489 static const struct pwm_ops stm32pwm_ops = {
490 .owner = THIS_MODULE,
491 .apply = stm32_pwm_apply_locked,
492 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
493 };
494
stm32_pwm_set_breakinput(struct stm32_pwm * priv,const struct stm32_breakinput * bi)495 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
496 const struct stm32_breakinput *bi)
497 {
498 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
499 u32 bke = TIM_BDTR_BKE(bi->index);
500 u32 bkp = TIM_BDTR_BKP(bi->index);
501 u32 bkf = TIM_BDTR_BKF(bi->index);
502 u32 mask = bkf | bkp | bke;
503 u32 bdtr;
504
505 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
506
507 if (bi->level)
508 bdtr |= bkp;
509
510 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
511
512 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
513
514 return (bdtr & bke) ? 0 : -EINVAL;
515 }
516
stm32_pwm_apply_breakinputs(struct stm32_pwm * priv)517 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
518 {
519 unsigned int i;
520 int ret;
521
522 for (i = 0; i < priv->num_breakinputs; i++) {
523 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
524 if (ret < 0)
525 return ret;
526 }
527
528 return 0;
529 }
530
stm32_pwm_probe_breakinputs(struct stm32_pwm * priv,struct device_node * np)531 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
532 struct device_node *np)
533 {
534 int nb, ret, array_size;
535 unsigned int i;
536
537 nb = of_property_count_elems_of_size(np, "st,breakinput",
538 sizeof(struct stm32_breakinput));
539
540 /*
541 * Because "st,breakinput" parameter is optional do not make probe
542 * failed if it doesn't exist.
543 */
544 if (nb <= 0)
545 return 0;
546
547 if (nb > MAX_BREAKINPUT)
548 return -EINVAL;
549
550 priv->num_breakinputs = nb;
551 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
552 ret = of_property_read_u32_array(np, "st,breakinput",
553 (u32 *)priv->breakinputs, array_size);
554 if (ret)
555 return ret;
556
557 for (i = 0; i < priv->num_breakinputs; i++) {
558 if (priv->breakinputs[i].index > 1 ||
559 priv->breakinputs[i].level > 1 ||
560 priv->breakinputs[i].filter > 15)
561 return -EINVAL;
562 }
563
564 return stm32_pwm_apply_breakinputs(priv);
565 }
566
stm32_pwm_detect_complementary(struct stm32_pwm * priv)567 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
568 {
569 u32 ccer;
570
571 /*
572 * If complementary bit doesn't exist writing 1 will have no
573 * effect so we can detect it.
574 */
575 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
576 regmap_read(priv->regmap, TIM_CCER, &ccer);
577 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
578
579 priv->have_complementary_output = (ccer != 0);
580 }
581
stm32_pwm_detect_channels(struct stm32_pwm * priv)582 static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
583 {
584 u32 ccer;
585 int npwm = 0;
586
587 /*
588 * If channels enable bits don't exist writing 1 will have no
589 * effect so we can detect and count them.
590 */
591 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
592 regmap_read(priv->regmap, TIM_CCER, &ccer);
593 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
594
595 if (ccer & TIM_CCER_CC1E)
596 npwm++;
597
598 if (ccer & TIM_CCER_CC2E)
599 npwm++;
600
601 if (ccer & TIM_CCER_CC3E)
602 npwm++;
603
604 if (ccer & TIM_CCER_CC4E)
605 npwm++;
606
607 return npwm;
608 }
609
stm32_pwm_probe(struct platform_device * pdev)610 static int stm32_pwm_probe(struct platform_device *pdev)
611 {
612 struct device *dev = &pdev->dev;
613 struct device_node *np = dev->of_node;
614 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
615 struct stm32_pwm *priv;
616 int ret;
617
618 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
619 if (!priv)
620 return -ENOMEM;
621
622 mutex_init(&priv->lock);
623 priv->regmap = ddata->regmap;
624 priv->clk = ddata->clk;
625 priv->max_arr = ddata->max_arr;
626
627 if (!priv->regmap || !priv->clk)
628 return -EINVAL;
629
630 ret = stm32_pwm_probe_breakinputs(priv, np);
631 if (ret)
632 return ret;
633
634 stm32_pwm_detect_complementary(priv);
635
636 priv->chip.dev = dev;
637 priv->chip.ops = &stm32pwm_ops;
638 priv->chip.npwm = stm32_pwm_detect_channels(priv);
639
640 ret = devm_pwmchip_add(dev, &priv->chip);
641 if (ret < 0)
642 return ret;
643
644 platform_set_drvdata(pdev, priv);
645
646 return 0;
647 }
648
stm32_pwm_suspend(struct device * dev)649 static int __maybe_unused stm32_pwm_suspend(struct device *dev)
650 {
651 struct stm32_pwm *priv = dev_get_drvdata(dev);
652 unsigned int i;
653 u32 ccer, mask;
654
655 /* Look for active channels */
656 ccer = active_channels(priv);
657
658 for (i = 0; i < priv->chip.npwm; i++) {
659 mask = TIM_CCER_CC1E << (i * 4);
660 if (ccer & mask) {
661 dev_err(dev, "PWM %u still in use by consumer %s\n",
662 i, priv->chip.pwms[i].label);
663 return -EBUSY;
664 }
665 }
666
667 return pinctrl_pm_select_sleep_state(dev);
668 }
669
stm32_pwm_resume(struct device * dev)670 static int __maybe_unused stm32_pwm_resume(struct device *dev)
671 {
672 struct stm32_pwm *priv = dev_get_drvdata(dev);
673 int ret;
674
675 ret = pinctrl_pm_select_default_state(dev);
676 if (ret)
677 return ret;
678
679 /* restore breakinput registers that may have been lost in low power */
680 return stm32_pwm_apply_breakinputs(priv);
681 }
682
683 static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
684
685 static const struct of_device_id stm32_pwm_of_match[] = {
686 { .compatible = "st,stm32-pwm", },
687 { /* end node */ },
688 };
689 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
690
691 static struct platform_driver stm32_pwm_driver = {
692 .probe = stm32_pwm_probe,
693 .driver = {
694 .name = "stm32-pwm",
695 .of_match_table = stm32_pwm_of_match,
696 .pm = &stm32_pwm_pm_ops,
697 },
698 };
699 module_platform_driver(stm32_pwm_driver);
700
701 MODULE_ALIAS("platform:stm32-pwm");
702 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
703 MODULE_LICENSE("GPL v2");
704
