1 /*
2  * Driver for the Gemini pin controller
3  *
4  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5  *
6  * This is a group-only pin controller.
7  */
8 #include <linux/err.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/of.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/regmap.h>
21 
22 #include "pinctrl-utils.h"
23 
24 #define DRIVER_NAME "pinctrl-gemini"
25 
26 /**
27  * struct gemini_pin_conf - information about configuring a pin
28  * @pin: the pin number
29  * @reg: config register
30  * @mask: the bits affecting the configuration of the pin
31  */
32 struct gemini_pin_conf {
33 	unsigned int pin;
34 	u32 reg;
35 	u32 mask;
36 };
37 
38 /**
39  * struct gemini_pmx - state holder for the gemini pin controller
40  * @dev: a pointer back to containing device
41  * @virtbase: the offset to the controller in virtual memory
42  * @map: regmap to access registers
43  * @is_3512: whether the SoC/package is the 3512 variant
44  * @is_3516: whether the SoC/package is the 3516 variant
45  * @flash_pin: whether the flash pin (extended pins for parallel
46  * flash) is set
47  * @confs: pin config information
48  * @nconfs: number of pin config information items
49  */
50 struct gemini_pmx {
51 	struct device *dev;
52 	struct pinctrl_dev *pctl;
53 	struct regmap *map;
54 	bool is_3512;
55 	bool is_3516;
56 	bool flash_pin;
57 	const struct gemini_pin_conf *confs;
58 	unsigned int nconfs;
59 };
60 
61 /**
62  * struct gemini_pin_group - describes a Gemini pin group
63  * @name: the name of this specific pin group
64  * @pins: an array of discrete physical pins used in this group, taken
65  *	from the driver-local pin enumeration space
66  * @num_pins: the number of pins in this group array, i.e. the number of
67  *	elements in .pins so we can iterate over that array
68  * @mask: bits to clear to enable this when doing pin muxing
69  * @value: bits to set to enable this when doing pin muxing
70  * @driving_mask: bitmask for the IO Pad driving register for this
71  *	group, if it supports altering the driving strength of
72  *	its lines.
73  */
74 struct gemini_pin_group {
75 	const char *name;
76 	const unsigned int *pins;
77 	const unsigned int num_pins;
78 	u32 mask;
79 	u32 value;
80 	u32 driving_mask;
81 };
82 
83 /* Some straight-forward control registers */
84 #define GLOBAL_WORD_ID		0x00
85 #define GLOBAL_STATUS		0x04
86 #define GLOBAL_STATUS_FLPIN	BIT(20)
87 #define GLOBAL_IODRIVE		0x10
88 #define GLOBAL_GMAC_CTRL_SKEW	0x1c
89 #define GLOBAL_GMAC0_DATA_SKEW	0x20
90 #define GLOBAL_GMAC1_DATA_SKEW	0x24
91 /*
92  * Global Miscellaneous Control Register
93  * This register controls all Gemini pad/pin multiplexing
94  *
95  * It is a tricky register though:
96  * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
97  *   be brought back online, so it means permanent disablement of the
98  *   corresponding pads.
99  * - For the bits named *_DISABLE, once you enable something, it cannot be
100  *   DISABLED again. So you select a flash configuration once, and then
101  *   you are stuck with it.
102  */
103 #define GLOBAL_MISC_CTRL	0x30
104 #define GEMINI_GMAC_IOSEL_MASK	GENMASK(28, 27)
105 /* Not really used */
106 #define GEMINI_GMAC_IOSEL_GMAC0_GMII	BIT(28)
107 /* Activated with GMAC1 */
108 #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
109 /* This will be the default */
110 #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
111 #define TVC_CLK_PAD_ENABLE	BIT(20)
112 #define PCI_CLK_PAD_ENABLE	BIT(17)
113 #define LPC_CLK_PAD_ENABLE	BIT(16)
114 #define TVC_PADS_ENABLE		BIT(9)
115 #define SSP_PADS_ENABLE		BIT(8)
116 #define LCD_PADS_ENABLE		BIT(7)
117 #define LPC_PADS_ENABLE		BIT(6)
118 #define PCI_PADS_ENABLE		BIT(5)
119 #define IDE_PADS_ENABLE		BIT(4)
120 #define DRAM_PADS_POWERDOWN	BIT(3)
121 #define NAND_PADS_DISABLE	BIT(2)
122 #define PFLASH_PADS_DISABLE	BIT(1)
123 #define SFLASH_PADS_DISABLE	BIT(0)
124 #define PADS_MASK		(GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
125 #define PADS_MAXBIT		27
126 
127 /* Ordered by bit index */
128 static const char * const gemini_padgroups[] = {
129 	"serial flash",
130 	"parallel flash",
131 	"NAND flash",
132 	"DRAM",
133 	"IDE",
134 	"PCI",
135 	"LPC",
136 	"LCD",
137 	"SSP",
138 	"TVC",
139 	NULL, NULL, NULL, NULL, NULL, NULL,
140 	"LPC CLK",
141 	"PCI CLK",
142 	NULL, NULL,
143 	"TVC CLK",
144 	NULL, NULL, NULL, NULL, NULL,
145 	"GMAC1",
146 };
147 
148 static const struct pinctrl_pin_desc gemini_3512_pins[] = {
149 	/* Row A */
150 	PINCTRL_PIN(0, "A1 VREF CTRL"),
151 	PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
152 	PINCTRL_PIN(2, "A3 DRAM CK"),
153 	PINCTRL_PIN(3, "A4 DRAM CK N"),
154 	PINCTRL_PIN(4, "A5 DRAM A5"),
155 	PINCTRL_PIN(5, "A6 DRAM CKE"),
156 	PINCTRL_PIN(6, "A7 DRAM DQ11"),
157 	PINCTRL_PIN(7, "A8 DRAM DQ0"),
158 	PINCTRL_PIN(8, "A9 DRAM DQ5"),
159 	PINCTRL_PIN(9, "A10 DRAM DQ6"),
160 	PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
161 	PINCTRL_PIN(11, "A12 DRAM BA1"),
162 	PINCTRL_PIN(12, "A13 DRAM A2"),
163 	PINCTRL_PIN(13, "A14 PCI GNT1 N"),
164 	PINCTRL_PIN(14, "A15 PCI REQ9 N"),
165 	PINCTRL_PIN(15, "A16 PCI REQ2 N"),
166 	PINCTRL_PIN(16, "A17 PCI REQ3 N"),
167 	PINCTRL_PIN(17, "A18 PCI AD31"),
168 	/* Row B */
169 	PINCTRL_PIN(18, "B1 VCCK CTRL"),
170 	PINCTRL_PIN(19, "B2 PWR EN"),
171 	PINCTRL_PIN(20, "B3 RTC CLKI"),
172 	PINCTRL_PIN(21, "B4 DRAM A4"),
173 	PINCTRL_PIN(22, "B5 DRAM A6"),
174 	PINCTRL_PIN(23, "B6 DRAM A12"),
175 	PINCTRL_PIN(24, "B7 DRAM DQS1"),
176 	PINCTRL_PIN(25, "B8 DRAM DQ15"),
177 	PINCTRL_PIN(26, "B9 DRAM DQ4"),
178 	PINCTRL_PIN(27, "B10 DRAM DQS0"),
179 	PINCTRL_PIN(28, "B11 DRAM WE N"),
180 	PINCTRL_PIN(29, "B12 DRAM A10"),
181 	PINCTRL_PIN(30, "B13 DRAM A3"),
182 	PINCTRL_PIN(31, "B14 PCI GNT0 N"),
183 	PINCTRL_PIN(32, "B15 PCI GNT3 N"),
184 	PINCTRL_PIN(33, "B16 PCI REQ1 N"),
185 	PINCTRL_PIN(34, "B17 PCI AD30"),
186 	PINCTRL_PIN(35, "B18 PCI AD29"),
187 	/* Row C */
188 	PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
189 	PINCTRL_PIN(37, "C2 XTALI"),
190 	PINCTRL_PIN(38, "C3 PWR BTN"),
191 	PINCTRL_PIN(39, "C4 RTC CLKO"),
192 	PINCTRL_PIN(40, "C5 DRAM A7"),
193 	PINCTRL_PIN(41, "C6 DRAM A11"),
194 	PINCTRL_PIN(42, "C7 DRAM DQ10"),
195 	PINCTRL_PIN(43, "C8 DRAM DQ14"),
196 	PINCTRL_PIN(44, "C9 DRAM DQ3"),
197 	PINCTRL_PIN(45, "C10 DRAM DQ7"),
198 	PINCTRL_PIN(46, "C11 DRAM CAS N"),
199 	PINCTRL_PIN(47, "C12 DRAM A0"),
200 	PINCTRL_PIN(48, "C13 PCI INT0 N"),
201 	PINCTRL_PIN(49, "C14 EXT RESET N"),
202 	PINCTRL_PIN(50, "C15 PCI GNT2 N"),
203 	PINCTRL_PIN(51, "C16 PCI AD28"),
204 	PINCTRL_PIN(52, "C17 PCI AD27"),
205 	PINCTRL_PIN(53, "C18 PCI AD26"),
206 	/* Row D */
207 	PINCTRL_PIN(54, "D1 AVCCKHA"),
208 	PINCTRL_PIN(55, "D2 AGNDIOHA"),
209 	PINCTRL_PIN(56, "D3 XTALO"),
210 	PINCTRL_PIN(57, "D4 AVCC3IOHA"),
211 	PINCTRL_PIN(58, "D5 DRAM A8"),
212 	PINCTRL_PIN(59, "D6 DRAM A9"),
213 	PINCTRL_PIN(60, "D7 DRAM DQ9"),
214 	PINCTRL_PIN(61, "D8 DRAM DQ13"),
215 	PINCTRL_PIN(62, "D9 DRAM DQ2"),
216 	PINCTRL_PIN(63, "D10 DRAM A13"),
217 	PINCTRL_PIN(64, "D11 DRAM RAS N"),
218 	PINCTRL_PIN(65, "D12 DRAM A1"),
219 	PINCTRL_PIN(66, "D13 PCI INTC N"),
220 	PINCTRL_PIN(67, "D14 PCI CLK"),
221 	PINCTRL_PIN(68, "D15 PCI AD25"),
222 	PINCTRL_PIN(69, "D16 PCI AD24"),
223 	PINCTRL_PIN(70, "D17 PCI CBE3 N"),
224 	PINCTRL_PIN(71, "D18 PCI AD23"),
225 	/* Row E */
226 	PINCTRL_PIN(72, "E1 AVCC3IOHA"),
227 	PINCTRL_PIN(73, "E2 EBG"),
228 	PINCTRL_PIN(74, "E3 AVCC3IOHB"),
229 	PINCTRL_PIN(75, "E4 REXT"),
230 	PINCTRL_PIN(76, "E5 GND"),
231 	PINCTRL_PIN(77, "E6 DRAM DQM1"),
232 	PINCTRL_PIN(78, "E7 DRAM DQ8"),
233 	PINCTRL_PIN(79, "E8 DRAM DQ12"),
234 	PINCTRL_PIN(80, "E9 DRAM DQ1"),
235 	PINCTRL_PIN(81, "E10 DRAM DQM0"),
236 	PINCTRL_PIN(82, "E11 DRAM BA0"),
237 	PINCTRL_PIN(83, "E12 PCI INTA N"),
238 	PINCTRL_PIN(84, "E13 PCI INTB N"),
239 	PINCTRL_PIN(85, "E14 GND"),
240 	PINCTRL_PIN(86, "E15 PCI AD22"),
241 	PINCTRL_PIN(87, "E16 PCI AD21"),
242 	PINCTRL_PIN(88, "E17 PCI AD20"),
243 	PINCTRL_PIN(89, "E18 PCI AD19"),
244 	/* Row F */
245 	PINCTRL_PIN(90, "F1 SATA0 RXDP"),
246 	PINCTRL_PIN(91, "F2 SATA0 RXDN"),
247 	PINCTRL_PIN(92, "F3 AGNDK 0"),
248 	PINCTRL_PIN(93, "F4 AVCC3 S"),
249 	PINCTRL_PIN(94, "F5 AVCCK P"),
250 	PINCTRL_PIN(95, "F6 GND"),
251 	PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
252 	PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
253 	PINCTRL_PIN(98, "F9 V1"),
254 	PINCTRL_PIN(99, "F10 V1"),
255 	PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
256 	PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
257 	PINCTRL_PIN(102, "F13 GND"),
258 	PINCTRL_PIN(103, "F14 PCI AD18"),
259 	PINCTRL_PIN(104, "F15 PCI AD17"),
260 	PINCTRL_PIN(105, "F16 PCI AD16"),
261 	PINCTRL_PIN(106, "F17 PCI CBE2 N"),
262 	PINCTRL_PIN(107, "F18 PCI FRAME N"),
263 	/* Row G */
264 	PINCTRL_PIN(108, "G1 SATA0 TXDP"),
265 	PINCTRL_PIN(109, "G2 SATA0 TXDN"),
266 	PINCTRL_PIN(110, "G3 AGNDK 1"),
267 	PINCTRL_PIN(111, "G4 AVCCK 0"),
268 	PINCTRL_PIN(112, "G5 TEST CLKOUT"),
269 	PINCTRL_PIN(113, "G6 AGND"),
270 	PINCTRL_PIN(114, "G7 GND"),
271 	PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
272 	PINCTRL_PIN(116, "G9 V1"),
273 	PINCTRL_PIN(117, "G10 V1"),
274 	PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
275 	PINCTRL_PIN(119, "G12 GND"),
276 	PINCTRL_PIN(120, "G13 VCC3IOHA"),
277 	PINCTRL_PIN(121, "G14 PCI IRDY N"),
278 	PINCTRL_PIN(122, "G15 PCI TRDY N"),
279 	PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
280 	PINCTRL_PIN(124, "G17 PCI STOP N"),
281 	PINCTRL_PIN(125, "G18 PCI PAR"),
282 	/* Row H */
283 	PINCTRL_PIN(126, "H1 SATA1 TXDP"),
284 	PINCTRL_PIN(127, "H2 SATA1 TXDN"),
285 	PINCTRL_PIN(128, "H3 AGNDK 2"),
286 	PINCTRL_PIN(129, "H4 AVCCK 1"),
287 	PINCTRL_PIN(130, "H5 AVCCK S"),
288 	PINCTRL_PIN(131, "H6 AVCCKHB"),
289 	PINCTRL_PIN(132, "H7 AGND"),
290 	PINCTRL_PIN(133, "H8 GND"),
291 	PINCTRL_PIN(134, "H9 GND"),
292 	PINCTRL_PIN(135, "H10 GND"),
293 	PINCTRL_PIN(136, "H11 GND"),
294 	PINCTRL_PIN(137, "H12 VCC3IOHA"),
295 	PINCTRL_PIN(138, "H13 VCC3IOHA"),
296 	PINCTRL_PIN(139, "H14 PCI CBE1 N"),
297 	PINCTRL_PIN(140, "H15 PCI AD15"),
298 	PINCTRL_PIN(141, "H16 PCI AD14"),
299 	PINCTRL_PIN(142, "H17 PCI AD13"),
300 	PINCTRL_PIN(143, "H18 PCI AD12"),
301 	/* Row J (for some reason I is skipped) */
302 	PINCTRL_PIN(144, "J1 SATA1 RXDP"),
303 	PINCTRL_PIN(145, "J2 SATA1 RXDN"),
304 	PINCTRL_PIN(146, "J3 AGNDK 3"),
305 	PINCTRL_PIN(147, "J4 AVCCK 2"),
306 	PINCTRL_PIN(148, "J5 IDE DA1"),
307 	PINCTRL_PIN(149, "J6 V1"),
308 	PINCTRL_PIN(150, "J7 V1"),
309 	PINCTRL_PIN(151, "J8 GND"),
310 	PINCTRL_PIN(152, "J9 GND"),
311 	PINCTRL_PIN(153, "J10 GND"),
312 	PINCTRL_PIN(154, "J11 GND"),
313 	PINCTRL_PIN(155, "J12 V1"),
314 	PINCTRL_PIN(156, "J13 V1"),
315 	PINCTRL_PIN(157, "J14 PCI AD11"),
316 	PINCTRL_PIN(158, "J15 PCI AD10"),
317 	PINCTRL_PIN(159, "J16 PCI AD9"),
318 	PINCTRL_PIN(160, "J17 PCI AD8"),
319 	PINCTRL_PIN(161, "J18 PCI CBE0 N"),
320 	/* Row K */
321 	PINCTRL_PIN(162, "K1 IDE CS1 N"),
322 	PINCTRL_PIN(163, "K2 IDE CS0 N"),
323 	PINCTRL_PIN(164, "K3 AVCCK 3"),
324 	PINCTRL_PIN(165, "K4 IDE DA2"),
325 	PINCTRL_PIN(166, "K5 IDE DA0"),
326 	PINCTRL_PIN(167, "K6 V1"),
327 	PINCTRL_PIN(168, "K7 V1"),
328 	PINCTRL_PIN(169, "K8 GND"),
329 	PINCTRL_PIN(170, "K9 GND"),
330 	PINCTRL_PIN(171, "K10 GND"),
331 	PINCTRL_PIN(172, "K11 GND"),
332 	PINCTRL_PIN(173, "K12 V1"),
333 	PINCTRL_PIN(174, "K13 V1"),
334 	PINCTRL_PIN(175, "K14 PCI AD3"),
335 	PINCTRL_PIN(176, "K15 PCI AD4"),
336 	PINCTRL_PIN(177, "K16 PCI AD5"),
337 	PINCTRL_PIN(178, "K17 PCI AD6"),
338 	PINCTRL_PIN(179, "K18 PCI AD7"),
339 	/* Row L */
340 	PINCTRL_PIN(180, "L1 IDE INTRQ"),
341 	PINCTRL_PIN(181, "L2 IDE DMACK N"),
342 	PINCTRL_PIN(182, "L3 IDE IORDY"),
343 	PINCTRL_PIN(183, "L4 IDE DIOR N"),
344 	PINCTRL_PIN(184, "L5 IDE DIOW N"),
345 	PINCTRL_PIN(185, "L6 VCC3IOHA"),
346 	PINCTRL_PIN(186, "L7 VCC3IOHA"),
347 	PINCTRL_PIN(187, "L8 GND"),
348 	PINCTRL_PIN(188, "L9 GND"),
349 	PINCTRL_PIN(189, "L10 GND"),
350 	PINCTRL_PIN(190, "L11 GND"),
351 	PINCTRL_PIN(191, "L12 VCC3IOHA"),
352 	PINCTRL_PIN(192, "L13 VCC3IOHA"),
353 	PINCTRL_PIN(193, "L14 GPIO0 30"),
354 	PINCTRL_PIN(194, "L15 GPIO0 31"),
355 	PINCTRL_PIN(195, "L16 PCI AD0"),
356 	PINCTRL_PIN(196, "L17 PCI AD1"),
357 	PINCTRL_PIN(197, "L18 PCI AD2"),
358 	/* Row M */
359 	PINCTRL_PIN(198, "M1 IDE DMARQ"),
360 	PINCTRL_PIN(199, "M2 IDE DD15"),
361 	PINCTRL_PIN(200, "M3 IDE DD0"),
362 	PINCTRL_PIN(201, "M4 IDE DD14"),
363 	PINCTRL_PIN(202, "M5 IDE DD1"),
364 	PINCTRL_PIN(203, "M6 VCC3IOHA"),
365 	PINCTRL_PIN(204, "M7 GND"),
366 	PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
367 	PINCTRL_PIN(206, "M9 V1"),
368 	PINCTRL_PIN(207, "M10 V1"),
369 	PINCTRL_PIN(208, "M11 VCC3IOHA"),
370 	PINCTRL_PIN(209, "M12 GND"),
371 	PINCTRL_PIN(210, "M13 VCC3IOHA"),
372 	PINCTRL_PIN(211, "M14 GPIO0 25"),
373 	PINCTRL_PIN(212, "M15 GPIO0 26"),
374 	PINCTRL_PIN(213, "M16 GPIO0 27"),
375 	PINCTRL_PIN(214, "M17 GPIO0 28"),
376 	PINCTRL_PIN(215, "M18 GPIO0 29"),
377 	/* Row N */
378 	PINCTRL_PIN(216, "N1 IDE DD13"),
379 	PINCTRL_PIN(217, "N2 IDE DD2"),
380 	PINCTRL_PIN(218, "N3 IDE DD12"),
381 	PINCTRL_PIN(219, "N4 IDE DD3"),
382 	PINCTRL_PIN(220, "N5 IDE DD11"),
383 	PINCTRL_PIN(221, "N6 GND"),
384 	PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
385 	PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
386 	PINCTRL_PIN(224, "N9 V1"),
387 	PINCTRL_PIN(225, "N10 V1"),
388 	PINCTRL_PIN(226, "N11 VCC3IOHA"),
389 	PINCTRL_PIN(227, "N12 VCC3IOHA"),
390 	PINCTRL_PIN(228, "N13 GND"),
391 	PINCTRL_PIN(229, "N14 GPIO0 20"),
392 	PINCTRL_PIN(230, "N15 GPIO0 21"),
393 	PINCTRL_PIN(231, "N16 GPIO0 22"),
394 	PINCTRL_PIN(232, "N17 GPIO0 23"),
395 	PINCTRL_PIN(233, "N18 GPIO0 24"),
396 	/* Row P (for some reason O is skipped) */
397 	PINCTRL_PIN(234, "P1 IDE DD4"),
398 	PINCTRL_PIN(235, "P2 IDE DD10"),
399 	PINCTRL_PIN(236, "P3 IDE DD5"),
400 	PINCTRL_PIN(237, "P4 IDE DD9"),
401 	PINCTRL_PIN(238, "P5 GND"),
402 	PINCTRL_PIN(239, "P6 USB XSCO"),
403 	PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
404 	PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
405 	PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
406 	PINCTRL_PIN(243, "P10 GMAC1 TXC"),
407 	PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
408 	PINCTRL_PIN(245, "P12 MODE SEL 1"),
409 	PINCTRL_PIN(246, "P13 GPIO1 28"),
410 	PINCTRL_PIN(247, "P14 GND"),
411 	PINCTRL_PIN(248, "P15 GPIO0 5"),
412 	PINCTRL_PIN(249, "P16 GPIO0 17"),
413 	PINCTRL_PIN(250, "P17 GPIO0 18"),
414 	PINCTRL_PIN(251, "P18 GPIO0 19"),
415 	/* Row R (for some reason Q us skipped) */
416 	PINCTRL_PIN(252, "R1 IDE DD6"),
417 	PINCTRL_PIN(253, "R2 IDE DD8"),
418 	PINCTRL_PIN(254, "R3 IDE DD7"),
419 	PINCTRL_PIN(255, "R4 IDE RESET N"),
420 	PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
421 	PINCTRL_PIN(257, "R6 USB XSCI"),
422 	PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
423 	PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
424 	PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
425 	PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
426 	PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
427 	PINCTRL_PIN(263, "R12 MODE SEL 0"),
428 	PINCTRL_PIN(264, "R13 MODE SEL 3"),
429 	PINCTRL_PIN(265, "R14 GPIO0 0"),
430 	PINCTRL_PIN(266, "R15 GPIO0 4"),
431 	PINCTRL_PIN(267, "R16 GPIO0 9"),
432 	PINCTRL_PIN(268, "R17 GPIO0 15"),
433 	PINCTRL_PIN(269, "R18 GPIO0 16"),
434 	/* Row T (for some reason S is skipped) */
435 	PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
436 	PINCTRL_PIN(271, "T2 ICE0 IDO"),
437 	PINCTRL_PIN(272, "T3 ICE0 ICK"),
438 	PINCTRL_PIN(273, "T4 ICE0 IMS"),
439 	PINCTRL_PIN(274, "T5 ICE0 IDI"),
440 	PINCTRL_PIN(275, "T6 USB RREF"),
441 	PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
442 	PINCTRL_PIN(277, "T8 GMAC0 RXC"),
443 	PINCTRL_PIN(278, "T9 GMAC0 CRS"),
444 	PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
445 	PINCTRL_PIN(280, "T11 GMAC1 RXC"),
446 	PINCTRL_PIN(281, "T12 GMAC1 CRS"),
447 	PINCTRL_PIN(282, "T13 EXT CLK"),
448 	PINCTRL_PIN(283, "T14 GPIO1 31"),
449 	PINCTRL_PIN(284, "T15 GPIO0 3"),
450 	PINCTRL_PIN(285, "T16 GPIO0 8"),
451 	PINCTRL_PIN(286, "T17 GPIO0 12"),
452 	PINCTRL_PIN(287, "T18 GPIO0 14"),
453 	/* Row U */
454 	PINCTRL_PIN(288, "U1 ICE0 IRST N"),
455 	PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
456 	PINCTRL_PIN(290, "U3 USB0 DP"),
457 	PINCTRL_PIN(291, "U4 USB VCCA U20"),
458 	PINCTRL_PIN(292, "U5 USB1 DP"),
459 	PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
460 	PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
461 	PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
462 	PINCTRL_PIN(296, "U9 GMAC1 COL"),
463 	PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
464 	PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
465 	PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
466 	PINCTRL_PIN(300, "U13 MODE SEL 2"),
467 	PINCTRL_PIN(301, "U14 GPIO1 30"),
468 	PINCTRL_PIN(302, "U15 GPIO0 2"),
469 	PINCTRL_PIN(303, "U16 GPIO0 7"),
470 	PINCTRL_PIN(304, "U17 GPIO0 11"),
471 	PINCTRL_PIN(305, "U18 GPIO0 13"),
472 	/* Row V */
473 	PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
474 	PINCTRL_PIN(307, "V2 USB0 DM"),
475 	PINCTRL_PIN(308, "V3 USB GNDA U20"),
476 	PINCTRL_PIN(309, "V4 USB1 DM"),
477 	PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
478 	PINCTRL_PIN(311, "V6 GMAC0 COL"),
479 	PINCTRL_PIN(312, "V7 GMAC0 TXC"),
480 	PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
481 	PINCTRL_PIN(314, "V9 REF CLK"),
482 	PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
483 	PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
484 	PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
485 	PINCTRL_PIN(318, "V13 M30 CLK"),
486 	PINCTRL_PIN(319, "V14 GPIO1 29"),
487 	PINCTRL_PIN(320, "V15 GPIO0 1"),
488 	PINCTRL_PIN(321, "V16 GPIO0 6"),
489 	PINCTRL_PIN(322, "V17 GPIO0 10"),
490 	PINCTRL_PIN(323, "V18 SYS RESET N"),
491 };
492 
493 
494 /* Digital ground */
495 static const unsigned int gnd_3512_pins[] = {
496 	76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
497 	170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
498 };
499 
500 static const unsigned int dram_3512_pins[] = {
501 	2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
502 	30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
503 	78, 79, 80, 81, 82
504 };
505 
506 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
507 
508 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
509 
510 static const unsigned int system_3512_pins[] = {
511 	318, 264, 300, 245, 263, 282, 314, 323, 49,
512 };
513 
514 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
515 
516 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
517 
518 static const unsigned int ide_3512_pins[] = {
519 	162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
520 	216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
521 };
522 
523 static const unsigned int sata_3512_pins[] = {
524 	75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
525 	128, 127, 126, 147, 146, 145, 144, 164
526 };
527 
528 static const unsigned int usb_3512_pins[] = {
529 	306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
530 };
531 
532 /* GMII, ethernet pins */
533 static const unsigned int gmii_gmac0_3512_pins[] = {
534 	240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
535 };
536 
537 static const unsigned int gmii_gmac1_3512_pins[] = {
538 	243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
539 };
540 
541 static const unsigned int pci_3512_pins[] = {
542 	13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
543 	70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
544 	124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
545 	178, 179, 195, 196, 197
546 };
547 
548 /*
549  * Apparently the LPC interface is using the PCICLK for the clocking so
550  * PCI needs to be active at the same time.
551  */
552 static const unsigned int lpc_3512_pins[] = {
553 	285, /* LPC_LAD[0] */
554 	304, /* LPC_SERIRQ */
555 	286, /* LPC_LAD[2] */
556 	305, /* LPC_LFRAME# */
557 	287, /* LPC_LAD[3] */
558 	268, /* LPC_LAD[1] */
559 };
560 
561 /* Character LCD */
562 static const unsigned int lcd_3512_pins[] = {
563 	262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
564 };
565 
566 static const unsigned int ssp_3512_pins[] = {
567 	285, /* SSP_97RST# SSP AC97 Reset, active low */
568 	304, /* SSP_FSC */
569 	286, /* SSP_ECLK */
570 	305, /* SSP_TXD */
571 	287, /* SSP_RXD */
572 	268, /* SSP_SCLK */
573 };
574 
575 static const unsigned int uart_rxtx_3512_pins[] = {
576 	267, /* UART_SIN serial input, RX */
577 	322, /* UART_SOUT serial output, TX */
578 };
579 
580 static const unsigned int uart_modem_3512_pins[] = {
581 	285, /* UART_NDCD DCD carrier detect */
582 	304, /* UART_NDTR DTR data terminal ready */
583 	286, /* UART_NDSR DSR data set ready */
584 	305, /* UART_NRTS RTS request to send */
585 	287, /* UART_NCTS CTS clear to send */
586 	268, /* UART_NRI RI ring indicator */
587 };
588 
589 static const unsigned int tvc_3512_pins[] = {
590 	246, /* TVC_DATA[0] */
591 	319, /* TVC_DATA[1] */
592 	301, /* TVC_DATA[2] */
593 	283, /* TVC_DATA[3] */
594 	265, /* TVC_CLK */
595 	320, /* TVC_DATA[4] */
596 	302, /* TVC_DATA[5] */
597 	284, /* TVC_DATA[6] */
598 	266, /* TVC_DATA[7] */
599 };
600 
601 /* NAND flash pins */
602 static const unsigned int nflash_3512_pins[] = {
603 	199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
604 	253, 254, 249, 250, 232, 233, 211, 193, 194
605 };
606 
607 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
608 static const unsigned int pflash_3512_pins[] = {
609 	162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
610 	234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
611 	214, 215, 193, 194
612 };
613 
614 /*
615  * The parallel flash can be set up in a 26-bit address bus mode exposing
616  * A[0-15] (A[15] takes the place of ALE), but it has the
617  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
618  * used at the same time.
619  */
620 static const unsigned int pflash_3512_pins_extended[] = {
621 	162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
622 	234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
623 	214, 215, 193, 194,
624 	/* The extra pins */
625 	296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
626 	265,
627 };
628 
629 /* Serial flash pins CE0, CE1, DI, DO, CK */
630 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
631 
632 /* The GPIO0A (0) pin overlap with TVC and extended parallel flash */
633 static const unsigned int gpio0a_3512_pins[] = { 265 };
634 
635 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
636 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
637 
638 /* The GPIO0C (5-7) pins overlap with ICE */
639 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
640 
641 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
642 static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
643 
644 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
645 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
646 
647 /* The GPIO0F (16) pins overlap with LCD */
648 static const unsigned int gpio0f_3512_pins[] = { 269 };
649 
650 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
651 static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
652 
653 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
654 static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
655 
656 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
657 static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
658 
659 /* The GPIO0J (23) pins overlap with all flash */
660 static const unsigned int gpio0j_3512_pins[] = { 232 };
661 
662 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
663 static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
664 
665 /* The GPIO0L (26-29) pins overlap with parallel flash */
666 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
667 
668 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
669 static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
670 
671 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
672 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
673 
674 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
675 static const unsigned int gpio1b_3512_pins[] = {
676 	180, 181, 182, 183, 184, 198, 255
677 };
678 
679 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
680 static const unsigned int gpio1c_3512_pins[] = {
681 	199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
682 	252, 253, 254
683 };
684 
685 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
686 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
687 
688 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
689 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
690 
691 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
692 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
693 
694 /* The GPIO2C (8-31) pins overlap with PCI */
695 static const unsigned int gpio2c_3512_pins[] = {
696 	17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
697 	140, 141, 142, 143, 157, 158, 159, 160
698 };
699 
700 /* Groups for the 3512 SoC/package */
701 static const struct gemini_pin_group gemini_3512_pin_groups[] = {
702 	{
703 		.name = "gndgrp",
704 		.pins = gnd_3512_pins,
705 		.num_pins = ARRAY_SIZE(gnd_3512_pins),
706 	},
707 	{
708 		.name = "dramgrp",
709 		.pins = dram_3512_pins,
710 		.num_pins = ARRAY_SIZE(dram_3512_pins),
711 		.mask = DRAM_PADS_POWERDOWN,
712 	},
713 	{
714 		.name = "rtcgrp",
715 		.pins = rtc_3512_pins,
716 		.num_pins = ARRAY_SIZE(rtc_3512_pins),
717 	},
718 	{
719 		.name = "powergrp",
720 		.pins = power_3512_pins,
721 		.num_pins = ARRAY_SIZE(power_3512_pins),
722 	},
723 	{
724 		.name = "systemgrp",
725 		.pins = system_3512_pins,
726 		.num_pins = ARRAY_SIZE(system_3512_pins),
727 	},
728 	{
729 		.name = "vcontrolgrp",
730 		.pins = vcontrol_3512_pins,
731 		.num_pins = ARRAY_SIZE(vcontrol_3512_pins),
732 	},
733 	{
734 		.name = "icegrp",
735 		.pins = ice_3512_pins,
736 		.num_pins = ARRAY_SIZE(ice_3512_pins),
737 		/* Conflict with some GPIO groups */
738 	},
739 	{
740 		.name = "idegrp",
741 		.pins = ide_3512_pins,
742 		.num_pins = ARRAY_SIZE(ide_3512_pins),
743 		/* Conflict with all flash usage */
744 		.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
745 			PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
746 		.driving_mask = GENMASK(21, 20),
747 	},
748 	{
749 		.name = "satagrp",
750 		.pins = sata_3512_pins,
751 		.num_pins = ARRAY_SIZE(sata_3512_pins),
752 	},
753 	{
754 		.name = "usbgrp",
755 		.pins = usb_3512_pins,
756 		.num_pins = ARRAY_SIZE(usb_3512_pins),
757 	},
758 	{
759 		.name = "gmii_gmac0_grp",
760 		.pins = gmii_gmac0_3512_pins,
761 		.num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
762 		.driving_mask = GENMASK(17, 16),
763 	},
764 	{
765 		.name = "gmii_gmac1_grp",
766 		.pins = gmii_gmac1_3512_pins,
767 		.num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
768 		/* Bring out RGMII on the GMAC1 pins */
769 		.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
770 		.driving_mask = GENMASK(19, 18),
771 	},
772 	{
773 		.name = "pcigrp",
774 		.pins = pci_3512_pins,
775 		.num_pins = ARRAY_SIZE(pci_3512_pins),
776 		/* Conflict only with GPIO2 */
777 		.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
778 		.driving_mask = GENMASK(23, 22),
779 	},
780 	{
781 		.name = "lpcgrp",
782 		.pins = lpc_3512_pins,
783 		.num_pins = ARRAY_SIZE(lpc_3512_pins),
784 		/* Conflict with SSP and UART modem pins */
785 		.mask = SSP_PADS_ENABLE,
786 		.value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
787 	},
788 	{
789 		.name = "lcdgrp",
790 		.pins = lcd_3512_pins,
791 		.num_pins = ARRAY_SIZE(lcd_3512_pins),
792 		/* Conflict with TVC and ICE */
793 		.mask = TVC_PADS_ENABLE,
794 		.value = LCD_PADS_ENABLE,
795 	},
796 	{
797 		.name = "sspgrp",
798 		.pins = ssp_3512_pins,
799 		.num_pins = ARRAY_SIZE(ssp_3512_pins),
800 		/* Conflict with LPC and UART modem pins */
801 		.mask = LPC_PADS_ENABLE,
802 		.value = SSP_PADS_ENABLE,
803 	},
804 	{
805 		.name = "uartrxtxgrp",
806 		.pins = uart_rxtx_3512_pins,
807 		.num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
808 		/* No conflicts except GPIO */
809 	},
810 	{
811 		.name = "uartmodemgrp",
812 		.pins = uart_modem_3512_pins,
813 		.num_pins = ARRAY_SIZE(uart_modem_3512_pins),
814 		/*
815 		 * Conflict with LPC and SSP,
816 		 * so when those are both disabled, modem UART can thrive.
817 		 */
818 		.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
819 	},
820 	{
821 		.name = "tvcgrp",
822 		.pins = tvc_3512_pins,
823 		.num_pins = ARRAY_SIZE(tvc_3512_pins),
824 		/* Conflict with character LCD and ICE */
825 		.mask = LCD_PADS_ENABLE,
826 		.value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
827 	},
828 	/*
829 	 * The construction is done such that it is possible to use a serial
830 	 * flash together with a NAND or parallel (NOR) flash, but it is not
831 	 * possible to use NAND and parallel flash together. To use serial
832 	 * flash with one of the two others, the muxbits need to be flipped
833 	 * around before any access.
834 	 */
835 	{
836 		.name = "nflashgrp",
837 		.pins = nflash_3512_pins,
838 		.num_pins = ARRAY_SIZE(nflash_3512_pins),
839 		/* Conflict with IDE, parallel and serial flash */
840 		.mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
841 		.value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
842 	},
843 	{
844 		.name = "pflashgrp",
845 		.pins = pflash_3512_pins,
846 		.num_pins = ARRAY_SIZE(pflash_3512_pins),
847 		/* Conflict with IDE, NAND and serial flash */
848 		.mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
849 		.value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
850 	},
851 	{
852 		.name = "sflashgrp",
853 		.pins = sflash_3512_pins,
854 		.num_pins = ARRAY_SIZE(sflash_3512_pins),
855 		/* Conflict with IDE, NAND and parallel flash */
856 		.mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
857 		.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
858 	},
859 	{
860 		.name = "gpio0agrp",
861 		.pins = gpio0a_3512_pins,
862 		.num_pins = ARRAY_SIZE(gpio0a_3512_pins),
863 		/* Conflict with TVC */
864 		.mask = TVC_PADS_ENABLE,
865 	},
866 	{
867 		.name = "gpio0bgrp",
868 		.pins = gpio0b_3512_pins,
869 		.num_pins = ARRAY_SIZE(gpio0b_3512_pins),
870 		/* Conflict with TVC and ICE */
871 		.mask = TVC_PADS_ENABLE,
872 	},
873 	{
874 		.name = "gpio0cgrp",
875 		.pins = gpio0c_3512_pins,
876 		.num_pins = ARRAY_SIZE(gpio0c_3512_pins),
877 		/* Conflict with ICE */
878 	},
879 	{
880 		.name = "gpio0dgrp",
881 		.pins = gpio0d_3512_pins,
882 		.num_pins = ARRAY_SIZE(gpio0d_3512_pins),
883 		/* Conflict with UART RX/TX */
884 	},
885 	{
886 		.name = "gpio0egrp",
887 		.pins = gpio0e_3512_pins,
888 		.num_pins = ARRAY_SIZE(gpio0e_3512_pins),
889 		/* Conflict with LPC, UART modem pins, SSP */
890 		.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
891 	},
892 	{
893 		.name = "gpio0fgrp",
894 		.pins = gpio0f_3512_pins,
895 		.num_pins = ARRAY_SIZE(gpio0f_3512_pins),
896 		/* Conflict with LCD */
897 		.mask = LCD_PADS_ENABLE,
898 	},
899 	{
900 		.name = "gpio0ggrp",
901 		.pins = gpio0g_3512_pins,
902 		.num_pins = ARRAY_SIZE(gpio0g_3512_pins),
903 		/* Conflict with NAND flash */
904 		.value = NAND_PADS_DISABLE,
905 	},
906 	{
907 		.name = "gpio0hgrp",
908 		.pins = gpio0h_3512_pins,
909 		.num_pins = ARRAY_SIZE(gpio0h_3512_pins),
910 		/* Conflict with parallel flash */
911 		.value = PFLASH_PADS_DISABLE,
912 	},
913 	{
914 		.name = "gpio0igrp",
915 		.pins = gpio0i_3512_pins,
916 		.num_pins = ARRAY_SIZE(gpio0i_3512_pins),
917 		/* Conflict with serial flash */
918 		.value = SFLASH_PADS_DISABLE,
919 	},
920 	{
921 		.name = "gpio0jgrp",
922 		.pins = gpio0j_3512_pins,
923 		.num_pins = ARRAY_SIZE(gpio0j_3512_pins),
924 		/* Conflict with all flash */
925 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
926 			SFLASH_PADS_DISABLE,
927 	},
928 	{
929 		.name = "gpio0kgrp",
930 		.pins = gpio0k_3512_pins,
931 		.num_pins = ARRAY_SIZE(gpio0k_3512_pins),
932 		/* Conflict with all flash and LCD */
933 		.mask = LCD_PADS_ENABLE,
934 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
935 			SFLASH_PADS_DISABLE,
936 	},
937 	{
938 		.name = "gpio0lgrp",
939 		.pins = gpio0l_3512_pins,
940 		.num_pins = ARRAY_SIZE(gpio0l_3512_pins),
941 		/* Conflict with parallel flash */
942 		.value = PFLASH_PADS_DISABLE,
943 	},
944 	{
945 		.name = "gpio0mgrp",
946 		.pins = gpio0m_3512_pins,
947 		.num_pins = ARRAY_SIZE(gpio0m_3512_pins),
948 		/* Conflict with parallel and NAND flash */
949 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
950 	},
951 	{
952 		.name = "gpio1agrp",
953 		.pins = gpio1a_3512_pins,
954 		.num_pins = ARRAY_SIZE(gpio1a_3512_pins),
955 		/* Conflict with IDE and parallel flash */
956 		.mask = IDE_PADS_ENABLE,
957 		.value = PFLASH_PADS_DISABLE,
958 	},
959 	{
960 		.name = "gpio1bgrp",
961 		.pins = gpio1b_3512_pins,
962 		.num_pins = ARRAY_SIZE(gpio1b_3512_pins),
963 		/* Conflict with IDE only */
964 		.mask = IDE_PADS_ENABLE,
965 	},
966 	{
967 		.name = "gpio1cgrp",
968 		.pins = gpio1c_3512_pins,
969 		.num_pins = ARRAY_SIZE(gpio1c_3512_pins),
970 		/* Conflict with IDE, parallel and NAND flash */
971 		.mask = IDE_PADS_ENABLE,
972 		.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
973 	},
974 	{
975 		.name = "gpio1dgrp",
976 		.pins = gpio1d_3512_pins,
977 		.num_pins = ARRAY_SIZE(gpio1d_3512_pins),
978 		/* Conflict with LCD and TVC */
979 		.mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
980 	},
981 	{
982 		.name = "gpio2agrp",
983 		.pins = gpio2a_3512_pins,
984 		.num_pins = ARRAY_SIZE(gpio2a_3512_pins),
985 		.mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
986 		/* Conflict with GMII GMAC1 and extended parallel flash */
987 	},
988 	{
989 		.name = "gpio2bgrp",
990 		.pins = gpio2b_3512_pins,
991 		.num_pins = ARRAY_SIZE(gpio2b_3512_pins),
992 		/* Conflict with GMII GMAC1, extended parallel flash and LCD */
993 		.mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
994 	},
995 	{
996 		.name = "gpio2cgrp",
997 		.pins = gpio2c_3512_pins,
998 		.num_pins = ARRAY_SIZE(gpio2c_3512_pins),
999 		/* Conflict with PCI */
1000 		.mask = PCI_PADS_ENABLE,
1001 	},
1002 };
1003 
1004 /* Pin names for the pinmux subsystem, 3516 variant */
1005 static const struct pinctrl_pin_desc gemini_3516_pins[] = {
1006 	/* Row A */
1007 	PINCTRL_PIN(0, "A1 AVCC3IOHA"),
1008 	PINCTRL_PIN(1, "A2 DRAM CK N"),
1009 	PINCTRL_PIN(2, "A3 DRAM CK"),
1010 	PINCTRL_PIN(3, "A4 DRAM DQM1"),
1011 	PINCTRL_PIN(4, "A5 DRAM DQ9"),
1012 	PINCTRL_PIN(5, "A6 DRAM DQ13"),
1013 	PINCTRL_PIN(6, "A7 DRAM DQ1"),
1014 	PINCTRL_PIN(7, "A8 DRAM DQ2"),
1015 	PINCTRL_PIN(8, "A9 DRAM DQ4"),
1016 	PINCTRL_PIN(9, "A10 DRAM VREF"),
1017 	PINCTRL_PIN(10, "A11 DRAM DQ24"),
1018 	PINCTRL_PIN(11, "A12 DRAM DQ28"),
1019 	PINCTRL_PIN(12, "A13 DRAM DQ30"),
1020 	PINCTRL_PIN(13, "A14 DRAM DQ18"),
1021 	PINCTRL_PIN(14, "A15 DRAM DQ21"),
1022 	PINCTRL_PIN(15, "A16 DRAM CAS_N"),
1023 	PINCTRL_PIN(16, "A17 DRAM BA1"),
1024 	PINCTRL_PIN(17, "A18 PCI INTA N"),
1025 	PINCTRL_PIN(18, "A19 PCI INTB N"),
1026 	PINCTRL_PIN(19, "A20 PCI INTC N"),
1027 	/* Row B */
1028 	PINCTRL_PIN(20, "B1 PWR EN"),
1029 	PINCTRL_PIN(21, "B2 GND"),
1030 	PINCTRL_PIN(22, "B3 RTC CLKO"),
1031 	PINCTRL_PIN(23, "B4 DRAM A5"),
1032 	PINCTRL_PIN(24, "B5 DRAM A6"),
1033 	PINCTRL_PIN(25, "B6 DRAM DQS1"),
1034 	PINCTRL_PIN(26, "B7 DRAM DQ11"),
1035 	PINCTRL_PIN(27, "B8 DRAM DQ0"),
1036 	PINCTRL_PIN(28, "B9 DRAM DQS0"),
1037 	PINCTRL_PIN(29, "B10 DRAM DQ7"),
1038 	PINCTRL_PIN(30, "B11 DRAM DQS3"),
1039 	PINCTRL_PIN(31, "B12 DRAM DQ27"),
1040 	PINCTRL_PIN(32, "B13 DRAM DQ31"),
1041 	PINCTRL_PIN(33, "B14 DRAM DQ20"),
1042 	PINCTRL_PIN(34, "B15 DRAM DQS2"),
1043 	PINCTRL_PIN(35, "B16 DRAM WE N"),
1044 	PINCTRL_PIN(36, "B17 DRAM A10"),
1045 	PINCTRL_PIN(37, "B18 DRAM A2"),
1046 	PINCTRL_PIN(38, "B19 GND"),
1047 	PINCTRL_PIN(39, "B20 PCI GNT0 N"),
1048 	/* Row C */
1049 	PINCTRL_PIN(40, "C1 AGNDIOHA"),
1050 	PINCTRL_PIN(41, "C2 XTALI"),
1051 	PINCTRL_PIN(42, "C3 GND"),
1052 	PINCTRL_PIN(43, "C4 RTC CLKI"),
1053 	PINCTRL_PIN(44, "C5 DRAM A12"),
1054 	PINCTRL_PIN(45, "C6 DRAM A11"),
1055 	PINCTRL_PIN(46, "C7 DRAM DQ8"),
1056 	PINCTRL_PIN(47, "C8 DRAM DQ10"),
1057 	PINCTRL_PIN(48, "C9 DRAM DQ3"),
1058 	PINCTRL_PIN(49, "C10 DRAM DQ6"),
1059 	PINCTRL_PIN(50, "C11 DRAM DQM0"),
1060 	PINCTRL_PIN(51, "C12 DRAM DQ26"),
1061 	PINCTRL_PIN(52, "C13 DRAM DQ16"),
1062 	PINCTRL_PIN(53, "C14 DRAM DQ22"),
1063 	PINCTRL_PIN(54, "C15 DRAM DQM2"),
1064 	PINCTRL_PIN(55, "C16 DRAM BA0"),
1065 	PINCTRL_PIN(56, "C17 DRAM A3"),
1066 	PINCTRL_PIN(57, "C18 GND"),
1067 	PINCTRL_PIN(58, "C19 PCI GNT1 N"),
1068 	PINCTRL_PIN(59, "C20 PCI REQ2 N"),
1069 	/* Row D */
1070 	PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
1071 	PINCTRL_PIN(61, "D2 AVCCKHA"),
1072 	PINCTRL_PIN(62, "D3 XTALO"),
1073 	PINCTRL_PIN(63, "D4 GND"),
1074 	PINCTRL_PIN(64, "D5 CIR RXD"),
1075 	PINCTRL_PIN(65, "D6 DRAM A7"),
1076 	PINCTRL_PIN(66, "D7 DRAM A4"),
1077 	PINCTRL_PIN(67, "D8 DRAM A8"),
1078 	PINCTRL_PIN(68, "D9 DRAM CKE"),
1079 	PINCTRL_PIN(69, "D10 DRAM DQ14"),
1080 	PINCTRL_PIN(70, "D11 DRAM DQ5"),
1081 	PINCTRL_PIN(71, "D12 DRAM DQ25"),
1082 	PINCTRL_PIN(72, "D13 DRAM DQ17"),
1083 	PINCTRL_PIN(73, "D14 DRAM DQ23"),
1084 	PINCTRL_PIN(74, "D15 DRAM RAS N"),
1085 	PINCTRL_PIN(75, "D16 DRAM A1"),
1086 	PINCTRL_PIN(76, "D17 GND"),
1087 	PINCTRL_PIN(77, "D18 EXT RESET N"),
1088 	PINCTRL_PIN(78, "D19 PCI REQ1 N"),
1089 	PINCTRL_PIN(79, "D20 PCI REQ3 N"),
1090 	/* Row E */
1091 	PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
1092 	PINCTRL_PIN(81, "E2 VREF CTRL"),
1093 	PINCTRL_PIN(82, "E3 CIR RST N"),
1094 	PINCTRL_PIN(83, "E4 PWR BTN"),
1095 	PINCTRL_PIN(84, "E5 GND"),
1096 	PINCTRL_PIN(85, "E6 CIR TXD"),
1097 	PINCTRL_PIN(86, "E7 VCCK CTRL"),
1098 	PINCTRL_PIN(87, "E8 DRAM A9"),
1099 	PINCTRL_PIN(88, "E9 DRAM DQ12"),
1100 	PINCTRL_PIN(89, "E10 DRAM DQ15"),
1101 	PINCTRL_PIN(90, "E11 DRAM DQM3"),
1102 	PINCTRL_PIN(91, "E12 DRAM DQ29"),
1103 	PINCTRL_PIN(92, "E13 DRAM DQ19"),
1104 	PINCTRL_PIN(93, "E14 DRAM A13"),
1105 	PINCTRL_PIN(94, "E15 DRAM A0"),
1106 	PINCTRL_PIN(95, "E16 GND"),
1107 	PINCTRL_PIN(96, "E17 PCI INTD N"),
1108 	PINCTRL_PIN(97, "E18 PCI GNT3 N"),
1109 	PINCTRL_PIN(98, "E19 PCI AD29"),
1110 	PINCTRL_PIN(99, "E20 PCI AD28"),
1111 	/* Row F */
1112 	PINCTRL_PIN(100, "F1 AVCCKHB"),
1113 	PINCTRL_PIN(101, "F2 AVCCK P"),
1114 	PINCTRL_PIN(102, "F3 EBG"),
1115 	PINCTRL_PIN(103, "F4 REXT"),
1116 	PINCTRL_PIN(104, "F5 AVCC3IOHB"),
1117 	PINCTRL_PIN(105, "F6 GND"),
1118 	PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
1119 	PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
1120 	PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
1121 	PINCTRL_PIN(109, "F10 V1"),
1122 	PINCTRL_PIN(110, "F11 V1"),
1123 	PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
1124 	PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
1125 	PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
1126 	PINCTRL_PIN(114, "F15 GND"),
1127 	PINCTRL_PIN(115, "F16 PCI CLK"),
1128 	PINCTRL_PIN(116, "F17 PCI GNT2 N"),
1129 	PINCTRL_PIN(117, "F18 PCI AD31"),
1130 	PINCTRL_PIN(118, "F19 PCI AD26"),
1131 	PINCTRL_PIN(119, "F20 PCI CBE3 N"),
1132 	/* Row G */
1133 	PINCTRL_PIN(120, "G1 SATA0 RXDP"),
1134 	PINCTRL_PIN(121, "G2 SATA0 RXDN"),
1135 	PINCTRL_PIN(122, "G3 AGNDK 0"),
1136 	PINCTRL_PIN(123, "G4 AVCCK S"),
1137 	PINCTRL_PIN(124, "G5 AVCC3 S"),
1138 	PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
1139 	PINCTRL_PIN(126, "G7 GND"),
1140 	PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
1141 	PINCTRL_PIN(128, "G9 V1"),
1142 	PINCTRL_PIN(129, "G10 V1"),
1143 	PINCTRL_PIN(130, "G11 V1"),
1144 	PINCTRL_PIN(131, "G12 V1"),
1145 	PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
1146 	PINCTRL_PIN(133, "G14 GND"),
1147 	PINCTRL_PIN(134, "G15 VCC3IOHA"),
1148 	PINCTRL_PIN(135, "G16 PCI REQ0 N"),
1149 	PINCTRL_PIN(136, "G17 PCI AD30"),
1150 	PINCTRL_PIN(137, "G18 PCI AD24"),
1151 	PINCTRL_PIN(138, "G19 PCI AD23"),
1152 	PINCTRL_PIN(139, "G20 PCI AD21"),
1153 	/* Row H */
1154 	PINCTRL_PIN(140, "H1 SATA0 TXDP"),
1155 	PINCTRL_PIN(141, "H2 SATA0 TXDN"),
1156 	PINCTRL_PIN(142, "H3 AGNDK 1"),
1157 	PINCTRL_PIN(143, "H4 AVCCK 0"),
1158 	PINCTRL_PIN(144, "H5 TEST CLKOUT"),
1159 	PINCTRL_PIN(145, "H6 AGND"),
1160 	PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
1161 	PINCTRL_PIN(147, "H8 GND"),
1162 	PINCTRL_PIN(148, "H9 GND"),
1163 	PINCTRL_PIN(149, "H10 GDN"),
1164 	PINCTRL_PIN(150, "H11 GND"),
1165 	PINCTRL_PIN(151, "H12 GND"),
1166 	PINCTRL_PIN(152, "H13 GND"),
1167 	PINCTRL_PIN(153, "H14 VCC3IOHA"),
1168 	PINCTRL_PIN(154, "H15 VCC3IOHA"),
1169 	PINCTRL_PIN(155, "H16 PCI AD27"),
1170 	PINCTRL_PIN(156, "H17 PCI AD25"),
1171 	PINCTRL_PIN(157, "H18 PCI AD22"),
1172 	PINCTRL_PIN(158, "H19 PCI AD18"),
1173 	PINCTRL_PIN(159, "H20 PCI AD17"),
1174 	/* Row J (for some reason I is skipped) */
1175 	PINCTRL_PIN(160, "J1 SATA1 TXDP"),
1176 	PINCTRL_PIN(161, "J2 SATA1 TXDN"),
1177 	PINCTRL_PIN(162, "J3 AGNDK 2"),
1178 	PINCTRL_PIN(163, "J4 AVCCK 1"),
1179 	PINCTRL_PIN(164, "J5 AGND"),
1180 	PINCTRL_PIN(165, "J6 AGND"),
1181 	PINCTRL_PIN(166, "J7 V1"),
1182 	PINCTRL_PIN(167, "J8 GND"),
1183 	PINCTRL_PIN(168, "J9 GND"),
1184 	PINCTRL_PIN(169, "J10 GND"),
1185 	PINCTRL_PIN(170, "J11 GND"),
1186 	PINCTRL_PIN(171, "J12 GND"),
1187 	PINCTRL_PIN(172, "J13 GND"),
1188 	PINCTRL_PIN(173, "J14 V1"),
1189 	PINCTRL_PIN(174, "J15 VCC3IOHA"),
1190 	PINCTRL_PIN(175, "J16 PCI AD19"),
1191 	PINCTRL_PIN(176, "J17 PCI AD20"),
1192 	PINCTRL_PIN(177, "J18 PCI AD16"),
1193 	PINCTRL_PIN(178, "J19 PCI CBE2 N"),
1194 	PINCTRL_PIN(179, "J20 PCI FRAME N"),
1195 	/* Row K */
1196 	PINCTRL_PIN(180, "K1 SATA1 RXDP"),
1197 	PINCTRL_PIN(181, "K2 SATA1 RXDN"),
1198 	PINCTRL_PIN(182, "K3 AGNDK 3"),
1199 	PINCTRL_PIN(183, "K4 AVCCK 2"),
1200 	PINCTRL_PIN(184, "K5 AGND"),
1201 	PINCTRL_PIN(185, "K6 V1"),
1202 	PINCTRL_PIN(186, "K7 V1"),
1203 	PINCTRL_PIN(187, "K8 GND"),
1204 	PINCTRL_PIN(188, "K9 GND"),
1205 	PINCTRL_PIN(189, "K10 GND"),
1206 	PINCTRL_PIN(190, "K11 GND"),
1207 	PINCTRL_PIN(191, "K12 GND"),
1208 	PINCTRL_PIN(192, "K13 GND"),
1209 	PINCTRL_PIN(193, "K14 V1"),
1210 	PINCTRL_PIN(194, "K15 V1"),
1211 	PINCTRL_PIN(195, "K16 PCI TRDY N"),
1212 	PINCTRL_PIN(196, "K17 PCI IRDY N"),
1213 	PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
1214 	PINCTRL_PIN(198, "K19 PCI STOP N"),
1215 	PINCTRL_PIN(199, "K20 PCI PAR"),
1216 	/* Row L */
1217 	PINCTRL_PIN(200, "L1 IDE CS0 N"),
1218 	PINCTRL_PIN(201, "L2 IDE DA0"),
1219 	PINCTRL_PIN(202, "L3 AVCCK 3"),
1220 	PINCTRL_PIN(203, "L4 AGND"),
1221 	PINCTRL_PIN(204, "L5 IDE DIOR N"),
1222 	PINCTRL_PIN(205, "L6 V1"),
1223 	PINCTRL_PIN(206, "L7 V1"),
1224 	PINCTRL_PIN(207, "L8 GND"),
1225 	PINCTRL_PIN(208, "L9 GND"),
1226 	PINCTRL_PIN(209, "L10 GND"),
1227 	PINCTRL_PIN(210, "L11 GND"),
1228 	PINCTRL_PIN(211, "L12 GND"),
1229 	PINCTRL_PIN(212, "L13 GND"),
1230 	PINCTRL_PIN(213, "L14 V1"),
1231 	PINCTRL_PIN(214, "L15 V1"),
1232 	PINCTRL_PIN(215, "L16 PCI AD12"),
1233 	PINCTRL_PIN(216, "L17 PCI AD13"),
1234 	PINCTRL_PIN(217, "L18 PCI AD14"),
1235 	PINCTRL_PIN(218, "L19 PCI AD15"),
1236 	PINCTRL_PIN(219, "L20 PCI CBE1 N"),
1237 	/* Row M */
1238 	PINCTRL_PIN(220, "M1 IDE DA1"),
1239 	PINCTRL_PIN(221, "M2 IDE CS1 N"),
1240 	PINCTRL_PIN(222, "M3 IDE DA2"),
1241 	PINCTRL_PIN(223, "M4 IDE DMACK N"),
1242 	PINCTRL_PIN(224, "M5 IDE DD1"),
1243 	PINCTRL_PIN(225, "M6 VCC3IOHA"),
1244 	PINCTRL_PIN(226, "M7 V1"),
1245 	PINCTRL_PIN(227, "M8 GND"),
1246 	PINCTRL_PIN(228, "M9 GND"),
1247 	PINCTRL_PIN(229, "M10 GND"),
1248 	PINCTRL_PIN(230, "M11 GND"),
1249 	PINCTRL_PIN(231, "M12 GND"),
1250 	PINCTRL_PIN(232, "M13 GND"),
1251 	PINCTRL_PIN(233, "M14 V1"),
1252 	PINCTRL_PIN(234, "M15 VCC3IOHA"),
1253 	PINCTRL_PIN(235, "M16 PCI AD7"),
1254 	PINCTRL_PIN(236, "M17 PCI AD6"),
1255 	PINCTRL_PIN(237, "M18 PCI AD9"),
1256 	PINCTRL_PIN(238, "M19 PCI AD10"),
1257 	PINCTRL_PIN(239, "M20 PCI AD11"),
1258 	/* Row N */
1259 	PINCTRL_PIN(240, "N1 IDE IORDY"),
1260 	PINCTRL_PIN(241, "N2 IDE INTRQ"),
1261 	PINCTRL_PIN(242, "N3 IDE DIOW N"),
1262 	PINCTRL_PIN(243, "N4 IDE DD15"),
1263 	PINCTRL_PIN(244, "N5 IDE DMARQ"),
1264 	PINCTRL_PIN(245, "N6 VCC3IOHA"),
1265 	PINCTRL_PIN(246, "N7 VCC3IOHA"),
1266 	PINCTRL_PIN(247, "N8 GND"),
1267 	PINCTRL_PIN(248, "N9 GND"),
1268 	PINCTRL_PIN(249, "N10 GND"),
1269 	PINCTRL_PIN(250, "N11 GND"),
1270 	PINCTRL_PIN(251, "N12 GND"),
1271 	PINCTRL_PIN(252, "N13 GND"),
1272 	PINCTRL_PIN(253, "N14 VCC3IOHA"),
1273 	PINCTRL_PIN(254, "N15 VCC3IOHA"),
1274 	PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
1275 	PINCTRL_PIN(256, "N17 PCI AD0"),
1276 	PINCTRL_PIN(257, "N18 PCI AD4"),
1277 	PINCTRL_PIN(258, "N19 PCI CBE0 N"),
1278 	PINCTRL_PIN(259, "N20 PCI AD8"),
1279 	/* Row P (for some reason O is skipped) */
1280 	PINCTRL_PIN(260, "P1 IDE DD0"),
1281 	PINCTRL_PIN(261, "P2 IDE DD14"),
1282 	PINCTRL_PIN(262, "P3 IDE DD2"),
1283 	PINCTRL_PIN(263, "P4 IDE DD4"),
1284 	PINCTRL_PIN(264, "P5 IDE DD3"),
1285 	PINCTRL_PIN(265, "P6 VCC3IOHA"),
1286 	PINCTRL_PIN(266, "P7 GND"),
1287 	PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
1288 	PINCTRL_PIN(268, "P9 V1"),
1289 	PINCTRL_PIN(269, "P10 V1"),
1290 	PINCTRL_PIN(270, "P11 V1"),
1291 	PINCTRL_PIN(271, "P12 V1"),
1292 	PINCTRL_PIN(272, "P13 VCC3IOHA"),
1293 	PINCTRL_PIN(273, "P14 GND"),
1294 	PINCTRL_PIN(274, "P15 VCC3IOHA"),
1295 	PINCTRL_PIN(275, "P16 GPIO0 30"),
1296 	PINCTRL_PIN(276, "P17 GPIO0 28"),
1297 	PINCTRL_PIN(277, "P18 PCI AD1"),
1298 	PINCTRL_PIN(278, "P19 PCI AD3"),
1299 	PINCTRL_PIN(279, "P20 PCI AD5"),
1300 	/* Row R (for some reason Q us skipped) */
1301 	PINCTRL_PIN(280, "R1 IDE DD13"),
1302 	PINCTRL_PIN(281, "R2 IDE DD12"),
1303 	PINCTRL_PIN(282, "R3 IDE DD10"),
1304 	PINCTRL_PIN(283, "R4 IDE DD6"),
1305 	PINCTRL_PIN(284, "R5 ICE0 IDI"),
1306 	PINCTRL_PIN(285, "R6 GND"),
1307 	PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
1308 	PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
1309 	PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
1310 	PINCTRL_PIN(289, "R10 V1"),
1311 	PINCTRL_PIN(290, "R11 V1"),
1312 	PINCTRL_PIN(291, "R12 VCC3IOHA"),
1313 	PINCTRL_PIN(292, "R13 VCC3IOHA"),
1314 	PINCTRL_PIN(293, "R14 VCC3IOHA"),
1315 	PINCTRL_PIN(294, "R15 GND"),
1316 	PINCTRL_PIN(295, "R16 GPIO0 23"),
1317 	PINCTRL_PIN(296, "R17 GPIO0 21"),
1318 	PINCTRL_PIN(297, "R18 GPIO0 26"),
1319 	PINCTRL_PIN(298, "R19 GPIO0 31"),
1320 	PINCTRL_PIN(299, "R20 PCI AD2"),
1321 	/* Row T (for some reason S is skipped) */
1322 	PINCTRL_PIN(300, "T1 IDE DD11"),
1323 	PINCTRL_PIN(301, "T2 IDE DD5"),
1324 	PINCTRL_PIN(302, "T3 IDE DD8"),
1325 	PINCTRL_PIN(303, "T4 ICE0 IDO"),
1326 	PINCTRL_PIN(304, "T5 GND"),
1327 	PINCTRL_PIN(305, "T6 USB GNDA U20"),
1328 	PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
1329 	PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
1330 	PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
1331 	PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
1332 	PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
1333 	PINCTRL_PIN(311, "T12 GPIO1 29"),
1334 	PINCTRL_PIN(312, "T13 GPIO0 3"),
1335 	PINCTRL_PIN(313, "T14 GPIO0 9"),
1336 	PINCTRL_PIN(314, "T15 GPIO0 16"),
1337 	PINCTRL_PIN(315, "T16 GND"),
1338 	PINCTRL_PIN(316, "T17 GPIO0 14"),
1339 	PINCTRL_PIN(317, "T18 GPIO0 19"),
1340 	PINCTRL_PIN(318, "T19 GPIO0 27"),
1341 	PINCTRL_PIN(319, "T20 GPIO0 29"),
1342 	/* Row U */
1343 	PINCTRL_PIN(320, "U1 IDE DD9"),
1344 	PINCTRL_PIN(321, "U2 IDE DD7"),
1345 	PINCTRL_PIN(322, "U3 ICE0 ICK"),
1346 	PINCTRL_PIN(323, "U4 GND"),
1347 	PINCTRL_PIN(324, "U5 USB XSCO"),
1348 	PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
1349 	PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
1350 	PINCTRL_PIN(327, "U8 GMAC0 TXC"),
1351 	PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
1352 	PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
1353 	PINCTRL_PIN(330, "U11 GMAC1 CRS"),
1354 	PINCTRL_PIN(331, "U12 EXT CLK"),
1355 	PINCTRL_PIN(332, "U13 DEV DEF"),
1356 	PINCTRL_PIN(333, "U14 GPIO0 0"),
1357 	PINCTRL_PIN(334, "U15 GPIO0 4"),
1358 	PINCTRL_PIN(335, "U16 GPIO0 10"),
1359 	PINCTRL_PIN(336, "U17 GND"),
1360 	PINCTRL_PIN(337, "U18 GPIO0 17"),
1361 	PINCTRL_PIN(338, "U19 GPIO0 22"),
1362 	PINCTRL_PIN(339, "U20 GPIO0 25"),
1363 	/* Row V */
1364 	PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
1365 	PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
1366 	PINCTRL_PIN(342, "V3 GND"),
1367 	PINCTRL_PIN(343, "V4 ICE0 IRST N"),
1368 	PINCTRL_PIN(344, "V5 USB XSCI"),
1369 	PINCTRL_PIN(345, "V6 GMAC0 COL"),
1370 	PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
1371 	PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
1372 	PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
1373 	PINCTRL_PIN(349, "V10 GMAC1 COL"),
1374 	PINCTRL_PIN(350, "V11 GMAC1 TXC"),
1375 	PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
1376 	PINCTRL_PIN(352, "V13 MODE SEL1"),
1377 	PINCTRL_PIN(353, "V14 GPIO1 28"),
1378 	PINCTRL_PIN(354, "V15 GPIO0 1"),
1379 	PINCTRL_PIN(355, "V16 GPIO0 8"),
1380 	PINCTRL_PIN(356, "V17 GPIO0 11"),
1381 	PINCTRL_PIN(357, "V18 GND"),
1382 	PINCTRL_PIN(358, "V19 GPIO0 18"),
1383 	PINCTRL_PIN(359, "V20 GPIO0 24"),
1384 	/* Row W */
1385 	PINCTRL_PIN(360, "W1 IDE RESET N"),
1386 	PINCTRL_PIN(361, "W2 GND"),
1387 	PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
1388 	PINCTRL_PIN(363, "W4 USB0 DP"),
1389 	PINCTRL_PIN(364, "W5 USB VCCA U20"),
1390 	PINCTRL_PIN(365, "W6 USB1 DP"),
1391 	PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
1392 	PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
1393 	PINCTRL_PIN(368, "W9 GMAC0 CRS"),
1394 	PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
1395 	PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
1396 	PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
1397 	PINCTRL_PIN(372, "W13 MODE SEL0"),
1398 	PINCTRL_PIN(373, "W14 MODE SEL3"),
1399 	PINCTRL_PIN(374, "W15 GPIO1 31"),
1400 	PINCTRL_PIN(375, "W16 GPIO0 5"),
1401 	PINCTRL_PIN(376, "W17 GPIO0 7"),
1402 	PINCTRL_PIN(377, "W18 GPIO0 12"),
1403 	PINCTRL_PIN(378, "W19 GND"),
1404 	PINCTRL_PIN(379, "W20 GPIO0 20"),
1405 	/* Row Y */
1406 	PINCTRL_PIN(380, "Y1 ICE0 IMS"),
1407 	PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
1408 	PINCTRL_PIN(382, "Y3 USB0 DM"),
1409 	PINCTRL_PIN(383, "Y4 USB RREF"),
1410 	PINCTRL_PIN(384, "Y5 USB1 DM"),
1411 	PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
1412 	PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
1413 	PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
1414 	PINCTRL_PIN(388, "Y9 REF CLK"),
1415 	PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
1416 	PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
1417 	PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
1418 	PINCTRL_PIN(392, "Y13 M30 CLK"),
1419 	PINCTRL_PIN(393, "Y14 MODE SEL2"),
1420 	PINCTRL_PIN(394, "Y15 GPIO1 30"),
1421 	PINCTRL_PIN(395, "Y16 GPIO0 2"),
1422 	PINCTRL_PIN(396, "Y17 GPIO0 6"),
1423 	PINCTRL_PIN(397, "Y18 SYS RESET N"),
1424 	PINCTRL_PIN(398, "Y19 GPIO0 13"),
1425 	PINCTRL_PIN(399, "Y20 GPIO0 15"),
1426 };
1427 
1428 /* Digital ground */
1429 static const unsigned int gnd_3516_pins[] = {
1430 	21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
1431 	151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
1432 	207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
1433 	249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
1434 	361, 378
1435 };
1436 
1437 static const unsigned int dram_3516_pins[] = {
1438 	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
1439 	27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
1440 	51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
1441 	87, 88, 89, 90, 91, 92, 93, 94
1442 };
1443 
1444 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
1445 
1446 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
1447 
1448 static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
1449 
1450 static const unsigned int system_3516_pins[] = {
1451 	332, 392, 372, 373, 393, 352, 331, 388, 397, 77
1452 };
1453 
1454 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
1455 
1456 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
1457 
1458 static const unsigned int ide_3516_pins[] = {
1459 	200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
1460 	261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
1461 };
1462 
1463 static const unsigned int sata_3516_pins[] = {
1464 	100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
1465 	144, 160, 161, 162, 163, 180, 181, 182, 183, 202
1466 };
1467 
1468 static const unsigned int usb_3516_pins[] = {
1469 	305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
1470 };
1471 
1472 /* GMII, ethernet pins */
1473 static const unsigned int gmii_gmac0_3516_pins[] = {
1474 	306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
1475 };
1476 
1477 static const unsigned int gmii_gmac1_3516_pins[] = {
1478 	308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
1479 };
1480 
1481 static const unsigned int pci_3516_pins[] = {
1482 	17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
1483 	119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
1484 	178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
1485 	237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
1486 };
1487 
1488 /*
1489  * Apparently the LPC interface is using the PCICLK for the clocking so
1490  * PCI needs to be active at the same time.
1491  */
1492 static const unsigned int lpc_3516_pins[] = {
1493 	355, /* LPC_LAD[0] */
1494 	356, /* LPC_SERIRQ */
1495 	377, /* LPC_LAD[2] */
1496 	398, /* LPC_LFRAME# */
1497 	316, /* LPC_LAD[3] */
1498 	399, /* LPC_LAD[1] */
1499 };
1500 
1501 /* Character LCD */
1502 static const unsigned int lcd_3516_pins[] = {
1503 	391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
1504 };
1505 
1506 static const unsigned int ssp_3516_pins[] = {
1507 	355, /* SSP_97RST# SSP AC97 Reset, active low */
1508 	356, /* SSP_FSC */
1509 	377, /* SSP_ECLK */
1510 	398, /* SSP_TXD */
1511 	316, /* SSP_RXD */
1512 	399, /* SSP_SCLK */
1513 };
1514 
1515 static const unsigned int uart_rxtx_3516_pins[] = {
1516 	313, /* UART_SIN serial input, RX */
1517 	335, /* UART_SOUT serial output, TX */
1518 };
1519 
1520 static const unsigned int uart_modem_3516_pins[] = {
1521 	355, /* UART_NDCD DCD carrier detect */
1522 	356, /* UART_NDTR DTR data terminal ready */
1523 	377, /* UART_NDSR DSR data set ready */
1524 	398, /* UART_NRTS RTS request to send */
1525 	316, /* UART_NCTS CTS clear to send */
1526 	399, /* UART_NRI RI ring indicator */
1527 };
1528 
1529 static const unsigned int tvc_3516_pins[] = {
1530 	353, /* TVC_DATA[0] */
1531 	311, /* TVC_DATA[1] */
1532 	394, /* TVC_DATA[2] */
1533 	374, /* TVC_DATA[3] */
1534 	333, /* TVC_CLK */
1535 	354, /* TVC_DATA[4] */
1536 	395, /* TVC_DATA[5] */
1537 	312, /* TVC_DATA[6] */
1538 	334, /* TVC_DATA[7] */
1539 };
1540 
1541 /* NAND flash pins */
1542 static const unsigned int nflash_3516_pins[] = {
1543 	243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1544 	302, 321, 337, 358, 295, 359, 339, 275, 298
1545 };
1546 
1547 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1548 static const unsigned int pflash_3516_pins[] = {
1549 	221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1550 	263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1551 	276, 319, 275, 298
1552 };
1553 
1554 /*
1555  * The parallel flash can be set up in a 26-bit address bus mode exposing
1556  * A[0-15] (A[15] takes the place of ALE), but it has the
1557  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1558  * used at the same time.
1559  */
1560 static const unsigned int pflash_3516_pins_extended[] = {
1561 	221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1562 	263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1563 	276, 319, 275, 298,
1564 	/* The extra pins */
1565 	349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
1566 	333
1567 };
1568 
1569 /* Serial flash pins CE0, CE1, DI, DO, CK */
1570 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
1571 
1572 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1573 static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 };
1574 
1575 /* The GPIO0B (5-7) pins overlap with ICE */
1576 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
1577 
1578 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1579 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
1580 
1581 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1582 static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
1583 
1584 /* The GPIO0E (16) pins overlap with LCD */
1585 static const unsigned int gpio0e_3516_pins[] = { 314 };
1586 
1587 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1588 static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
1589 
1590 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1591 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
1592 
1593 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1594 static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
1595 
1596 /* The GPIO0I (23) pins overlap with all flash */
1597 static const unsigned int gpio0i_3516_pins[] = { 295 };
1598 
1599 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1600 static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
1601 
1602 /* The GPIO0K (30,31) pins overlap with NAND flash */
1603 static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
1604 
1605 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1606 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
1607 
1608 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1609 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
1610 
1611 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1612 static const unsigned int gpio1c_3516_pins[] = {
1613 	243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1614 	302, 321
1615 };
1616 
1617 /* The GPIO1D (28-31) pins overlap with TVC */
1618 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1619 
1620 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1621 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1622 
1623 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1624 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1625 
1626 /* The GPIO2C (8-31) pins overlap with PCI */
1627 static const unsigned int gpio2c_3516_pins[] = {
1628 	259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
1629 	157, 138, 137, 156, 118, 155, 99, 98, 136, 117
1630 };
1631 
1632 /* Groups for the 3516 SoC/package */
1633 static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1634 	{
1635 		.name = "gndgrp",
1636 		.pins = gnd_3516_pins,
1637 		.num_pins = ARRAY_SIZE(gnd_3516_pins),
1638 	},
1639 	{
1640 		.name = "dramgrp",
1641 		.pins = dram_3516_pins,
1642 		.num_pins = ARRAY_SIZE(dram_3516_pins),
1643 		.mask = DRAM_PADS_POWERDOWN,
1644 	},
1645 	{
1646 		.name = "rtcgrp",
1647 		.pins = rtc_3516_pins,
1648 		.num_pins = ARRAY_SIZE(rtc_3516_pins),
1649 	},
1650 	{
1651 		.name = "powergrp",
1652 		.pins = power_3516_pins,
1653 		.num_pins = ARRAY_SIZE(power_3516_pins),
1654 	},
1655 	{
1656 		.name = "cirgrp",
1657 		.pins = cir_3516_pins,
1658 		.num_pins = ARRAY_SIZE(cir_3516_pins),
1659 	},
1660 	{
1661 		.name = "systemgrp",
1662 		.pins = system_3516_pins,
1663 		.num_pins = ARRAY_SIZE(system_3516_pins),
1664 	},
1665 	{
1666 		.name = "vcontrolgrp",
1667 		.pins = vcontrol_3516_pins,
1668 		.num_pins = ARRAY_SIZE(vcontrol_3516_pins),
1669 	},
1670 	{
1671 		.name = "icegrp",
1672 		.pins = ice_3516_pins,
1673 		.num_pins = ARRAY_SIZE(ice_3516_pins),
1674 		/* Conflict with some GPIO groups */
1675 	},
1676 	{
1677 		.name = "idegrp",
1678 		.pins = ide_3516_pins,
1679 		.num_pins = ARRAY_SIZE(ide_3516_pins),
1680 		/* Conflict with all flash usage */
1681 		.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1682 			PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1683 		.driving_mask = GENMASK(21, 20),
1684 	},
1685 	{
1686 		.name = "satagrp",
1687 		.pins = sata_3516_pins,
1688 		.num_pins = ARRAY_SIZE(sata_3516_pins),
1689 	},
1690 	{
1691 		.name = "usbgrp",
1692 		.pins = usb_3516_pins,
1693 		.num_pins = ARRAY_SIZE(usb_3516_pins),
1694 	},
1695 	{
1696 		.name = "gmii_gmac0_grp",
1697 		.pins = gmii_gmac0_3516_pins,
1698 		.num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1699 		.mask = GEMINI_GMAC_IOSEL_MASK,
1700 		.driving_mask = GENMASK(17, 16),
1701 	},
1702 	{
1703 		.name = "gmii_gmac1_grp",
1704 		.pins = gmii_gmac1_3516_pins,
1705 		.num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1706 		/* Bring out RGMII on the GMAC1 pins */
1707 		.mask = GEMINI_GMAC_IOSEL_MASK,
1708 		.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1709 		.driving_mask = GENMASK(19, 18),
1710 	},
1711 	{
1712 		.name = "pcigrp",
1713 		.pins = pci_3516_pins,
1714 		.num_pins = ARRAY_SIZE(pci_3516_pins),
1715 		/* Conflict only with GPIO2 */
1716 		.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1717 		.driving_mask = GENMASK(23, 22),
1718 	},
1719 	{
1720 		.name = "lpcgrp",
1721 		.pins = lpc_3516_pins,
1722 		.num_pins = ARRAY_SIZE(lpc_3516_pins),
1723 		/* Conflict with SSP */
1724 		.mask = SSP_PADS_ENABLE,
1725 		.value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
1726 	},
1727 	{
1728 		.name = "lcdgrp",
1729 		.pins = lcd_3516_pins,
1730 		.num_pins = ARRAY_SIZE(lcd_3516_pins),
1731 		.mask = TVC_PADS_ENABLE,
1732 		.value = LCD_PADS_ENABLE,
1733 	},
1734 	{
1735 		.name = "sspgrp",
1736 		.pins = ssp_3516_pins,
1737 		.num_pins = ARRAY_SIZE(ssp_3516_pins),
1738 		/* Conflict with LPC */
1739 		.mask = LPC_PADS_ENABLE,
1740 		.value = SSP_PADS_ENABLE,
1741 	},
1742 	{
1743 		.name = "uartrxtxgrp",
1744 		.pins = uart_rxtx_3516_pins,
1745 		.num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
1746 		/* No conflicts except GPIO */
1747 	},
1748 	{
1749 		.name = "uartmodemgrp",
1750 		.pins = uart_modem_3516_pins,
1751 		.num_pins = ARRAY_SIZE(uart_modem_3516_pins),
1752 		/*
1753 		 * Conflict with LPC and SSP,
1754 		 * so when those are both disabled, modem UART can thrive.
1755 		 */
1756 		.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1757 	},
1758 	{
1759 		.name = "tvcgrp",
1760 		.pins = tvc_3516_pins,
1761 		.num_pins = ARRAY_SIZE(tvc_3516_pins),
1762 		/* Conflict with character LCD */
1763 		.mask = LCD_PADS_ENABLE,
1764 		.value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
1765 	},
1766 	/*
1767 	 * The construction is done such that it is possible to use a serial
1768 	 * flash together with a NAND or parallel (NOR) flash, but it is not
1769 	 * possible to use NAND and parallel flash together. To use serial
1770 	 * flash with one of the two others, the muxbits need to be flipped
1771 	 * around before any access.
1772 	 */
1773 	{
1774 		.name = "nflashgrp",
1775 		.pins = nflash_3516_pins,
1776 		.num_pins = ARRAY_SIZE(nflash_3516_pins),
1777 		/* Conflict with IDE, parallel and serial flash */
1778 		.mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
1779 		.value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1780 	},
1781 	{
1782 		.name = "pflashgrp",
1783 		.pins = pflash_3516_pins,
1784 		.num_pins = ARRAY_SIZE(pflash_3516_pins),
1785 		/* Conflict with IDE, NAND and serial flash */
1786 		.mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1787 		.value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
1788 	},
1789 	{
1790 		.name = "sflashgrp",
1791 		.pins = sflash_3516_pins,
1792 		.num_pins = ARRAY_SIZE(sflash_3516_pins),
1793 		/* Conflict with IDE, NAND and parallel flash */
1794 		.mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1795 		.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1796 	},
1797 	{
1798 		.name = "gpio0agrp",
1799 		.pins = gpio0a_3516_pins,
1800 		.num_pins = ARRAY_SIZE(gpio0a_3516_pins),
1801 		/* Conflict with TVC and ICE */
1802 		.mask = TVC_PADS_ENABLE,
1803 	},
1804 	{
1805 		.name = "gpio0bgrp",
1806 		.pins = gpio0b_3516_pins,
1807 		.num_pins = ARRAY_SIZE(gpio0b_3516_pins),
1808 		/* Conflict with ICE */
1809 	},
1810 	{
1811 		.name = "gpio0cgrp",
1812 		.pins = gpio0c_3516_pins,
1813 		.num_pins = ARRAY_SIZE(gpio0c_3516_pins),
1814 		/* Conflict with LPC, UART and SSP */
1815 		.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1816 	},
1817 	{
1818 		.name = "gpio0dgrp",
1819 		.pins = gpio0d_3516_pins,
1820 		.num_pins = ARRAY_SIZE(gpio0d_3516_pins),
1821 		/* Conflict with UART */
1822 	},
1823 	{
1824 		.name = "gpio0egrp",
1825 		.pins = gpio0e_3516_pins,
1826 		.num_pins = ARRAY_SIZE(gpio0e_3516_pins),
1827 		/* Conflict with LCD */
1828 		.mask = LCD_PADS_ENABLE,
1829 	},
1830 	{
1831 		.name = "gpio0fgrp",
1832 		.pins = gpio0f_3516_pins,
1833 		.num_pins = ARRAY_SIZE(gpio0f_3516_pins),
1834 		/* Conflict with NAND flash */
1835 		.value = NAND_PADS_DISABLE,
1836 	},
1837 	{
1838 		.name = "gpio0ggrp",
1839 		.pins = gpio0g_3516_pins,
1840 		.num_pins = ARRAY_SIZE(gpio0g_3516_pins),
1841 		/* Conflict with parallel flash */
1842 		.value = PFLASH_PADS_DISABLE,
1843 	},
1844 	{
1845 		.name = "gpio0hgrp",
1846 		.pins = gpio0h_3516_pins,
1847 		.num_pins = ARRAY_SIZE(gpio0h_3516_pins),
1848 		/* Conflict with serial flash */
1849 		.value = SFLASH_PADS_DISABLE,
1850 	},
1851 	{
1852 		.name = "gpio0igrp",
1853 		.pins = gpio0i_3516_pins,
1854 		.num_pins = ARRAY_SIZE(gpio0i_3516_pins),
1855 		/* Conflict with all flash */
1856 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1857 			SFLASH_PADS_DISABLE,
1858 	},
1859 	{
1860 		.name = "gpio0jgrp",
1861 		.pins = gpio0j_3516_pins,
1862 		.num_pins = ARRAY_SIZE(gpio0j_3516_pins),
1863 		/* Conflict with all flash and LCD */
1864 		.mask = LCD_PADS_ENABLE,
1865 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1866 			SFLASH_PADS_DISABLE,
1867 	},
1868 	{
1869 		.name = "gpio0kgrp",
1870 		.pins = gpio0k_3516_pins,
1871 		.num_pins = ARRAY_SIZE(gpio0k_3516_pins),
1872 		/* Conflict with parallel and NAND flash */
1873 		.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
1874 	},
1875 	{
1876 		.name = "gpio1agrp",
1877 		.pins = gpio1a_3516_pins,
1878 		.num_pins = ARRAY_SIZE(gpio1a_3516_pins),
1879 		/* Conflict with IDE and parallel flash */
1880 		.mask = IDE_PADS_ENABLE,
1881 		.value = PFLASH_PADS_DISABLE,
1882 	},
1883 	{
1884 		.name = "gpio1bgrp",
1885 		.pins = gpio1b_3516_pins,
1886 		.num_pins = ARRAY_SIZE(gpio1b_3516_pins),
1887 		/* Conflict with IDE only */
1888 		.mask = IDE_PADS_ENABLE,
1889 	},
1890 	{
1891 		.name = "gpio1cgrp",
1892 		.pins = gpio1c_3516_pins,
1893 		.num_pins = ARRAY_SIZE(gpio1c_3516_pins),
1894 		/* Conflict with IDE, parallel and NAND flash */
1895 		.mask = IDE_PADS_ENABLE,
1896 		.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1897 	},
1898 	{
1899 		.name = "gpio1dgrp",
1900 		.pins = gpio1d_3516_pins,
1901 		.num_pins = ARRAY_SIZE(gpio1d_3516_pins),
1902 		/* Conflict with TVC */
1903 		.mask = TVC_PADS_ENABLE,
1904 	},
1905 	{
1906 		.name = "gpio2agrp",
1907 		.pins = gpio2a_3516_pins,
1908 		.num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1909 		.mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1910 		/* Conflict with GMII GMAC1 and extended parallel flash */
1911 	},
1912 	{
1913 		.name = "gpio2bgrp",
1914 		.pins = gpio2b_3516_pins,
1915 		.num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1916 		/* Conflict with GMII GMAC1, extended parallel flash and LCD */
1917 		.mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1918 	},
1919 	{
1920 		.name = "gpio2cgrp",
1921 		.pins = gpio2c_3516_pins,
1922 		.num_pins = ARRAY_SIZE(gpio2c_3516_pins),
1923 		/* Conflict with PCI */
1924 		.mask = PCI_PADS_ENABLE,
1925 	},
1926 };
1927 
gemini_get_groups_count(struct pinctrl_dev * pctldev)1928 static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
1929 {
1930 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1931 
1932 	if (pmx->is_3512)
1933 		return ARRAY_SIZE(gemini_3512_pin_groups);
1934 	if (pmx->is_3516)
1935 		return ARRAY_SIZE(gemini_3516_pin_groups);
1936 	return 0;
1937 }
1938 
gemini_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)1939 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
1940 					 unsigned int selector)
1941 {
1942 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1943 
1944 	if (pmx->is_3512)
1945 		return gemini_3512_pin_groups[selector].name;
1946 	if (pmx->is_3516)
1947 		return gemini_3516_pin_groups[selector].name;
1948 	return NULL;
1949 }
1950 
gemini_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)1951 static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
1952 				 unsigned int selector,
1953 				 const unsigned int **pins,
1954 				 unsigned int *num_pins)
1955 {
1956 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1957 
1958 	/* The special case with the 3516 flash pin */
1959 	if (pmx->flash_pin &&
1960 	    pmx->is_3512 &&
1961 	    !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
1962 		*pins = pflash_3512_pins_extended;
1963 		*num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
1964 		return 0;
1965 	}
1966 	if (pmx->flash_pin &&
1967 	    pmx->is_3516 &&
1968 	    !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
1969 		*pins = pflash_3516_pins_extended;
1970 		*num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
1971 		return 0;
1972 	}
1973 	if (pmx->is_3512) {
1974 		*pins = gemini_3512_pin_groups[selector].pins;
1975 		*num_pins = gemini_3512_pin_groups[selector].num_pins;
1976 	}
1977 	if (pmx->is_3516) {
1978 		*pins = gemini_3516_pin_groups[selector].pins;
1979 		*num_pins = gemini_3516_pin_groups[selector].num_pins;
1980 	}
1981 	return 0;
1982 }
1983 
gemini_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)1984 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1985 				unsigned int offset)
1986 {
1987 	seq_printf(s, " " DRIVER_NAME);
1988 }
1989 
1990 static const struct pinctrl_ops gemini_pctrl_ops = {
1991 	.get_groups_count = gemini_get_groups_count,
1992 	.get_group_name = gemini_get_group_name,
1993 	.get_group_pins = gemini_get_group_pins,
1994 	.pin_dbg_show = gemini_pin_dbg_show,
1995 	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1996 	.dt_free_map = pinconf_generic_dt_free_map,
1997 };
1998 
1999 /**
2000  * struct gemini_pmx_func - describes Gemini pinmux functions
2001  * @name: the name of this specific function
2002  * @groups: corresponding pin groups
2003  */
2004 struct gemini_pmx_func {
2005 	const char *name;
2006 	const char * const *groups;
2007 	const unsigned int num_groups;
2008 };
2009 
2010 static const char * const dramgrps[] = { "dramgrp" };
2011 static const char * const rtcgrps[] = { "rtcgrp" };
2012 static const char * const powergrps[] = { "powergrp" };
2013 static const char * const cirgrps[] = { "cirgrp" };
2014 static const char * const systemgrps[] = { "systemgrp" };
2015 static const char * const vcontrolgrps[] = { "vcontrolgrp" };
2016 static const char * const icegrps[] = { "icegrp" };
2017 static const char * const idegrps[] = { "idegrp" };
2018 static const char * const satagrps[] = { "satagrp" };
2019 static const char * const usbgrps[] = { "usbgrp" };
2020 static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
2021 static const char * const pcigrps[] = { "pcigrp" };
2022 static const char * const lpcgrps[] = { "lpcgrp" };
2023 static const char * const lcdgrps[] = { "lcdgrp" };
2024 static const char * const sspgrps[] = { "sspgrp" };
2025 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
2026 static const char * const tvcgrps[] = { "tvcgrp" };
2027 static const char * const nflashgrps[] = { "nflashgrp" };
2028 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
2029 static const char * const sflashgrps[] = { "sflashgrp" };
2030 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2031 					  "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2032 					  "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
2033 					  "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
2034 					  "gpio0mgrp" };
2035 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2036 					  "gpio1dgrp" };
2037 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
2038 
2039 static const struct gemini_pmx_func gemini_pmx_functions[] = {
2040 	{
2041 		.name = "dram",
2042 		.groups = dramgrps,
2043 		.num_groups = ARRAY_SIZE(idegrps),
2044 	},
2045 	{
2046 		.name = "rtc",
2047 		.groups = rtcgrps,
2048 		.num_groups = ARRAY_SIZE(rtcgrps),
2049 	},
2050 	{
2051 		.name = "power",
2052 		.groups = powergrps,
2053 		.num_groups = ARRAY_SIZE(powergrps),
2054 	},
2055 	{
2056 		/* This function is strictly unavailable on 3512 */
2057 		.name = "cir",
2058 		.groups = cirgrps,
2059 		.num_groups = ARRAY_SIZE(cirgrps),
2060 	},
2061 	{
2062 		.name = "system",
2063 		.groups = systemgrps,
2064 		.num_groups = ARRAY_SIZE(systemgrps),
2065 	},
2066 	{
2067 		.name = "vcontrol",
2068 		.groups = vcontrolgrps,
2069 		.num_groups = ARRAY_SIZE(vcontrolgrps),
2070 	},
2071 	{
2072 		.name = "ice",
2073 		.groups = icegrps,
2074 		.num_groups = ARRAY_SIZE(icegrps),
2075 	},
2076 	{
2077 		.name = "ide",
2078 		.groups = idegrps,
2079 		.num_groups = ARRAY_SIZE(idegrps),
2080 	},
2081 	{
2082 		.name = "sata",
2083 		.groups = satagrps,
2084 		.num_groups = ARRAY_SIZE(satagrps),
2085 	},
2086 	{
2087 		.name = "usb",
2088 		.groups = usbgrps,
2089 		.num_groups = ARRAY_SIZE(usbgrps),
2090 	},
2091 	{
2092 		.name = "gmii",
2093 		.groups = gmiigrps,
2094 		.num_groups = ARRAY_SIZE(gmiigrps),
2095 	},
2096 	{
2097 		.name = "pci",
2098 		.groups = pcigrps,
2099 		.num_groups = ARRAY_SIZE(pcigrps),
2100 	},
2101 	{
2102 		.name = "lpc",
2103 		.groups = lpcgrps,
2104 		.num_groups = ARRAY_SIZE(lpcgrps),
2105 	},
2106 	{
2107 		.name = "lcd",
2108 		.groups = lcdgrps,
2109 		.num_groups = ARRAY_SIZE(lcdgrps),
2110 	},
2111 	{
2112 		.name = "ssp",
2113 		.groups = sspgrps,
2114 		.num_groups = ARRAY_SIZE(sspgrps),
2115 	},
2116 	{
2117 		.name = "uart",
2118 		.groups = uartgrps,
2119 		.num_groups = ARRAY_SIZE(uartgrps),
2120 	},
2121 	{
2122 		.name = "tvc",
2123 		.groups = tvcgrps,
2124 		.num_groups = ARRAY_SIZE(tvcgrps),
2125 	},
2126 	{
2127 		.name = "nflash",
2128 		.groups = nflashgrps,
2129 		.num_groups = ARRAY_SIZE(nflashgrps),
2130 	},
2131 	{
2132 		.name = "pflash",
2133 		.groups = pflashgrps,
2134 		.num_groups = ARRAY_SIZE(pflashgrps),
2135 	},
2136 	{
2137 		.name = "sflash",
2138 		.groups = sflashgrps,
2139 		.num_groups = ARRAY_SIZE(sflashgrps),
2140 	},
2141 	{
2142 		.name = "gpio0",
2143 		.groups = gpio0grps,
2144 		.num_groups = ARRAY_SIZE(gpio0grps),
2145 	},
2146 	{
2147 		.name = "gpio1",
2148 		.groups = gpio1grps,
2149 		.num_groups = ARRAY_SIZE(gpio1grps),
2150 	},
2151 	{
2152 		.name = "gpio2",
2153 		.groups = gpio2grps,
2154 		.num_groups = ARRAY_SIZE(gpio2grps),
2155 	},
2156 };
2157 
2158 
gemini_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)2159 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
2160 			      unsigned int selector,
2161 			      unsigned int group)
2162 {
2163 	struct gemini_pmx *pmx;
2164 	const struct gemini_pmx_func *func;
2165 	const struct gemini_pin_group *grp;
2166 	u32 before, after, expected;
2167 	unsigned long tmp;
2168 	int i;
2169 
2170 	pmx = pinctrl_dev_get_drvdata(pctldev);
2171 
2172 	func = &gemini_pmx_functions[selector];
2173 	if (pmx->is_3512)
2174 		grp = &gemini_3512_pin_groups[group];
2175 	else if (pmx->is_3516)
2176 		grp = &gemini_3516_pin_groups[group];
2177 	else {
2178 		dev_err(pmx->dev, "invalid SoC type\n");
2179 		return -ENODEV;
2180 	}
2181 
2182 	dev_info(pmx->dev,
2183 		 "ACTIVATE function \"%s\" with group \"%s\"\n",
2184 		 func->name, grp->name);
2185 
2186 	regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
2187 	regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, grp->mask,
2188 			   grp->value);
2189 	regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
2190 
2191 	/* Which bits changed */
2192 	before &= PADS_MASK;
2193 	after &= PADS_MASK;
2194 	expected = before &= ~grp->mask;
2195 	expected |= grp->value;
2196 	expected &= PADS_MASK;
2197 
2198 	/* Print changed states */
2199 	tmp = grp->mask;
2200 	for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2201 		bool enabled = !(i > 3);
2202 
2203 		/* Did not go low though it should */
2204 		if (after & BIT(i)) {
2205 			dev_err(pmx->dev,
2206 				"pin group %s could not be %s: "
2207 				"probably a hardware limitation\n",
2208 				gemini_padgroups[i],
2209 				enabled ? "enabled" : "disabled");
2210 			dev_err(pmx->dev,
2211 				"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2212 				before, after, expected);
2213 		} else {
2214 			dev_info(pmx->dev,
2215 				 "padgroup %s %s\n",
2216 				 gemini_padgroups[i],
2217 				 enabled ? "enabled" : "disabled");
2218 		}
2219 	}
2220 
2221 	tmp = grp->value;
2222 	for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2223 		bool enabled = (i > 3);
2224 
2225 		/* Did not go high though it should */
2226 		if (!(after & BIT(i))) {
2227 			dev_err(pmx->dev,
2228 				"pin group %s could not be %s: "
2229 				"probably a hardware limitation\n",
2230 				gemini_padgroups[i],
2231 				enabled ? "enabled" : "disabled");
2232 			dev_err(pmx->dev,
2233 				"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2234 				before, after, expected);
2235 		} else {
2236 			dev_info(pmx->dev,
2237 				 "padgroup %s %s\n",
2238 				 gemini_padgroups[i],
2239 				 enabled ? "enabled" : "disabled");
2240 		}
2241 	}
2242 
2243 	return 0;
2244 }
2245 
gemini_pmx_get_funcs_count(struct pinctrl_dev * pctldev)2246 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2247 {
2248 	return ARRAY_SIZE(gemini_pmx_functions);
2249 }
2250 
gemini_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned int selector)2251 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
2252 					    unsigned int selector)
2253 {
2254 	return gemini_pmx_functions[selector].name;
2255 }
2256 
gemini_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)2257 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
2258 				 unsigned int selector,
2259 				 const char * const **groups,
2260 				 unsigned int * const num_groups)
2261 {
2262 	*groups = gemini_pmx_functions[selector].groups;
2263 	*num_groups = gemini_pmx_functions[selector].num_groups;
2264 	return 0;
2265 }
2266 
2267 static const struct pinmux_ops gemini_pmx_ops = {
2268 	.get_functions_count = gemini_pmx_get_funcs_count,
2269 	.get_function_name = gemini_pmx_get_func_name,
2270 	.get_function_groups = gemini_pmx_get_groups,
2271 	.set_mux = gemini_pmx_set_mux,
2272 };
2273 
2274 #define GEMINI_CFGPIN(_n, _r, _lb, _hb) {	\
2275 	.pin = _n,				\
2276 	.reg = _r,				\
2277 	.mask = GENMASK(_hb, _lb)		\
2278 }
2279 
2280 static const struct gemini_pin_conf gemini_confs_3512[] = {
2281 	GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2282 	GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2283 	GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2284 	GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2285 	GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2286 	GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2287 	GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2288 	GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2289 	GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2290 	GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2291 	GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2292 	GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2293 	GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2294 	GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2295 	GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2296 	GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2297 	GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2298 	GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2299 	GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2300 	GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2301 	GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2302 	GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2303 	GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2304 	GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2305 };
2306 
2307 static const struct gemini_pin_conf gemini_confs_3516[] = {
2308 	GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2309 	GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2310 	GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2311 	GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2312 	GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2313 	GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2314 	GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2315 	GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2316 	GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2317 	GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2318 	GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2319 	GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2320 	GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2321 	GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2322 	GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2323 	GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2324 	GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2325 	GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2326 	GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2327 	GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2328 	GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2329 	GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2330 	GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2331 	GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2332 };
2333 
gemini_get_pin_conf(struct gemini_pmx * pmx,unsigned int pin)2334 static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2335 							 unsigned int pin)
2336 {
2337 	const struct gemini_pin_conf *retconf;
2338 	int i;
2339 
2340 	for (i = 0; i < pmx->nconfs; i++) {
2341 		retconf = &pmx->confs[i];
2342 		if (retconf->pin == pin)
2343 			return retconf;
2344 	}
2345 	return NULL;
2346 }
2347 
gemini_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2348 static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2349 			      unsigned long *config)
2350 {
2351 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2352 	enum pin_config_param param = pinconf_to_config_param(*config);
2353 	const struct gemini_pin_conf *conf;
2354 	u32 val;
2355 
2356 	switch (param) {
2357 	case PIN_CONFIG_SKEW_DELAY:
2358 		conf = gemini_get_pin_conf(pmx, pin);
2359 		if (!conf)
2360 			return -ENOTSUPP;
2361 		regmap_read(pmx->map, conf->reg, &val);
2362 		val &= conf->mask;
2363 		val >>= (ffs(conf->mask) - 1);
2364 		*config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
2365 		break;
2366 	default:
2367 		return -ENOTSUPP;
2368 	}
2369 
2370 	return 0;
2371 }
2372 
gemini_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2373 static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2374 			      unsigned long *configs, unsigned int num_configs)
2375 {
2376 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2377 	const struct gemini_pin_conf *conf;
2378 	enum pin_config_param param;
2379 	u32 arg;
2380 	int ret = 0;
2381 	int i;
2382 
2383 	for (i = 0; i < num_configs; i++) {
2384 		param = pinconf_to_config_param(configs[i]);
2385 		arg = pinconf_to_config_argument(configs[i]);
2386 
2387 		switch (param) {
2388 		case PIN_CONFIG_SKEW_DELAY:
2389 			if (arg > 0xf)
2390 				return -EINVAL;
2391 			conf = gemini_get_pin_conf(pmx, pin);
2392 			if (!conf) {
2393 				dev_err(pmx->dev,
2394 					"invalid pin for skew delay %d\n", pin);
2395 				return -ENOTSUPP;
2396 			}
2397 			arg <<= (ffs(conf->mask) - 1);
2398 			dev_dbg(pmx->dev,
2399 				"set pin %d to skew delay mask %08x, val %08x\n",
2400 				pin, conf->mask, arg);
2401 			regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
2402 			break;
2403 		default:
2404 			dev_err(pmx->dev, "Invalid config param %04x\n", param);
2405 			return -ENOTSUPP;
2406 		}
2407 	}
2408 
2409 	return ret;
2410 }
2411 
gemini_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned long * configs,unsigned num_configs)2412 static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
2413 				    unsigned selector,
2414 				    unsigned long *configs,
2415 				    unsigned num_configs)
2416 {
2417 	struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2418 	const struct gemini_pin_group *grp = NULL;
2419 	enum pin_config_param param;
2420 	u32 arg;
2421 	u32 val;
2422 	int i;
2423 
2424 	if (pmx->is_3512)
2425 		grp = &gemini_3512_pin_groups[selector];
2426 	if (pmx->is_3516)
2427 		grp = &gemini_3516_pin_groups[selector];
2428 
2429 	/* First figure out if this group supports configs */
2430 	if (!grp->driving_mask) {
2431 		dev_err(pmx->dev, "pin config group \"%s\" does "
2432 			"not support drive strength setting\n",
2433 			grp->name);
2434 		return -EINVAL;
2435 	}
2436 
2437 	for (i = 0; i < num_configs; i++) {
2438 		param = pinconf_to_config_param(configs[i]);
2439 		arg = pinconf_to_config_argument(configs[i]);
2440 
2441 		switch (param) {
2442 		case PIN_CONFIG_DRIVE_STRENGTH:
2443 			switch (arg) {
2444 			case 4:
2445 				val = 0;
2446 				break;
2447 			case 8:
2448 				val = 1;
2449 				break;
2450 			case 12:
2451 				val = 2;
2452 				break;
2453 			case 16:
2454 				val = 3;
2455 				break;
2456 			default:
2457 				dev_err(pmx->dev,
2458 					"invalid drive strength %d mA\n",
2459 					arg);
2460 				return -ENOTSUPP;
2461 			}
2462 			val <<= (ffs(grp->driving_mask) - 1);
2463 			regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
2464 					   grp->driving_mask,
2465 					   val);
2466 			dev_info(pmx->dev,
2467 				 "set group %s to %d mA drive strength mask %08x val %08x\n",
2468 				 grp->name, arg, grp->driving_mask, val);
2469 			break;
2470 		default:
2471 			dev_err(pmx->dev, "invalid config param %04x\n", param);
2472 			return -ENOTSUPP;
2473 		}
2474 	}
2475 
2476 	return 0;
2477 }
2478 
2479 static const struct pinconf_ops gemini_pinconf_ops = {
2480 	.pin_config_get = gemini_pinconf_get,
2481 	.pin_config_set = gemini_pinconf_set,
2482 	.pin_config_group_set = gemini_pinconf_group_set,
2483 	.is_generic = true,
2484 };
2485 
2486 static struct pinctrl_desc gemini_pmx_desc = {
2487 	.name = DRIVER_NAME,
2488 	.pctlops = &gemini_pctrl_ops,
2489 	.pmxops = &gemini_pmx_ops,
2490 	.confops = &gemini_pinconf_ops,
2491 	.owner = THIS_MODULE,
2492 };
2493 
gemini_pmx_probe(struct platform_device * pdev)2494 static int gemini_pmx_probe(struct platform_device *pdev)
2495 {
2496 	struct gemini_pmx *pmx;
2497 	struct regmap *map;
2498 	struct device *dev = &pdev->dev;
2499 	struct device *parent;
2500 	unsigned long tmp;
2501 	u32 val;
2502 	int ret;
2503 	int i;
2504 
2505 	/* Create state holders etc for this driver */
2506 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2507 	if (!pmx)
2508 		return -ENOMEM;
2509 
2510 	pmx->dev = &pdev->dev;
2511 	parent = dev->parent;
2512 	if (!parent) {
2513 		dev_err(dev, "no parent to pin controller\n");
2514 		return -ENODEV;
2515 	}
2516 	map = syscon_node_to_regmap(parent->of_node);
2517 	if (IS_ERR(map)) {
2518 		dev_err(dev, "no syscon regmap\n");
2519 		return PTR_ERR(map);
2520 	}
2521 	pmx->map = map;
2522 
2523 	/* Check that regmap works at first call, then no more */
2524 	ret = regmap_read(map, GLOBAL_WORD_ID, &val);
2525 	if (ret) {
2526 		dev_err(dev, "cannot access regmap\n");
2527 		return ret;
2528 	}
2529 	val >>= 8;
2530 	val &= 0xffff;
2531 	if (val == 0x3512) {
2532 		pmx->is_3512 = true;
2533 		pmx->confs = gemini_confs_3512;
2534 		pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
2535 		gemini_pmx_desc.pins = gemini_3512_pins;
2536 		gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
2537 		dev_info(dev, "detected 3512 chip variant\n");
2538 	} else if (val == 0x3516) {
2539 		pmx->is_3516 = true;
2540 		pmx->confs = gemini_confs_3516;
2541 		pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
2542 		gemini_pmx_desc.pins = gemini_3516_pins;
2543 		gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
2544 		dev_info(dev, "detected 3516 chip variant\n");
2545 	} else {
2546 		dev_err(dev, "unknown chip ID: %04x\n", val);
2547 		return -ENODEV;
2548 	}
2549 
2550 	ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
2551 	dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
2552 	/* Mask off relevant pads */
2553 	val &= PADS_MASK;
2554 	/* Invert the meaning of the DRAM+flash pads */
2555 	val ^= 0x0f;
2556 	/* Print initial state */
2557 	tmp = val;
2558 	for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2559 		dev_info(dev, "pad group %s %s\n", gemini_padgroups[i],
2560 			 (val & BIT(i)) ? "enabled" : "disabled");
2561 	}
2562 
2563 	/* Check if flash pin is set */
2564 	regmap_read(map, GLOBAL_STATUS, &val);
2565 	pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
2566 	dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
2567 
2568 	pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
2569 	if (IS_ERR(pmx->pctl)) {
2570 		dev_err(dev, "could not register pinmux driver\n");
2571 		return PTR_ERR(pmx->pctl);
2572 	}
2573 
2574 	dev_info(dev, "initialized Gemini pin control driver\n");
2575 
2576 	return 0;
2577 }
2578 
2579 static const struct of_device_id gemini_pinctrl_match[] = {
2580 	{ .compatible = "cortina,gemini-pinctrl" },
2581 	{},
2582 };
2583 
2584 static struct platform_driver gemini_pmx_driver = {
2585 	.driver = {
2586 		.name = DRIVER_NAME,
2587 		.of_match_table = gemini_pinctrl_match,
2588 	},
2589 	.probe = gemini_pmx_probe,
2590 };
2591 
gemini_pmx_init(void)2592 static int __init gemini_pmx_init(void)
2593 {
2594 	return platform_driver_register(&gemini_pmx_driver);
2595 }
2596 arch_initcall(gemini_pmx_init);
2597