1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 */
10
11 #include <linux/err.h>
12 #include <linux/bug.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/slab.h>
23 #include <linux/platform_device.h>
24 #include <linux/mutex.h>
25 #include <linux/acpi.h>
26 #include <linux/seq_file.h>
27 #include <linux/interrupt.h>
28 #include <linux/list.h>
29 #include <linux/bitops.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/pinctrl/pinmux.h>
33
34 #include "core.h"
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)38 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
39 {
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
47
48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
49 return GPIO_LINE_DIRECTION_OUT;
50
51 return GPIO_LINE_DIRECTION_IN;
52 }
53
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)54 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
55 {
56 unsigned long flags;
57 u32 pin_reg;
58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
59
60 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
63 writel(pin_reg, gpio_dev->base + offset * 4);
64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
65
66 return 0;
67 }
68
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
70 int value)
71 {
72 u32 pin_reg;
73 unsigned long flags;
74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
75
76 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
77 pin_reg = readl(gpio_dev->base + offset * 4);
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
79 if (value)
80 pin_reg |= BIT(OUTPUT_VALUE_OFF);
81 else
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
83 writel(pin_reg, gpio_dev->base + offset * 4);
84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
85
86 return 0;
87 }
88
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
90 {
91 u32 pin_reg;
92 unsigned long flags;
93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
94
95 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
96 pin_reg = readl(gpio_dev->base + offset * 4);
97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
98
99 return !!(pin_reg & BIT(PIN_STS_OFF));
100 }
101
amd_gpio_set_value(struct gpio_chip * gc,unsigned offset,int value)102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
103 {
104 u32 pin_reg;
105 unsigned long flags;
106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
107
108 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
109 pin_reg = readl(gpio_dev->base + offset * 4);
110 if (value)
111 pin_reg |= BIT(OUTPUT_VALUE_OFF);
112 else
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
114 writel(pin_reg, gpio_dev->base + offset * 4);
115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
116 }
117
amd_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
119 unsigned debounce)
120 {
121 u32 time;
122 u32 pin_reg;
123 int ret = 0;
124 unsigned long flags;
125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
126
127 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
128 pin_reg = readl(gpio_dev->base + offset * 4);
129
130 if (debounce) {
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
132 pin_reg &= ~DB_TMR_OUT_MASK;
133 /*
134 Debounce Debounce Timer Max
135 TmrLarge TmrOutUnit Unit Debounce
136 Time
137 0 0 61 usec (2 RtcClk) 976 usec
138 0 1 244 usec (8 RtcClk) 3.9 msec
139 1 0 15.6 msec (512 RtcClk) 250 msec
140 1 1 62.5 msec (2048 RtcClk) 1 sec
141 */
142
143 if (debounce < 61) {
144 pin_reg |= 1;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 976) {
148 time = debounce / 61;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
152 } else if (debounce < 3900) {
153 time = debounce / 244;
154 pin_reg |= time & DB_TMR_OUT_MASK;
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157 } else if (debounce < 250000) {
158 time = debounce / 15625;
159 pin_reg |= time & DB_TMR_OUT_MASK;
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg |= BIT(DB_TMR_LARGE_OFF);
162 } else if (debounce < 1000000) {
163 time = debounce / 62500;
164 pin_reg |= time & DB_TMR_OUT_MASK;
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
166 pin_reg |= BIT(DB_TMR_LARGE_OFF);
167 } else {
168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
169 ret = -EINVAL;
170 }
171 } else {
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
174 pin_reg &= ~DB_TMR_OUT_MASK;
175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
176 }
177 writel(pin_reg, gpio_dev->base + offset * 4);
178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
179
180 return ret;
181 }
182
amd_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
184 unsigned long config)
185 {
186 u32 debounce;
187
188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
189 return -ENOTSUPP;
190
191 debounce = pinconf_to_config_argument(config);
192 return amd_gpio_set_debounce(gc, offset, debounce);
193 }
194
195 #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
197 {
198 u32 pin_reg;
199 u32 db_cntrl;
200 unsigned long flags;
201 unsigned int bank, i, pin_num;
202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
203
204 bool tmr_out_unit;
205 bool tmr_large;
206
207 char *level_trig;
208 char *active_level;
209 char *interrupt_enable;
210 char *interrupt_mask;
211 char *wake_cntrl0;
212 char *wake_cntrl1;
213 char *wake_cntrl2;
214 char *pin_sts;
215 char *pull_up_sel;
216 char *pull_up_enable;
217 char *pull_down_enable;
218 char *orientation;
219 char debounce_value[40];
220 char *debounce_enable;
221
222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
223 unsigned int time = 0;
224 unsigned int unit = 0;
225
226 switch (bank) {
227 case 0:
228 i = 0;
229 pin_num = AMD_GPIO_PINS_BANK0;
230 break;
231 case 1:
232 i = 64;
233 pin_num = AMD_GPIO_PINS_BANK1 + i;
234 break;
235 case 2:
236 i = 128;
237 pin_num = AMD_GPIO_PINS_BANK2 + i;
238 break;
239 case 3:
240 i = 192;
241 pin_num = AMD_GPIO_PINS_BANK3 + i;
242 break;
243 default:
244 /* Illegal bank number, ignore */
245 continue;
246 }
247 seq_printf(s, "GPIO bank%d\n", bank);
248 for (; i < pin_num; i++) {
249 seq_printf(s, "#%d\t", i);
250 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
251 pin_reg = readl(gpio_dev->base + i * 4);
252 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
253
254 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
255 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
256 ACTIVE_LEVEL_MASK;
257 interrupt_enable = "+";
258
259 if (level == ACTIVE_LEVEL_HIGH)
260 active_level = "↑";
261 else if (level == ACTIVE_LEVEL_LOW)
262 active_level = "↓";
263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
264 level == ACTIVE_LEVEL_BOTH)
265 active_level = "b";
266 else
267 active_level = "?";
268
269 if (pin_reg & BIT(LEVEL_TRIG_OFF))
270 level_trig = "level";
271 else
272 level_trig = " edge";
273
274 } else {
275 interrupt_enable = "∅";
276 active_level = "∅";
277 level_trig = " ∅";
278 }
279
280 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
281 interrupt_mask = "��";
282 else
283 interrupt_mask = "��";
284 seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ",
285 interrupt_enable,
286 interrupt_mask,
287 active_level,
288 level_trig);
289
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
291 wake_cntrl0 = "⏰";
292 else
293 wake_cntrl0 = " ∅";
294 seq_printf(s, "S0i3 %s| ", wake_cntrl0);
295
296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
297 wake_cntrl1 = "⏰";
298 else
299 wake_cntrl1 = " ∅";
300 seq_printf(s, "S3 %s| ", wake_cntrl1);
301
302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
303 wake_cntrl2 = "⏰";
304 else
305 wake_cntrl2 = " ∅";
306 seq_printf(s, "S4/S5 %s| ", wake_cntrl2);
307
308 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
309 pull_up_enable = "+";
310 if (pin_reg & BIT(PULL_UP_SEL_OFF))
311 pull_up_sel = "8k";
312 else
313 pull_up_sel = "4k";
314 } else {
315 pull_up_enable = "∅";
316 pull_up_sel = " ";
317 }
318 seq_printf(s, "pull-↑ %s (%s)| ",
319 pull_up_enable,
320 pull_up_sel);
321
322 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
323 pull_down_enable = "+";
324 else
325 pull_down_enable = "∅";
326 seq_printf(s, "pull-↓ %s| ", pull_down_enable);
327
328 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
329 pin_sts = "output";
330 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
331 orientation = "↑";
332 else
333 orientation = "↓";
334 } else {
335 pin_sts = "input ";
336 if (pin_reg & BIT(PIN_STS_OFF))
337 orientation = "↑";
338 else
339 orientation = "↓";
340 }
341 seq_printf(s, "%s %s| ", pin_sts, orientation);
342
343 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
344 if (db_cntrl) {
345 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
346 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
347 time = pin_reg & DB_TMR_OUT_MASK;
348 if (tmr_large) {
349 if (tmr_out_unit)
350 unit = 62500;
351 else
352 unit = 15625;
353 } else {
354 if (tmr_out_unit)
355 unit = 244;
356 else
357 unit = 61;
358 }
359 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
360 debounce_enable = "b +";
361 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
362 debounce_enable = "↓ +";
363 else
364 debounce_enable = "↑ +";
365
366 } else {
367 debounce_enable = " ∅";
368 }
369 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit);
370 seq_printf(s, "debounce %s (�� %sus)| ", debounce_enable, debounce_value);
371 seq_printf(s, " 0x%x\n", pin_reg);
372 }
373 }
374 }
375 #else
376 #define amd_gpio_dbg_show NULL
377 #endif
378
amd_gpio_irq_enable(struct irq_data * d)379 static void amd_gpio_irq_enable(struct irq_data *d)
380 {
381 u32 pin_reg;
382 unsigned long flags;
383 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
384 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
385
386 gpiochip_enable_irq(gc, d->hwirq);
387
388 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
389 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
390 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
391 pin_reg |= BIT(INTERRUPT_MASK_OFF);
392 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
393 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
394 }
395
amd_gpio_irq_disable(struct irq_data * d)396 static void amd_gpio_irq_disable(struct irq_data *d)
397 {
398 u32 pin_reg;
399 unsigned long flags;
400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
401 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
402
403 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
404 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
405 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
406 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
407 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
408 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
409
410 gpiochip_disable_irq(gc, d->hwirq);
411 }
412
amd_gpio_irq_mask(struct irq_data * d)413 static void amd_gpio_irq_mask(struct irq_data *d)
414 {
415 u32 pin_reg;
416 unsigned long flags;
417 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
418 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
419
420 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
424 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
425 }
426
amd_gpio_irq_unmask(struct irq_data * d)427 static void amd_gpio_irq_unmask(struct irq_data *d)
428 {
429 u32 pin_reg;
430 unsigned long flags;
431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
433
434 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
436 pin_reg |= BIT(INTERRUPT_MASK_OFF);
437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
439 }
440
amd_gpio_irq_set_wake(struct irq_data * d,unsigned int on)441 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
442 {
443 u32 pin_reg;
444 unsigned long flags;
445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
447 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
448 int err;
449
450 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
451 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
452
453 if (on)
454 pin_reg |= wake_mask;
455 else
456 pin_reg &= ~wake_mask;
457
458 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
459 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
460
461 if (on)
462 err = enable_irq_wake(gpio_dev->irq);
463 else
464 err = disable_irq_wake(gpio_dev->irq);
465
466 if (err)
467 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
468 on ? "enable" : "disable");
469
470 return 0;
471 }
472
amd_gpio_irq_eoi(struct irq_data * d)473 static void amd_gpio_irq_eoi(struct irq_data *d)
474 {
475 u32 reg;
476 unsigned long flags;
477 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
478 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
479
480 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
481 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
482 reg |= EOI_MASK;
483 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
484 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
485 }
486
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)487 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
488 {
489 int ret = 0;
490 u32 pin_reg, pin_reg_irq_en, mask;
491 unsigned long flags;
492 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
493 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
494
495 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
496 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
497
498 switch (type & IRQ_TYPE_SENSE_MASK) {
499 case IRQ_TYPE_EDGE_RISING:
500 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
501 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
502 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
503 irq_set_handler_locked(d, handle_edge_irq);
504 break;
505
506 case IRQ_TYPE_EDGE_FALLING:
507 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
509 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
510 irq_set_handler_locked(d, handle_edge_irq);
511 break;
512
513 case IRQ_TYPE_EDGE_BOTH:
514 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
516 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
517 irq_set_handler_locked(d, handle_edge_irq);
518 break;
519
520 case IRQ_TYPE_LEVEL_HIGH:
521 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
523 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
524 irq_set_handler_locked(d, handle_level_irq);
525 break;
526
527 case IRQ_TYPE_LEVEL_LOW:
528 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
530 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
531 irq_set_handler_locked(d, handle_level_irq);
532 break;
533
534 case IRQ_TYPE_NONE:
535 break;
536
537 default:
538 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
539 ret = -EINVAL;
540 }
541
542 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
543 /*
544 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
545 * debounce registers of any GPIO will block wake/interrupt status
546 * generation for *all* GPIOs for a length of time that depends on
547 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
548 * INTERRUPT_ENABLE bit will read as 0.
549 *
550 * We temporarily enable irq for the GPIO whose configuration is
551 * changing, and then wait for it to read back as 1 to know when
552 * debounce has settled and then disable the irq again.
553 * We do this polling with the spinlock held to ensure other GPIO
554 * access routines do not read an incorrect value for the irq enable
555 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
556 * spurious irqs, and disable the irq again after polling.
557 */
558 mask = BIT(INTERRUPT_ENABLE_OFF);
559 pin_reg_irq_en = pin_reg;
560 pin_reg_irq_en |= mask;
561 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
562 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
563 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
564 continue;
565 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
566 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
567
568 return ret;
569 }
570
amd_irq_ack(struct irq_data * d)571 static void amd_irq_ack(struct irq_data *d)
572 {
573 /*
574 * based on HW design,there is no need to ack HW
575 * before handle current irq. But this routine is
576 * necessary for handle_edge_irq
577 */
578 }
579
580 static const struct irq_chip amd_gpio_irqchip = {
581 .name = "amd_gpio",
582 .irq_ack = amd_irq_ack,
583 .irq_enable = amd_gpio_irq_enable,
584 .irq_disable = amd_gpio_irq_disable,
585 .irq_mask = amd_gpio_irq_mask,
586 .irq_unmask = amd_gpio_irq_unmask,
587 .irq_set_wake = amd_gpio_irq_set_wake,
588 .irq_eoi = amd_gpio_irq_eoi,
589 .irq_set_type = amd_gpio_irq_set_type,
590 /*
591 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
592 * also generates an IRQ. We need the IRQ so the irq_handler can clear
593 * the wake event. Otherwise the wake event will never clear and
594 * prevent the system from suspending.
595 */
596 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
597 GPIOCHIP_IRQ_RESOURCE_HELPERS,
598 };
599
600 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
601
do_amd_gpio_irq_handler(int irq,void * dev_id)602 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
603 {
604 struct amd_gpio *gpio_dev = dev_id;
605 struct gpio_chip *gc = &gpio_dev->gc;
606 unsigned int i, irqnr;
607 unsigned long flags;
608 u32 __iomem *regs;
609 bool ret = false;
610 u32 regval;
611 u64 status, mask;
612
613 /* Read the wake status */
614 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
615 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
616 status <<= 32;
617 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
618 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
619
620 /* Bit 0-45 contain the relevant status bits */
621 status &= (1ULL << 46) - 1;
622 regs = gpio_dev->base;
623 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
624 if (!(status & mask))
625 continue;
626 status &= ~mask;
627
628 /* Each status bit covers four pins */
629 for (i = 0; i < 4; i++) {
630 regval = readl(regs + i);
631 /* caused wake on resume context for shared IRQ */
632 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
633 dev_dbg(&gpio_dev->pdev->dev,
634 "Waking due to GPIO %d: 0x%x",
635 irqnr + i, regval);
636 return true;
637 }
638
639 if (!(regval & PIN_IRQ_PENDING) ||
640 !(regval & BIT(INTERRUPT_MASK_OFF)))
641 continue;
642 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
643
644 /* Clear interrupt.
645 * We must read the pin register again, in case the
646 * value was changed while executing
647 * generic_handle_domain_irq() above.
648 * If we didn't find a mapping for the interrupt,
649 * disable it in order to avoid a system hang caused
650 * by an interrupt storm.
651 */
652 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
653 regval = readl(regs + i);
654 if (irq == 0) {
655 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
656 dev_dbg(&gpio_dev->pdev->dev,
657 "Disabling spurious GPIO IRQ %d\n",
658 irqnr + i);
659 }
660 writel(regval, regs + i);
661 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
662 ret = true;
663 }
664 }
665 /* did not cause wake on resume context for shared IRQ */
666 if (irq < 0)
667 return false;
668
669 /* Signal EOI to the GPIO unit */
670 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
671 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
672 regval |= EOI_MASK;
673 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
674 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
675
676 return ret;
677 }
678
amd_gpio_irq_handler(int irq,void * dev_id)679 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
680 {
681 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
682 }
683
amd_gpio_check_wake(void * dev_id)684 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
685 {
686 return do_amd_gpio_irq_handler(-1, dev_id);
687 }
688
amd_get_groups_count(struct pinctrl_dev * pctldev)689 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
690 {
691 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
692
693 return gpio_dev->ngroups;
694 }
695
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)696 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
697 unsigned group)
698 {
699 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
700
701 return gpio_dev->groups[group].name;
702 }
703
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)704 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
705 unsigned group,
706 const unsigned **pins,
707 unsigned *num_pins)
708 {
709 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
710
711 *pins = gpio_dev->groups[group].pins;
712 *num_pins = gpio_dev->groups[group].npins;
713 return 0;
714 }
715
716 static const struct pinctrl_ops amd_pinctrl_ops = {
717 .get_groups_count = amd_get_groups_count,
718 .get_group_name = amd_get_group_name,
719 .get_group_pins = amd_get_group_pins,
720 #ifdef CONFIG_OF
721 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
722 .dt_free_map = pinctrl_utils_free_map,
723 #endif
724 };
725
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)726 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
727 unsigned int pin,
728 unsigned long *config)
729 {
730 u32 pin_reg;
731 unsigned arg;
732 unsigned long flags;
733 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
734 enum pin_config_param param = pinconf_to_config_param(*config);
735
736 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
737 pin_reg = readl(gpio_dev->base + pin*4);
738 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
739 switch (param) {
740 case PIN_CONFIG_INPUT_DEBOUNCE:
741 arg = pin_reg & DB_TMR_OUT_MASK;
742 break;
743
744 case PIN_CONFIG_BIAS_PULL_DOWN:
745 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
746 break;
747
748 case PIN_CONFIG_BIAS_PULL_UP:
749 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
750 break;
751
752 case PIN_CONFIG_DRIVE_STRENGTH:
753 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
754 break;
755
756 default:
757 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
758 param);
759 return -ENOTSUPP;
760 }
761
762 *config = pinconf_to_config_packed(param, arg);
763
764 return 0;
765 }
766
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)767 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
768 unsigned long *configs, unsigned num_configs)
769 {
770 int i;
771 u32 arg;
772 int ret = 0;
773 u32 pin_reg;
774 unsigned long flags;
775 enum pin_config_param param;
776 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
777
778 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
779 for (i = 0; i < num_configs; i++) {
780 param = pinconf_to_config_param(configs[i]);
781 arg = pinconf_to_config_argument(configs[i]);
782 pin_reg = readl(gpio_dev->base + pin*4);
783
784 switch (param) {
785 case PIN_CONFIG_INPUT_DEBOUNCE:
786 pin_reg &= ~DB_TMR_OUT_MASK;
787 pin_reg |= arg & DB_TMR_OUT_MASK;
788 break;
789
790 case PIN_CONFIG_BIAS_PULL_DOWN:
791 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
792 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
793 break;
794
795 case PIN_CONFIG_BIAS_PULL_UP:
796 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
797 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
798 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
799 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
800 break;
801
802 case PIN_CONFIG_DRIVE_STRENGTH:
803 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
804 << DRV_STRENGTH_SEL_OFF);
805 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
806 << DRV_STRENGTH_SEL_OFF;
807 break;
808
809 default:
810 dev_err(&gpio_dev->pdev->dev,
811 "Invalid config param %04x\n", param);
812 ret = -ENOTSUPP;
813 }
814
815 writel(pin_reg, gpio_dev->base + pin*4);
816 }
817 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
818
819 return ret;
820 }
821
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)822 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
823 unsigned int group,
824 unsigned long *config)
825 {
826 const unsigned *pins;
827 unsigned npins;
828 int ret;
829
830 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
831 if (ret)
832 return ret;
833
834 if (amd_pinconf_get(pctldev, pins[0], config))
835 return -ENOTSUPP;
836
837 return 0;
838 }
839
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)840 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
841 unsigned group, unsigned long *configs,
842 unsigned num_configs)
843 {
844 const unsigned *pins;
845 unsigned npins;
846 int i, ret;
847
848 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
849 if (ret)
850 return ret;
851 for (i = 0; i < npins; i++) {
852 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
853 return -ENOTSUPP;
854 }
855 return 0;
856 }
857
858 static const struct pinconf_ops amd_pinconf_ops = {
859 .pin_config_get = amd_pinconf_get,
860 .pin_config_set = amd_pinconf_set,
861 .pin_config_group_get = amd_pinconf_group_get,
862 .pin_config_group_set = amd_pinconf_group_set,
863 };
864
amd_gpio_irq_init(struct amd_gpio * gpio_dev)865 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
866 {
867 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
868 unsigned long flags;
869 u32 pin_reg, mask;
870 int i;
871
872 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
873 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
874 BIT(WAKE_CNTRL_OFF_S4);
875
876 for (i = 0; i < desc->npins; i++) {
877 int pin = desc->pins[i].number;
878 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
879
880 if (!pd)
881 continue;
882
883 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
884
885 pin_reg = readl(gpio_dev->base + i * 4);
886 pin_reg &= ~mask;
887 writel(pin_reg, gpio_dev->base + i * 4);
888
889 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
890 }
891 }
892
893 #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)894 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
895 {
896 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
897
898 if (!pd)
899 return false;
900
901 /*
902 * Only restore the pin if it is actually in use by the kernel (or
903 * by userspace).
904 */
905 if (pd->mux_owner || pd->gpio_owner ||
906 gpiochip_line_is_irq(&gpio_dev->gc, pin))
907 return true;
908
909 return false;
910 }
911
amd_gpio_suspend(struct device * dev)912 static int amd_gpio_suspend(struct device *dev)
913 {
914 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
915 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
916 unsigned long flags;
917 int i;
918
919 for (i = 0; i < desc->npins; i++) {
920 int pin = desc->pins[i].number;
921
922 if (!amd_gpio_should_save(gpio_dev, pin))
923 continue;
924
925 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
926 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
927 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
928 }
929
930 return 0;
931 }
932
amd_gpio_resume(struct device * dev)933 static int amd_gpio_resume(struct device *dev)
934 {
935 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
936 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
937 unsigned long flags;
938 int i;
939
940 for (i = 0; i < desc->npins; i++) {
941 int pin = desc->pins[i].number;
942
943 if (!amd_gpio_should_save(gpio_dev, pin))
944 continue;
945
946 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
947 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
948 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
949 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
950 }
951
952 return 0;
953 }
954
955 static const struct dev_pm_ops amd_gpio_pm_ops = {
956 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
957 amd_gpio_resume)
958 };
959 #endif
960
amd_get_functions_count(struct pinctrl_dev * pctldev)961 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
962 {
963 return ARRAY_SIZE(pmx_functions);
964 }
965
amd_get_fname(struct pinctrl_dev * pctrldev,unsigned int selector)966 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
967 {
968 return pmx_functions[selector].name;
969 }
970
amd_get_groups(struct pinctrl_dev * pctrldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)971 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
972 const char * const **groups,
973 unsigned int * const num_groups)
974 {
975 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
976
977 if (!gpio_dev->iomux_base) {
978 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
979 return -EINVAL;
980 }
981
982 *groups = pmx_functions[selector].groups;
983 *num_groups = pmx_functions[selector].ngroups;
984 return 0;
985 }
986
amd_set_mux(struct pinctrl_dev * pctrldev,unsigned int function,unsigned int group)987 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
988 {
989 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
990 struct device *dev = &gpio_dev->pdev->dev;
991 struct pin_desc *pd;
992 int ind, index;
993
994 if (!gpio_dev->iomux_base)
995 return -EINVAL;
996
997 for (index = 0; index < NSELECTS; index++) {
998 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
999 continue;
1000
1001 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1002 FUNCTION_INVALID) {
1003 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1004 pmx_functions[function].index);
1005 return -EINVAL;
1006 }
1007
1008 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1009
1010 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1011 FUNCTION_MASK)) {
1012 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1013 pmx_functions[function].index);
1014 return -EINVAL;
1015 }
1016
1017 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1018 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1019 continue;
1020
1021 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1022 pd->mux_owner = gpio_dev->groups[group].name;
1023 }
1024 break;
1025 }
1026
1027 return 0;
1028 }
1029
1030 static const struct pinmux_ops amd_pmxops = {
1031 .get_functions_count = amd_get_functions_count,
1032 .get_function_name = amd_get_fname,
1033 .get_function_groups = amd_get_groups,
1034 .set_mux = amd_set_mux,
1035 };
1036
1037 static struct pinctrl_desc amd_pinctrl_desc = {
1038 .pins = kerncz_pins,
1039 .npins = ARRAY_SIZE(kerncz_pins),
1040 .pctlops = &amd_pinctrl_ops,
1041 .pmxops = &amd_pmxops,
1042 .confops = &amd_pinconf_ops,
1043 .owner = THIS_MODULE,
1044 };
1045
amd_get_iomux_res(struct amd_gpio * gpio_dev)1046 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1047 {
1048 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1049 struct device *dev = &gpio_dev->pdev->dev;
1050 int index;
1051
1052 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1053 if (index < 0) {
1054 dev_dbg(dev, "iomux not supported\n");
1055 goto out_no_pinmux;
1056 }
1057
1058 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1059 if (IS_ERR(gpio_dev->iomux_base)) {
1060 dev_dbg(dev, "iomux not supported %d io resource\n", index);
1061 goto out_no_pinmux;
1062 }
1063
1064 return;
1065
1066 out_no_pinmux:
1067 desc->pmxops = NULL;
1068 }
1069
amd_gpio_probe(struct platform_device * pdev)1070 static int amd_gpio_probe(struct platform_device *pdev)
1071 {
1072 int ret = 0;
1073 struct resource *res;
1074 struct amd_gpio *gpio_dev;
1075 struct gpio_irq_chip *girq;
1076
1077 gpio_dev = devm_kzalloc(&pdev->dev,
1078 sizeof(struct amd_gpio), GFP_KERNEL);
1079 if (!gpio_dev)
1080 return -ENOMEM;
1081
1082 raw_spin_lock_init(&gpio_dev->lock);
1083
1084 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1085 if (IS_ERR(gpio_dev->base)) {
1086 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1087 return PTR_ERR(gpio_dev->base);
1088 }
1089
1090 gpio_dev->irq = platform_get_irq(pdev, 0);
1091 if (gpio_dev->irq < 0)
1092 return gpio_dev->irq;
1093
1094 #ifdef CONFIG_PM_SLEEP
1095 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1096 sizeof(*gpio_dev->saved_regs),
1097 GFP_KERNEL);
1098 if (!gpio_dev->saved_regs)
1099 return -ENOMEM;
1100 #endif
1101
1102 gpio_dev->pdev = pdev;
1103 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1104 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1105 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1106 gpio_dev->gc.get = amd_gpio_get_value;
1107 gpio_dev->gc.set = amd_gpio_set_value;
1108 gpio_dev->gc.set_config = amd_gpio_set_config;
1109 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1110
1111 gpio_dev->gc.base = -1;
1112 gpio_dev->gc.label = pdev->name;
1113 gpio_dev->gc.owner = THIS_MODULE;
1114 gpio_dev->gc.parent = &pdev->dev;
1115 gpio_dev->gc.ngpio = resource_size(res) / 4;
1116
1117 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1118 gpio_dev->groups = kerncz_groups;
1119 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1120
1121 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1122 amd_get_iomux_res(gpio_dev);
1123 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1124 gpio_dev);
1125 if (IS_ERR(gpio_dev->pctrl)) {
1126 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1127 return PTR_ERR(gpio_dev->pctrl);
1128 }
1129
1130 /* Disable and mask interrupts */
1131 amd_gpio_irq_init(gpio_dev);
1132
1133 girq = &gpio_dev->gc.irq;
1134 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1135 /* This will let us handle the parent IRQ in the driver */
1136 girq->parent_handler = NULL;
1137 girq->num_parents = 0;
1138 girq->parents = NULL;
1139 girq->default_type = IRQ_TYPE_NONE;
1140 girq->handler = handle_simple_irq;
1141
1142 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1143 if (ret)
1144 return ret;
1145
1146 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1147 0, 0, gpio_dev->gc.ngpio);
1148 if (ret) {
1149 dev_err(&pdev->dev, "Failed to add pin range\n");
1150 goto out2;
1151 }
1152
1153 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1154 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
1155 if (ret)
1156 goto out2;
1157
1158 platform_set_drvdata(pdev, gpio_dev);
1159 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1160
1161 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1162 return ret;
1163
1164 out2:
1165 gpiochip_remove(&gpio_dev->gc);
1166
1167 return ret;
1168 }
1169
amd_gpio_remove(struct platform_device * pdev)1170 static int amd_gpio_remove(struct platform_device *pdev)
1171 {
1172 struct amd_gpio *gpio_dev;
1173
1174 gpio_dev = platform_get_drvdata(pdev);
1175
1176 gpiochip_remove(&gpio_dev->gc);
1177 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1178
1179 return 0;
1180 }
1181
1182 #ifdef CONFIG_ACPI
1183 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1184 { "AMD0030", 0 },
1185 { "AMDI0030", 0},
1186 { "AMDI0031", 0},
1187 { },
1188 };
1189 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1190 #endif
1191
1192 static struct platform_driver amd_gpio_driver = {
1193 .driver = {
1194 .name = "amd_gpio",
1195 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1196 #ifdef CONFIG_PM_SLEEP
1197 .pm = &amd_gpio_pm_ops,
1198 #endif
1199 },
1200 .probe = amd_gpio_probe,
1201 .remove = amd_gpio_remove,
1202 };
1203
1204 module_platform_driver(amd_gpio_driver);
1205
1206 MODULE_LICENSE("GPL v2");
1207 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1208 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1209
