1 /*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Biao Huang <biao.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/regmap.h>
22
23 #include "pinctrl-mtk-common.h"
24 #include "pinctrl-mtk-mt2701.h"
25
26 /**
27 * struct mtk_spec_pinmux_set
28 * - For special pins' mode setting
29 * @pin: The pin number.
30 * @offset: The offset of extra setting register.
31 * @bit: The bit of extra setting register.
32 */
33 struct mtk_spec_pinmux_set {
34 unsigned short pin;
35 unsigned short offset;
36 unsigned char bit;
37 };
38
39 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
40 { \
41 .pin = _pin, \
42 .offset = _offset, \
43 .bit = _bit, \
44 }
45
46 static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
47 /* 0E4E8SR 4/8/12/16 */
48 MTK_DRV_GRP(4, 16, 1, 2, 4),
49 /* 0E2E4SR 2/4/6/8 */
50 MTK_DRV_GRP(2, 8, 1, 2, 2),
51 /* E8E4E2 2/4/6/8/10/12/14/16 */
52 MTK_DRV_GRP(2, 16, 0, 2, 2)
53 };
54
55 static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
56 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
57 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
58 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
59 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
60 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
61 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
62 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
63 MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
64 MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
65 MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
66 MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
67 MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
68 MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
69 MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
70 MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
71 MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
72 MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
73 MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
74 MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
75 MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
76 MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
77 MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
78 MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
79 MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
80 MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
81 MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
82 MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
83 MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
84 MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
85 MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
86 MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
87 MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
88 MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
89 MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
90 MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
91 MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
92 MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
93 MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
94 MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
95 MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
96 MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
97 MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
98 MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
99 MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
100 MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
101 MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
102 MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
103 MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
104 MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
105 MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
106 MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
107 MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
108 MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
109 MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
110 MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
111 MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
112 MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
113 MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
114 MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
115 MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
116 MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
117 MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
118 MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
119 MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
120 MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
121 MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
122 MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
123 MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
124 MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
125 MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
126 MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
127 MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
128 MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
129 MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
130 MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
131 MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
132 MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
133 MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
134 MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
135 MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
136 MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
137 MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
138 MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
139 MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
140 MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
141 MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
142 MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
143 MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
144 MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
145 MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
146 MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
147 MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
148 MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
149 MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
150 MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
151 MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
152 MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
153 MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
154 MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
155 MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
156 MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
157 MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
158 MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
159 MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
160 MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
161 MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
162 MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
163 MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
164 MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
165 MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
166 MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
167 MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
168 MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
169 MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
170 MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
171 MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
172 MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
173 MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
174 MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
175 MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
176 MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
177 MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
178 MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
179 MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
180 MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
181 MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
182 MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
183 MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
184 MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
185 MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
186 MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
187 MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
188 MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
189 MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
190 MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
191 MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
192 MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
193 MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
194 MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
195 MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
196 MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
197 MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
198 MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
199 MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
200 MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
201 MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
202 MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
203 MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
204 MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
205 MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
206 MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
207 MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
208 MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
209 MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
210 MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
211 MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
212 MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
213 MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
214 MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
215 MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
216 MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
217 MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
218 MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
219 MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
220 MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
221 MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
222 MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
223 MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
224 MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
225 MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
226 MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
227 MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
228 MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
229 MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
230 MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
231 MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
232 MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
233 MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
234 MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
235 MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
236 MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
237 MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
238 };
239
240 static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
241 MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
242 MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
243 MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
244 MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
245 MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
246 MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
247 MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
248 MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
249 MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
250 MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
251 MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
252
253 MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
254 MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
255 MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
256 MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
257 MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
258 MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
259
260 MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
261 MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
262 MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
263 MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
264 MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
265 MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
266
267 MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
268 MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
269 MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
270 MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
271 MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
272 MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
273 MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
274 MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
275 MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
276 MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
277 MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
278 MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
279 };
280
mt2701_spec_pull_set(struct regmap * regmap,unsigned int pin,unsigned char align,bool isup,unsigned int r1r0)281 static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
282 unsigned char align, bool isup, unsigned int r1r0)
283 {
284 return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
285 ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
286 }
287
288 static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
289 MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
290 MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
291 MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
292 MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
293 MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
294 MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
295 MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
296 MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
297 MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
298 MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
299 MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
300 MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
301 MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
302 MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
303 MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
304 MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
305 MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
306 MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
307 MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
308 MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
309 MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
310 MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
311 MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
312 MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
313 MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
314 MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
315 MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
316 MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
317 MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
318 MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
319 MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
320 MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
321 MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
322 MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
323 MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
324 MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
325 MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
326 MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
327 MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
328 MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
329 MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
330 MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
331 MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
332 MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
333 MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
334 MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
335 MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
336 MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
337 MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
338 MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
339 MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
340 MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
341 MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
342 MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
343 MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
344 MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
345 MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
346 MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
347 MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
348 MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
349 MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
350 MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
351 MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
352 MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
353 MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
354 MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
355 };
356
357 static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
358 MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
359 MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
360 MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
361 MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
362 MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
363 MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
364 MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
365 MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
366 MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
367 MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
368 MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
369 MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
370 MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
371 MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
372 MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
373 MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
374 MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
375 MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
376 MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
377 MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
378 MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
379 MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
380 MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
381 MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
382 MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
383 MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
384 MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
385 MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
386 MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
387 MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
388 MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
389 MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
390 MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
391 MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
392 MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
393 MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
394 MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
395 MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
396 MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
397 MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
398 MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
399 MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
400 MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
401 MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
402 MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
403 MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
404 MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
405 MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
406 MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
407 MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
408 MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
409 MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
410 MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
411 MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
412 MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
413 MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
414 MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
415 MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
416 MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
417 MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
418 MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
419 MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
420 MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
421 MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
422 MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
423 MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
424 MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
425 MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
426 MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
427 MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
428 MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
429 MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
430 MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
431 MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
432 MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
433 MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
434 MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
435 MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
436 MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
437 MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
438 MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
439 MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
440 MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
441 MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
442 MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
443 MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
444 MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
445 };
446
mt2701_ies_smt_set(struct regmap * regmap,unsigned int pin,unsigned char align,int value,enum pin_config_param arg)447 static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
448 unsigned char align, int value, enum pin_config_param arg)
449 {
450 if (arg == PIN_CONFIG_INPUT_ENABLE)
451 return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
452 ARRAY_SIZE(mt2701_ies_set), pin, align, value);
453 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
454 return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
455 ARRAY_SIZE(mt2701_smt_set), pin, align, value);
456 return -EINVAL;
457 }
458
459 static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
460 MTK_PINMUX_SPEC(22, 0xb10, 3),
461 MTK_PINMUX_SPEC(23, 0xb10, 4),
462 MTK_PINMUX_SPEC(24, 0xb10, 5),
463 MTK_PINMUX_SPEC(29, 0xb10, 9),
464 MTK_PINMUX_SPEC(208, 0xb10, 7),
465 MTK_PINMUX_SPEC(209, 0xb10, 8),
466 MTK_PINMUX_SPEC(203, 0xf20, 0),
467 MTK_PINMUX_SPEC(204, 0xf20, 1),
468 MTK_PINMUX_SPEC(249, 0xef0, 0),
469 MTK_PINMUX_SPEC(250, 0xef0, 0),
470 MTK_PINMUX_SPEC(251, 0xef0, 0),
471 MTK_PINMUX_SPEC(252, 0xef0, 0),
472 MTK_PINMUX_SPEC(253, 0xef0, 0),
473 MTK_PINMUX_SPEC(254, 0xef0, 0),
474 MTK_PINMUX_SPEC(255, 0xef0, 0),
475 MTK_PINMUX_SPEC(256, 0xef0, 0),
476 MTK_PINMUX_SPEC(257, 0xef0, 0),
477 MTK_PINMUX_SPEC(258, 0xef0, 0),
478 MTK_PINMUX_SPEC(259, 0xef0, 0),
479 MTK_PINMUX_SPEC(260, 0xef0, 0),
480 };
481
mt2701_spec_pinmux_set(struct regmap * reg,unsigned int pin,unsigned int mode)482 static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
483 unsigned int mode)
484 {
485 unsigned int i, value, mask;
486 unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
487 unsigned int spec_flag;
488
489 for (i = 0; i < info_num; i++) {
490 if (pin == mt2701_spec_pinmux[i].pin)
491 break;
492 }
493
494 if (i == info_num)
495 return;
496
497 spec_flag = (mode >> 3);
498 mask = BIT(mt2701_spec_pinmux[i].bit);
499 if (!spec_flag)
500 value = mask;
501 else
502 value = 0;
503 regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
504 }
505
mt2701_spec_dir_set(unsigned int * reg_addr,unsigned int pin)506 static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
507 {
508 if (pin > 175)
509 *reg_addr += 0x10;
510 }
511
512 static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
513 .pins = mtk_pins_mt2701,
514 .npins = ARRAY_SIZE(mtk_pins_mt2701),
515 .grp_desc = mt2701_drv_grp,
516 .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
517 .pin_drv_grp = mt2701_pin_drv,
518 .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
519 .spec_pull_set = mt2701_spec_pull_set,
520 .spec_ies_smt_set = mt2701_ies_smt_set,
521 .spec_pinmux_set = mt2701_spec_pinmux_set,
522 .spec_dir_set = mt2701_spec_dir_set,
523 .dir_offset = 0x0000,
524 .pullen_offset = 0x0150,
525 .pullsel_offset = 0x0280,
526 .dout_offset = 0x0500,
527 .din_offset = 0x0630,
528 .pinmux_offset = 0x0760,
529 .type1_start = 280,
530 .type1_end = 280,
531 .port_shf = 4,
532 .port_mask = 0x1f,
533 .port_align = 4,
534 .eint_hw = {
535 .port_mask = 6,
536 .ports = 6,
537 .ap_num = 169,
538 .db_cnt = 16,
539 },
540 };
541
mt2701_pinctrl_probe(struct platform_device * pdev)542 static int mt2701_pinctrl_probe(struct platform_device *pdev)
543 {
544 return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
545 }
546
547 static const struct of_device_id mt2701_pctrl_match[] = {
548 { .compatible = "mediatek,mt2701-pinctrl", },
549 { .compatible = "mediatek,mt7623-pinctrl", },
550 {}
551 };
552 MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
553
554 static struct platform_driver mtk_pinctrl_driver = {
555 .probe = mt2701_pinctrl_probe,
556 .driver = {
557 .name = "mediatek-mt2701-pinctrl",
558 .of_match_table = mt2701_pctrl_match,
559 .pm = &mtk_eint_pm_ops,
560 },
561 };
562
mtk_pinctrl_init(void)563 static int __init mtk_pinctrl_init(void)
564 {
565 return platform_driver_register(&mtk_pinctrl_driver);
566 }
567 arch_initcall(mtk_pinctrl_init);
568
