1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RISC-V performance counter support.
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 *
7 * This code is based on ARM perf event code which is in turn based on
8 * sparc64 and x86 code.
9 */
10
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
12
13 #include <linux/mod_devicetable.h>
14 #include <linux/perf/riscv_pmu.h>
15 #include <linux/platform_device.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/of_irq.h>
19 #include <linux/of.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/sched/clock.h>
22
23 #include <asm/sbi.h>
24 #include <asm/hwcap.h>
25
26 PMU_FORMAT_ATTR(event, "config:0-47");
27 PMU_FORMAT_ATTR(firmware, "config:63");
28
29 static struct attribute *riscv_arch_formats_attr[] = {
30 &format_attr_event.attr,
31 &format_attr_firmware.attr,
32 NULL,
33 };
34
35 static struct attribute_group riscv_pmu_format_group = {
36 .name = "format",
37 .attrs = riscv_arch_formats_attr,
38 };
39
40 static const struct attribute_group *riscv_pmu_attr_groups[] = {
41 &riscv_pmu_format_group,
42 NULL,
43 };
44
45 /*
46 * RISC-V doesn't have hetergenous harts yet. This need to be part of
47 * per_cpu in case of harts with different pmu counters
48 */
49 static union sbi_pmu_ctr_info *pmu_ctr_list;
50 static unsigned int riscv_pmu_irq;
51
52 struct sbi_pmu_event_data {
53 union {
54 union {
55 struct hw_gen_event {
56 uint32_t event_code:16;
57 uint32_t event_type:4;
58 uint32_t reserved:12;
59 } hw_gen_event;
60 struct hw_cache_event {
61 uint32_t result_id:1;
62 uint32_t op_id:2;
63 uint32_t cache_id:13;
64 uint32_t event_type:4;
65 uint32_t reserved:12;
66 } hw_cache_event;
67 };
68 uint32_t event_idx;
69 };
70 };
71
72 static const struct sbi_pmu_event_data pmu_hw_event_map[] = {
73 [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = {
74 SBI_PMU_HW_CPU_CYCLES,
75 SBI_PMU_EVENT_TYPE_HW, 0}},
76 [PERF_COUNT_HW_INSTRUCTIONS] = {.hw_gen_event = {
77 SBI_PMU_HW_INSTRUCTIONS,
78 SBI_PMU_EVENT_TYPE_HW, 0}},
79 [PERF_COUNT_HW_CACHE_REFERENCES] = {.hw_gen_event = {
80 SBI_PMU_HW_CACHE_REFERENCES,
81 SBI_PMU_EVENT_TYPE_HW, 0}},
82 [PERF_COUNT_HW_CACHE_MISSES] = {.hw_gen_event = {
83 SBI_PMU_HW_CACHE_MISSES,
84 SBI_PMU_EVENT_TYPE_HW, 0}},
85 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = {.hw_gen_event = {
86 SBI_PMU_HW_BRANCH_INSTRUCTIONS,
87 SBI_PMU_EVENT_TYPE_HW, 0}},
88 [PERF_COUNT_HW_BRANCH_MISSES] = {.hw_gen_event = {
89 SBI_PMU_HW_BRANCH_MISSES,
90 SBI_PMU_EVENT_TYPE_HW, 0}},
91 [PERF_COUNT_HW_BUS_CYCLES] = {.hw_gen_event = {
92 SBI_PMU_HW_BUS_CYCLES,
93 SBI_PMU_EVENT_TYPE_HW, 0}},
94 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = {
95 SBI_PMU_HW_STALLED_CYCLES_FRONTEND,
96 SBI_PMU_EVENT_TYPE_HW, 0}},
97 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = {
98 SBI_PMU_HW_STALLED_CYCLES_BACKEND,
99 SBI_PMU_EVENT_TYPE_HW, 0}},
100 [PERF_COUNT_HW_REF_CPU_CYCLES] = {.hw_gen_event = {
101 SBI_PMU_HW_REF_CPU_CYCLES,
102 SBI_PMU_EVENT_TYPE_HW, 0}},
103 };
104
105 #define C(x) PERF_COUNT_HW_CACHE_##x
106 static const struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
107 [PERF_COUNT_HW_CACHE_OP_MAX]
108 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
109 [C(L1D)] = {
110 [C(OP_READ)] = {
111 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
112 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
113 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
114 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
115 },
116 [C(OP_WRITE)] = {
117 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
118 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
119 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
120 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
121 },
122 [C(OP_PREFETCH)] = {
123 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
124 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
125 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
126 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
127 },
128 },
129 [C(L1I)] = {
130 [C(OP_READ)] = {
131 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
132 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
133 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
134 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
135 },
136 [C(OP_WRITE)] = {
137 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
138 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
139 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
140 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
141 },
142 [C(OP_PREFETCH)] = {
143 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
144 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
145 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
146 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
147 },
148 },
149 [C(LL)] = {
150 [C(OP_READ)] = {
151 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
152 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
153 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
154 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
155 },
156 [C(OP_WRITE)] = {
157 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
158 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
159 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
160 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
161 },
162 [C(OP_PREFETCH)] = {
163 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
164 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
166 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
167 },
168 },
169 [C(DTLB)] = {
170 [C(OP_READ)] = {
171 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
172 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
173 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
174 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
175 },
176 [C(OP_WRITE)] = {
177 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
178 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
179 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
180 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
181 },
182 [C(OP_PREFETCH)] = {
183 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
184 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
185 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
186 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
187 },
188 },
189 [C(ITLB)] = {
190 [C(OP_READ)] = {
191 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
192 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
193 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
194 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
195 },
196 [C(OP_WRITE)] = {
197 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
198 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
199 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
200 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
201 },
202 [C(OP_PREFETCH)] = {
203 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
204 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
205 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
206 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
207 },
208 },
209 [C(BPU)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
212 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
213 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
214 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
215 },
216 [C(OP_WRITE)] = {
217 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
218 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
219 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
220 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
221 },
222 [C(OP_PREFETCH)] = {
223 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
224 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
225 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
226 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
227 },
228 },
229 [C(NODE)] = {
230 [C(OP_READ)] = {
231 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
232 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
233 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
234 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
235 },
236 [C(OP_WRITE)] = {
237 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
238 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
239 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
240 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
241 },
242 [C(OP_PREFETCH)] = {
243 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
244 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
245 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
246 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
247 },
248 },
249 };
250
pmu_sbi_ctr_get_width(int idx)251 static int pmu_sbi_ctr_get_width(int idx)
252 {
253 return pmu_ctr_list[idx].width;
254 }
255
pmu_sbi_ctr_is_fw(int cidx)256 static bool pmu_sbi_ctr_is_fw(int cidx)
257 {
258 union sbi_pmu_ctr_info *info;
259
260 info = &pmu_ctr_list[cidx];
261 if (!info)
262 return false;
263
264 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
265 }
266
pmu_sbi_ctr_get_idx(struct perf_event * event)267 static int pmu_sbi_ctr_get_idx(struct perf_event *event)
268 {
269 struct hw_perf_event *hwc = &event->hw;
270 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
271 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
272 struct sbiret ret;
273 int idx;
274 uint64_t cbase = 0;
275 unsigned long cflags = 0;
276
277 if (event->attr.exclude_kernel)
278 cflags |= SBI_PMU_CFG_FLAG_SET_SINH;
279 if (event->attr.exclude_user)
280 cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
281
282 /* retrieve the available counter index */
283 #if defined(CONFIG_32BIT)
284 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
285 rvpmu->cmask, cflags, hwc->event_base, hwc->config,
286 hwc->config >> 32);
287 #else
288 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase,
289 rvpmu->cmask, cflags, hwc->event_base, hwc->config, 0);
290 #endif
291 if (ret.error) {
292 pr_debug("Not able to find a counter for event %lx config %llx\n",
293 hwc->event_base, hwc->config);
294 return sbi_err_map_linux_errno(ret.error);
295 }
296
297 idx = ret.value;
298 if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value)
299 return -ENOENT;
300
301 /* Additional sanity check for the counter id */
302 if (pmu_sbi_ctr_is_fw(idx)) {
303 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs))
304 return idx;
305 } else {
306 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs))
307 return idx;
308 }
309
310 return -ENOENT;
311 }
312
pmu_sbi_ctr_clear_idx(struct perf_event * event)313 static void pmu_sbi_ctr_clear_idx(struct perf_event *event)
314 {
315
316 struct hw_perf_event *hwc = &event->hw;
317 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
318 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
319 int idx = hwc->idx;
320
321 if (pmu_sbi_ctr_is_fw(idx))
322 clear_bit(idx, cpuc->used_fw_ctrs);
323 else
324 clear_bit(idx, cpuc->used_hw_ctrs);
325 }
326
pmu_event_find_cache(u64 config)327 static int pmu_event_find_cache(u64 config)
328 {
329 unsigned int cache_type, cache_op, cache_result, ret;
330
331 cache_type = (config >> 0) & 0xff;
332 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
333 return -EINVAL;
334
335 cache_op = (config >> 8) & 0xff;
336 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
337 return -EINVAL;
338
339 cache_result = (config >> 16) & 0xff;
340 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
341 return -EINVAL;
342
343 ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;
344
345 return ret;
346 }
347
pmu_sbi_is_fw_event(struct perf_event * event)348 static bool pmu_sbi_is_fw_event(struct perf_event *event)
349 {
350 u32 type = event->attr.type;
351 u64 config = event->attr.config;
352
353 if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1))
354 return true;
355 else
356 return false;
357 }
358
pmu_sbi_event_map(struct perf_event * event,u64 * econfig)359 static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
360 {
361 u32 type = event->attr.type;
362 u64 config = event->attr.config;
363 int bSoftware;
364 u64 raw_config_val;
365 int ret;
366
367 switch (type) {
368 case PERF_TYPE_HARDWARE:
369 if (config >= PERF_COUNT_HW_MAX)
370 return -EINVAL;
371 ret = pmu_hw_event_map[event->attr.config].event_idx;
372 break;
373 case PERF_TYPE_HW_CACHE:
374 ret = pmu_event_find_cache(config);
375 break;
376 case PERF_TYPE_RAW:
377 /*
378 * As per SBI specification, the upper 16 bits must be unused for
379 * a raw event. Use the MSB (63b) to distinguish between hardware
380 * raw event and firmware events.
381 */
382 bSoftware = config >> 63;
383 raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
384 if (bSoftware) {
385 if (raw_config_val < SBI_PMU_FW_MAX)
386 ret = (raw_config_val & 0xFFFF) |
387 (SBI_PMU_EVENT_TYPE_FW << 16);
388 else
389 return -EINVAL;
390 } else {
391 ret = RISCV_PMU_RAW_EVENT_IDX;
392 *econfig = raw_config_val;
393 }
394 break;
395 default:
396 ret = -EINVAL;
397 break;
398 }
399
400 return ret;
401 }
402
pmu_sbi_ctr_read(struct perf_event * event)403 static u64 pmu_sbi_ctr_read(struct perf_event *event)
404 {
405 struct hw_perf_event *hwc = &event->hw;
406 int idx = hwc->idx;
407 struct sbiret ret;
408 union sbi_pmu_ctr_info info;
409 u64 val = 0;
410
411 if (pmu_sbi_is_fw_event(event)) {
412 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ,
413 hwc->idx, 0, 0, 0, 0, 0);
414 if (!ret.error)
415 val = ret.value;
416 } else {
417 info = pmu_ctr_list[idx];
418 val = riscv_pmu_ctr_read_csr(info.csr);
419 if (IS_ENABLED(CONFIG_32BIT))
420 val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val;
421 }
422
423 return val;
424 }
425
pmu_sbi_ctr_start(struct perf_event * event,u64 ival)426 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
427 {
428 struct sbiret ret;
429 struct hw_perf_event *hwc = &event->hw;
430 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
431
432 #if defined(CONFIG_32BIT)
433 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
434 1, flag, ival, ival >> 32, 0);
435 #else
436 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
437 1, flag, ival, 0, 0);
438 #endif
439 if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
440 pr_err("Starting counter idx %d failed with error %d\n",
441 hwc->idx, sbi_err_map_linux_errno(ret.error));
442 }
443
pmu_sbi_ctr_stop(struct perf_event * event,unsigned long flag)444 static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
445 {
446 struct sbiret ret;
447 struct hw_perf_event *hwc = &event->hw;
448
449 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
450 if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
451 flag != SBI_PMU_STOP_FLAG_RESET)
452 pr_err("Stopping counter idx %d failed with error %d\n",
453 hwc->idx, sbi_err_map_linux_errno(ret.error));
454 }
455
pmu_sbi_find_num_ctrs(void)456 static int pmu_sbi_find_num_ctrs(void)
457 {
458 struct sbiret ret;
459
460 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);
461 if (!ret.error)
462 return ret.value;
463 else
464 return sbi_err_map_linux_errno(ret.error);
465 }
466
pmu_sbi_get_ctrinfo(int nctr,unsigned long * mask)467 static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
468 {
469 struct sbiret ret;
470 int i, num_hw_ctr = 0, num_fw_ctr = 0;
471 union sbi_pmu_ctr_info cinfo;
472
473 pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
474 if (!pmu_ctr_list)
475 return -ENOMEM;
476
477 for (i = 0; i < nctr; i++) {
478 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
479 if (ret.error)
480 /* The logical counter ids are not expected to be contiguous */
481 continue;
482
483 *mask |= BIT(i);
484
485 cinfo.value = ret.value;
486 if (cinfo.type == SBI_PMU_CTR_TYPE_FW)
487 num_fw_ctr++;
488 else
489 num_hw_ctr++;
490 pmu_ctr_list[i].value = cinfo.value;
491 }
492
493 pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr);
494
495 return 0;
496 }
497
pmu_sbi_stop_all(struct riscv_pmu * pmu)498 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
499 {
500 /*
501 * No need to check the error because we are disabling all the counters
502 * which may include counters that are not enabled yet.
503 */
504 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
505 0, pmu->cmask, 0, 0, 0, 0);
506 }
507
pmu_sbi_stop_hw_ctrs(struct riscv_pmu * pmu)508 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
509 {
510 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
511
512 /* No need to check the error here as we can't do anything about the error */
513 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0,
514 cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0);
515 }
516
517 /*
518 * This function starts all the used counters in two step approach.
519 * Any counter that did not overflow can be start in a single step
520 * while the overflowed counters need to be started with updated initialization
521 * value.
522 */
pmu_sbi_start_overflow_mask(struct riscv_pmu * pmu,unsigned long ctr_ovf_mask)523 static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
524 unsigned long ctr_ovf_mask)
525 {
526 int idx = 0;
527 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
528 struct perf_event *event;
529 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
530 unsigned long ctr_start_mask = 0;
531 uint64_t max_period;
532 struct hw_perf_event *hwc;
533 u64 init_val = 0;
534
535 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask;
536
537 /* Start all the counters that did not overflow in a single shot */
538 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask,
539 0, 0, 0, 0);
540
541 /* Reinitialize and start all the counter that overflowed */
542 while (ctr_ovf_mask) {
543 if (ctr_ovf_mask & 0x01) {
544 event = cpu_hw_evt->events[idx];
545 hwc = &event->hw;
546 max_period = riscv_pmu_ctr_get_width_mask(event);
547 init_val = local64_read(&hwc->prev_count) & max_period;
548 #if defined(CONFIG_32BIT)
549 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
550 flag, init_val, init_val >> 32, 0);
551 #else
552 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
553 flag, init_val, 0, 0);
554 #endif
555 perf_event_update_userpage(event);
556 }
557 ctr_ovf_mask = ctr_ovf_mask >> 1;
558 idx++;
559 }
560 }
561
pmu_sbi_ovf_handler(int irq,void * dev)562 static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
563 {
564 struct perf_sample_data data;
565 struct pt_regs *regs;
566 struct hw_perf_event *hw_evt;
567 union sbi_pmu_ctr_info *info;
568 int lidx, hidx, fidx;
569 struct riscv_pmu *pmu;
570 struct perf_event *event;
571 unsigned long overflow;
572 unsigned long overflowed_ctrs = 0;
573 struct cpu_hw_events *cpu_hw_evt = dev;
574 u64 start_clock = sched_clock();
575
576 if (WARN_ON_ONCE(!cpu_hw_evt))
577 return IRQ_NONE;
578
579 /* Firmware counter don't support overflow yet */
580 fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS);
581 event = cpu_hw_evt->events[fidx];
582 if (!event) {
583 csr_clear(CSR_SIP, SIP_LCOFIP);
584 return IRQ_NONE;
585 }
586
587 pmu = to_riscv_pmu(event->pmu);
588 pmu_sbi_stop_hw_ctrs(pmu);
589
590 /* Overflow status register should only be read after counter are stopped */
591 overflow = csr_read(CSR_SSCOUNTOVF);
592
593 /*
594 * Overflow interrupt pending bit should only be cleared after stopping
595 * all the counters to avoid any race condition.
596 */
597 csr_clear(CSR_SIP, SIP_LCOFIP);
598
599 /* No overflow bit is set */
600 if (!overflow)
601 return IRQ_NONE;
602
603 regs = get_irq_regs();
604
605 for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) {
606 struct perf_event *event = cpu_hw_evt->events[lidx];
607
608 /* Skip if invalid event or user did not request a sampling */
609 if (!event || !is_sampling_event(event))
610 continue;
611
612 info = &pmu_ctr_list[lidx];
613 /* Do a sanity check */
614 if (!info || info->type != SBI_PMU_CTR_TYPE_HW)
615 continue;
616
617 /* compute hardware counter index */
618 hidx = info->csr - CSR_CYCLE;
619 /* check if the corresponding bit is set in sscountovf */
620 if (!(overflow & (1 << hidx)))
621 continue;
622
623 /*
624 * Keep a track of overflowed counters so that they can be started
625 * with updated initial value.
626 */
627 overflowed_ctrs |= 1 << lidx;
628 hw_evt = &event->hw;
629 riscv_pmu_event_update(event);
630 perf_sample_data_init(&data, 0, hw_evt->last_period);
631 if (riscv_pmu_event_set_period(event)) {
632 /*
633 * Unlike other ISAs, RISC-V don't have to disable interrupts
634 * to avoid throttling here. As per the specification, the
635 * interrupt remains disabled until the OF bit is set.
636 * Interrupts are enabled again only during the start.
637 * TODO: We will need to stop the guest counters once
638 * virtualization support is added.
639 */
640 perf_event_overflow(event, &data, regs);
641 }
642 }
643
644 pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
645 perf_sample_event_took(sched_clock() - start_clock);
646
647 return IRQ_HANDLED;
648 }
649
pmu_sbi_starting_cpu(unsigned int cpu,struct hlist_node * node)650 static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
651 {
652 struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
653 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
654
655 /*
656 * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
657 * as is necessary to maintain uABI compatibility.
658 */
659 csr_write(CSR_SCOUNTEREN, 0x7);
660
661 /* Stop all the counters so that they can be enabled from perf */
662 pmu_sbi_stop_all(pmu);
663
664 if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
665 cpu_hw_evt->irq = riscv_pmu_irq;
666 csr_clear(CSR_IP, BIT(RV_IRQ_PMU));
667 csr_set(CSR_IE, BIT(RV_IRQ_PMU));
668 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
669 }
670
671 return 0;
672 }
673
pmu_sbi_dying_cpu(unsigned int cpu,struct hlist_node * node)674 static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
675 {
676 if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
677 disable_percpu_irq(riscv_pmu_irq);
678 csr_clear(CSR_IE, BIT(RV_IRQ_PMU));
679 }
680
681 /* Disable all counters access for user mode now */
682 csr_write(CSR_SCOUNTEREN, 0x0);
683
684 return 0;
685 }
686
pmu_sbi_setup_irqs(struct riscv_pmu * pmu,struct platform_device * pdev)687 static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
688 {
689 int ret;
690 struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
691 struct device_node *cpu, *child;
692 struct irq_domain *domain = NULL;
693
694 if (!riscv_isa_extension_available(NULL, SSCOFPMF))
695 return -EOPNOTSUPP;
696
697 for_each_of_cpu_node(cpu) {
698 child = of_get_compatible_child(cpu, "riscv,cpu-intc");
699 if (!child) {
700 pr_err("Failed to find INTC node\n");
701 of_node_put(cpu);
702 return -ENODEV;
703 }
704 domain = irq_find_host(child);
705 of_node_put(child);
706 if (domain) {
707 of_node_put(cpu);
708 break;
709 }
710 }
711 if (!domain) {
712 pr_err("Failed to find INTC IRQ root domain\n");
713 return -ENODEV;
714 }
715
716 riscv_pmu_irq = irq_create_mapping(domain, RV_IRQ_PMU);
717 if (!riscv_pmu_irq) {
718 pr_err("Failed to map PMU interrupt for node\n");
719 return -ENODEV;
720 }
721
722 ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
723 if (ret) {
724 pr_err("registering percpu irq failed [%d]\n", ret);
725 return ret;
726 }
727
728 return 0;
729 }
730
731 #ifdef CONFIG_CPU_PM
riscv_pm_pmu_notify(struct notifier_block * b,unsigned long cmd,void * v)732 static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
733 void *v)
734 {
735 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb);
736 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
737 int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS);
738 struct perf_event *event;
739 int idx;
740
741 if (!enabled)
742 return NOTIFY_OK;
743
744 for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) {
745 event = cpuc->events[idx];
746 if (!event)
747 continue;
748
749 switch (cmd) {
750 case CPU_PM_ENTER:
751 /*
752 * Stop and update the counter
753 */
754 riscv_pmu_stop(event, PERF_EF_UPDATE);
755 break;
756 case CPU_PM_EXIT:
757 case CPU_PM_ENTER_FAILED:
758 /*
759 * Restore and enable the counter.
760 *
761 * Requires RCU read locking to be functional,
762 * wrap the call within RCU_NONIDLE to make the
763 * RCU subsystem aware this cpu is not idle from
764 * an RCU perspective for the riscv_pmu_start() call
765 * duration.
766 */
767 RCU_NONIDLE(riscv_pmu_start(event, PERF_EF_RELOAD));
768 break;
769 default:
770 break;
771 }
772 }
773
774 return NOTIFY_OK;
775 }
776
riscv_pm_pmu_register(struct riscv_pmu * pmu)777 static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
778 {
779 pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
780 return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
781 }
782
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)783 static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
784 {
785 cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
786 }
787 #else
riscv_pm_pmu_register(struct riscv_pmu * pmu)788 static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
riscv_pm_pmu_unregister(struct riscv_pmu * pmu)789 static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
790 #endif
791
riscv_pmu_destroy(struct riscv_pmu * pmu)792 static void riscv_pmu_destroy(struct riscv_pmu *pmu)
793 {
794 riscv_pm_pmu_unregister(pmu);
795 cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
796 }
797
pmu_sbi_device_probe(struct platform_device * pdev)798 static int pmu_sbi_device_probe(struct platform_device *pdev)
799 {
800 struct riscv_pmu *pmu = NULL;
801 unsigned long cmask = 0;
802 int ret = -ENODEV;
803 int num_counters;
804
805 pr_info("SBI PMU extension is available\n");
806 pmu = riscv_pmu_alloc();
807 if (!pmu)
808 return -ENOMEM;
809
810 num_counters = pmu_sbi_find_num_ctrs();
811 if (num_counters < 0) {
812 pr_err("SBI PMU extension doesn't provide any counters\n");
813 goto out_free;
814 }
815
816 /* cache all the information about counters now */
817 if (pmu_sbi_get_ctrinfo(num_counters, &cmask))
818 goto out_free;
819
820 ret = pmu_sbi_setup_irqs(pmu, pdev);
821 if (ret < 0) {
822 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n");
823 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
824 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
825 }
826
827 pmu->pmu.attr_groups = riscv_pmu_attr_groups;
828 pmu->cmask = cmask;
829 pmu->ctr_start = pmu_sbi_ctr_start;
830 pmu->ctr_stop = pmu_sbi_ctr_stop;
831 pmu->event_map = pmu_sbi_event_map;
832 pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
833 pmu->ctr_get_width = pmu_sbi_ctr_get_width;
834 pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
835 pmu->ctr_read = pmu_sbi_ctr_read;
836
837 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
838 if (ret)
839 return ret;
840
841 ret = riscv_pm_pmu_register(pmu);
842 if (ret)
843 goto out_unregister;
844
845 ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
846 if (ret)
847 goto out_unregister;
848
849 return 0;
850
851 out_unregister:
852 riscv_pmu_destroy(pmu);
853
854 out_free:
855 kfree(pmu);
856 return ret;
857 }
858
859 static struct platform_driver pmu_sbi_driver = {
860 .probe = pmu_sbi_device_probe,
861 .driver = {
862 .name = RISCV_PMU_PDEV_NAME,
863 },
864 };
865
pmu_sbi_devinit(void)866 static int __init pmu_sbi_devinit(void)
867 {
868 int ret;
869 struct platform_device *pdev;
870
871 if (sbi_spec_version < sbi_mk_version(0, 3) ||
872 sbi_probe_extension(SBI_EXT_PMU) <= 0) {
873 return 0;
874 }
875
876 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING,
877 "perf/riscv/pmu:starting",
878 pmu_sbi_starting_cpu, pmu_sbi_dying_cpu);
879 if (ret) {
880 pr_err("CPU hotplug notifier could not be registered: %d\n",
881 ret);
882 return ret;
883 }
884
885 ret = platform_driver_register(&pmu_sbi_driver);
886 if (ret)
887 return ret;
888
889 pdev = platform_device_register_simple(RISCV_PMU_PDEV_NAME, -1, NULL, 0);
890 if (IS_ERR(pdev)) {
891 platform_driver_unregister(&pmu_sbi_driver);
892 return PTR_ERR(pdev);
893 }
894
895 /* Notify legacy implementation that SBI pmu is available*/
896 riscv_pmu_legacy_skip_init();
897
898 return ret;
899 }
900 device_initcall(pmu_sbi_devinit)
901
