1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Express Downstream Port Containment services driver
4 * Author: Keith Busch <keith.busch@intel.com>
5 *
6 * Copyright (C) 2016 Intel Corp.
7 */
8
9 #include <linux/aer.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14
15 #include "portdrv.h"
16 #include "../pci.h"
17
18 struct dpc_dev {
19 struct pcie_device *dev;
20 u16 cap_pos;
21 bool rp_extensions;
22 u8 rp_log_size;
23 };
24
25 static const char * const rp_pio_error_string[] = {
26 "Configuration Request received UR Completion", /* Bit Position 0 */
27 "Configuration Request received CA Completion", /* Bit Position 1 */
28 "Configuration Request Completion Timeout", /* Bit Position 2 */
29 NULL,
30 NULL,
31 NULL,
32 NULL,
33 NULL,
34 "I/O Request received UR Completion", /* Bit Position 8 */
35 "I/O Request received CA Completion", /* Bit Position 9 */
36 "I/O Request Completion Timeout", /* Bit Position 10 */
37 NULL,
38 NULL,
39 NULL,
40 NULL,
41 NULL,
42 "Memory Request received UR Completion", /* Bit Position 16 */
43 "Memory Request received CA Completion", /* Bit Position 17 */
44 "Memory Request Completion Timeout", /* Bit Position 18 */
45 };
46
dpc_wait_rp_inactive(struct dpc_dev * dpc)47 static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
48 {
49 unsigned long timeout = jiffies + HZ;
50 struct pci_dev *pdev = dpc->dev->port;
51 struct device *dev = &dpc->dev->device;
52 u16 cap = dpc->cap_pos, status;
53
54 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
55 while (status & PCI_EXP_DPC_RP_BUSY &&
56 !time_after(jiffies, timeout)) {
57 msleep(10);
58 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
59 }
60 if (status & PCI_EXP_DPC_RP_BUSY) {
61 dev_warn(dev, "DPC root port still busy\n");
62 return -EBUSY;
63 }
64 return 0;
65 }
66
dpc_reset_link(struct pci_dev * pdev)67 static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
68 {
69 struct dpc_dev *dpc;
70 struct pcie_device *pciedev;
71 struct device *devdpc;
72
73 u16 cap;
74
75 /*
76 * DPC disables the Link automatically in hardware, so it has
77 * already been reset by the time we get here.
78 */
79 devdpc = pcie_port_find_device(pdev, PCIE_PORT_SERVICE_DPC);
80 pciedev = to_pcie_device(devdpc);
81 dpc = get_service_data(pciedev);
82 cap = dpc->cap_pos;
83
84 /*
85 * Wait until the Link is inactive, then clear DPC Trigger Status
86 * to allow the Port to leave DPC.
87 */
88 pcie_wait_for_link(pdev, false);
89
90 if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
91 return PCI_ERS_RESULT_DISCONNECT;
92
93 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
94 PCI_EXP_DPC_STATUS_TRIGGER);
95
96 return PCI_ERS_RESULT_RECOVERED;
97 }
98
99
dpc_process_rp_pio_error(struct dpc_dev * dpc)100 static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
101 {
102 struct device *dev = &dpc->dev->device;
103 struct pci_dev *pdev = dpc->dev->port;
104 u16 cap = dpc->cap_pos, dpc_status, first_error;
105 u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
106 int i;
107
108 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
109 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
110 dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
111 status, mask);
112
113 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
114 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
115 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
116 dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
117 sev, syserr, exc);
118
119 /* Get First Error Pointer */
120 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
121 first_error = (dpc_status & 0x1f00) >> 8;
122
123 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
124 if ((status & ~mask) & (1 << i))
125 dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
126 first_error == i ? " (First)" : "");
127 }
128
129 if (dpc->rp_log_size < 4)
130 goto clear_status;
131 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
132 &dw0);
133 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
134 &dw1);
135 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
136 &dw2);
137 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
138 &dw3);
139 dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
140 dw0, dw1, dw2, dw3);
141
142 if (dpc->rp_log_size < 5)
143 goto clear_status;
144 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
145 dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
146
147 for (i = 0; i < dpc->rp_log_size - 5; i++) {
148 pci_read_config_dword(pdev,
149 cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
150 dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
151 }
152 clear_status:
153 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
154 }
155
dpc_handler(int irq,void * context)156 static irqreturn_t dpc_handler(int irq, void *context)
157 {
158 struct aer_err_info info;
159 struct dpc_dev *dpc = context;
160 struct pci_dev *pdev = dpc->dev->port;
161 struct device *dev = &dpc->dev->device;
162 u16 cap = dpc->cap_pos, status, source, reason, ext_reason;
163
164 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
165 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
166
167 dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
168 status, source);
169
170 reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
171 ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
172 dev_warn(dev, "DPC %s detected, remove downstream devices\n",
173 (reason == 0) ? "unmasked uncorrectable error" :
174 (reason == 1) ? "ERR_NONFATAL" :
175 (reason == 2) ? "ERR_FATAL" :
176 (ext_reason == 0) ? "RP PIO error" :
177 (ext_reason == 1) ? "software trigger" :
178 "reserved error");
179
180 /* show RP PIO error detail information */
181 if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
182 dpc_process_rp_pio_error(dpc);
183 else if (reason == 0 && aer_get_device_error_info(pdev, &info)) {
184 aer_print_error(pdev, &info);
185 pci_cleanup_aer_uncorrect_error_status(pdev);
186 }
187
188 /* We configure DPC so it only triggers on ERR_FATAL */
189 pcie_do_fatal_recovery(pdev, PCIE_PORT_SERVICE_DPC);
190
191 return IRQ_HANDLED;
192 }
193
dpc_irq(int irq,void * context)194 static irqreturn_t dpc_irq(int irq, void *context)
195 {
196 struct dpc_dev *dpc = (struct dpc_dev *)context;
197 struct pci_dev *pdev = dpc->dev->port;
198 u16 cap = dpc->cap_pos, status;
199
200 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
201
202 if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0))
203 return IRQ_NONE;
204
205 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
206 PCI_EXP_DPC_STATUS_INTERRUPT);
207 if (status & PCI_EXP_DPC_STATUS_TRIGGER)
208 return IRQ_WAKE_THREAD;
209 return IRQ_HANDLED;
210 }
211
212 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
dpc_probe(struct pcie_device * dev)213 static int dpc_probe(struct pcie_device *dev)
214 {
215 struct dpc_dev *dpc;
216 struct pci_dev *pdev = dev->port;
217 struct device *device = &dev->device;
218 int status;
219 u16 ctl, cap;
220
221 if (pcie_aer_get_firmware_first(pdev))
222 return -ENOTSUPP;
223
224 dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
225 if (!dpc)
226 return -ENOMEM;
227
228 dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
229 dpc->dev = dev;
230 set_service_data(dev, dpc);
231
232 status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
233 dpc_handler, IRQF_SHARED,
234 "pcie-dpc", dpc);
235 if (status) {
236 dev_warn(device, "request IRQ%d failed: %d\n", dev->irq,
237 status);
238 return status;
239 }
240
241 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
242 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
243
244 dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
245 if (dpc->rp_extensions) {
246 dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
247 if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
248 dev_err(device, "RP PIO log size %u is invalid\n",
249 dpc->rp_log_size);
250 dpc->rp_log_size = 0;
251 }
252 }
253
254 ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
255 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
256
257 dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
258 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
259 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
260 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
261 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
262 return status;
263 }
264
dpc_remove(struct pcie_device * dev)265 static void dpc_remove(struct pcie_device *dev)
266 {
267 struct dpc_dev *dpc = get_service_data(dev);
268 struct pci_dev *pdev = dev->port;
269 u16 ctl;
270
271 pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
272 ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
273 pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
274 }
275
276 static struct pcie_port_service_driver dpcdriver = {
277 .name = "dpc",
278 .port_type = PCIE_ANY_PORT,
279 .service = PCIE_PORT_SERVICE_DPC,
280 .probe = dpc_probe,
281 .remove = dpc_remove,
282 .reset_link = dpc_reset_link,
283 };
284
dpc_service_init(void)285 static int __init dpc_service_init(void)
286 {
287 return pcie_port_service_register(&dpcdriver);
288 }
289 device_initcall(dpc_service_init);
290
