1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Mobiveil PCIe Host controller
4 *
5 * Copyright (c) 2018 Mobiveil Inc.
6 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/msi.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25
26 #include "../pci.h"
27
28 /* register offsets and bit positions */
29
30 /*
31 * translation tables are grouped into windows, each window registers are
32 * grouped into blocks of 4 or 16 registers each
33 */
34 #define PAB_REG_BLOCK_SIZE 16
35 #define PAB_EXT_REG_BLOCK_SIZE 4
36
37 #define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
38 #define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
39
40 #define LTSSM_STATUS 0x0404
41 #define LTSSM_STATUS_L0_MASK 0x3f
42 #define LTSSM_STATUS_L0 0x2d
43
44 #define PAB_CTRL 0x0808
45 #define AMBA_PIO_ENABLE_SHIFT 0
46 #define PEX_PIO_ENABLE_SHIFT 1
47 #define PAGE_SEL_SHIFT 13
48 #define PAGE_SEL_MASK 0x3f
49 #define PAGE_LO_MASK 0x3ff
50 #define PAGE_SEL_EN 0xc00
51 #define PAGE_SEL_OFFSET_SHIFT 10
52
53 #define PAB_AXI_PIO_CTRL 0x0840
54 #define APIO_EN_MASK 0xf
55
56 #define PAB_PEX_PIO_CTRL 0x08c0
57 #define PIO_ENABLE_SHIFT 0
58
59 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
60 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
61 #define PAB_INTP_INTX_MASK 0x01e0
62 #define PAB_INTP_MSI_MASK 0x8
63
64 #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
65 #define WIN_ENABLE_SHIFT 0
66 #define WIN_TYPE_SHIFT 1
67
68 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
69
70 #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
71 #define AXI_WINDOW_ALIGN_MASK 3
72
73 #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
74 #define PAB_BUS_SHIFT 24
75 #define PAB_DEVICE_SHIFT 19
76 #define PAB_FUNCTION_SHIFT 16
77
78 #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
79 #define PAB_INTP_AXI_PIO_CLASS 0x474
80
81 #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
82 #define AMAP_CTRL_EN_SHIFT 0
83 #define AMAP_CTRL_TYPE_SHIFT 1
84
85 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
86 #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
87 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
88 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
89
90 /* starting offset of INTX bits in status register */
91 #define PAB_INTX_START 5
92
93 /* supported number of MSI interrupts */
94 #define PCI_NUM_MSI 16
95
96 /* MSI registers */
97 #define MSI_BASE_LO_OFFSET 0x04
98 #define MSI_BASE_HI_OFFSET 0x08
99 #define MSI_SIZE_OFFSET 0x0c
100 #define MSI_ENABLE_OFFSET 0x14
101 #define MSI_STATUS_OFFSET 0x18
102 #define MSI_DATA_OFFSET 0x20
103 #define MSI_ADDR_L_OFFSET 0x24
104 #define MSI_ADDR_H_OFFSET 0x28
105
106 /* outbound and inbound window definitions */
107 #define WIN_NUM_0 0
108 #define WIN_NUM_1 1
109 #define CFG_WINDOW_TYPE 0
110 #define IO_WINDOW_TYPE 1
111 #define MEM_WINDOW_TYPE 2
112 #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
113 #define MAX_PIO_WINDOWS 8
114
115 /* Parameters for the waiting for link up routine */
116 #define LINK_WAIT_MAX_RETRIES 10
117 #define LINK_WAIT_MIN 90000
118 #define LINK_WAIT_MAX 100000
119
120 struct mobiveil_msi { /* MSI information */
121 struct mutex lock; /* protect bitmap variable */
122 struct irq_domain *msi_domain;
123 struct irq_domain *dev_domain;
124 phys_addr_t msi_pages_phys;
125 int num_of_vectors;
126 DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
127 };
128
129 struct mobiveil_pcie {
130 struct platform_device *pdev;
131 struct list_head resources;
132 void __iomem *config_axi_slave_base; /* endpoint config base */
133 void __iomem *csr_axi_slave_base; /* root port config base */
134 void __iomem *apb_csr_base; /* MSI register base */
135 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
136 struct irq_domain *intx_domain;
137 raw_spinlock_t intx_mask_lock;
138 int irq;
139 int apio_wins;
140 int ppio_wins;
141 int ob_wins_configured; /* configured outbound windows */
142 int ib_wins_configured; /* configured inbound windows */
143 struct resource *ob_io_res;
144 char root_bus_nr;
145 struct mobiveil_msi msi;
146 };
147
csr_writel(struct mobiveil_pcie * pcie,const u32 value,const u32 reg)148 static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
149 const u32 reg)
150 {
151 writel_relaxed(value, pcie->csr_axi_slave_base + reg);
152 }
153
csr_readl(struct mobiveil_pcie * pcie,const u32 reg)154 static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
155 {
156 return readl_relaxed(pcie->csr_axi_slave_base + reg);
157 }
158
mobiveil_pcie_link_up(struct mobiveil_pcie * pcie)159 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
160 {
161 return (csr_readl(pcie, LTSSM_STATUS) &
162 LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
163 }
164
mobiveil_pcie_valid_device(struct pci_bus * bus,unsigned int devfn)165 static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
166 {
167 struct mobiveil_pcie *pcie = bus->sysdata;
168
169 /* Only one device down on each root port */
170 if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
171 return false;
172
173 /*
174 * Do not read more than one device on the bus directly
175 * attached to RC
176 */
177 if ((bus->primary == pcie->root_bus_nr) && (devfn > 0))
178 return false;
179
180 return true;
181 }
182
183 /*
184 * mobiveil_pcie_map_bus - routine to get the configuration base of either
185 * root port or endpoint
186 */
mobiveil_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)187 static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
188 unsigned int devfn, int where)
189 {
190 struct mobiveil_pcie *pcie = bus->sysdata;
191
192 if (!mobiveil_pcie_valid_device(bus, devfn))
193 return NULL;
194
195 if (bus->number == pcie->root_bus_nr) {
196 /* RC config access */
197 return pcie->csr_axi_slave_base + where;
198 }
199
200 /*
201 * EP config access (in Config/APIO space)
202 * Program PEX Address base (31..16 bits) with appropriate value
203 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
204 * Relies on pci_lock serialization
205 */
206 csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
207 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
208 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
209 PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
210 return pcie->config_axi_slave_base + where;
211 }
212
213 static struct pci_ops mobiveil_pcie_ops = {
214 .map_bus = mobiveil_pcie_map_bus,
215 .read = pci_generic_config_read,
216 .write = pci_generic_config_write,
217 };
218
mobiveil_pcie_isr(struct irq_desc * desc)219 static void mobiveil_pcie_isr(struct irq_desc *desc)
220 {
221 struct irq_chip *chip = irq_desc_get_chip(desc);
222 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
223 struct device *dev = &pcie->pdev->dev;
224 struct mobiveil_msi *msi = &pcie->msi;
225 u32 msi_data, msi_addr_lo, msi_addr_hi;
226 u32 intr_status, msi_status;
227 unsigned long shifted_status;
228 u32 bit, virq, val, mask;
229
230 /*
231 * The core provides a single interrupt for both INTx/MSI messages.
232 * So we'll read both INTx and MSI status
233 */
234
235 chained_irq_enter(chip, desc);
236
237 /* read INTx status */
238 val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
239 mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
240 intr_status = val & mask;
241
242 /* Handle INTx */
243 if (intr_status & PAB_INTP_INTX_MASK) {
244 shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
245 PAB_INTX_START;
246 do {
247 for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
248 virq = irq_find_mapping(pcie->intx_domain,
249 bit + 1);
250 if (virq)
251 generic_handle_irq(virq);
252 else
253 dev_err_ratelimited(dev,
254 "unexpected IRQ, INT%d\n", bit);
255
256 /* clear interrupt */
257 csr_writel(pcie,
258 shifted_status << PAB_INTX_START,
259 PAB_INTP_AMBA_MISC_STAT);
260 }
261 } while ((shifted_status >> PAB_INTX_START) != 0);
262 }
263
264 /* read extra MSI status register */
265 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
266
267 /* handle MSI interrupts */
268 while (msi_status & 1) {
269 msi_data = readl_relaxed(pcie->apb_csr_base
270 + MSI_DATA_OFFSET);
271
272 /*
273 * MSI_STATUS_OFFSET register gets updated to zero
274 * once we pop not only the MSI data but also address
275 * from MSI hardware FIFO. So keeping these following
276 * two dummy reads.
277 */
278 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
279 MSI_ADDR_L_OFFSET);
280 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
281 MSI_ADDR_H_OFFSET);
282 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
283 msi_data, msi_addr_hi, msi_addr_lo);
284
285 virq = irq_find_mapping(msi->dev_domain, msi_data);
286 if (virq)
287 generic_handle_irq(virq);
288
289 msi_status = readl_relaxed(pcie->apb_csr_base +
290 MSI_STATUS_OFFSET);
291 }
292
293 /* Clear the interrupt status */
294 csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
295 chained_irq_exit(chip, desc);
296 }
297
mobiveil_pcie_parse_dt(struct mobiveil_pcie * pcie)298 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
299 {
300 struct device *dev = &pcie->pdev->dev;
301 struct platform_device *pdev = pcie->pdev;
302 struct device_node *node = dev->of_node;
303 struct resource *res;
304 const char *type;
305
306 type = of_get_property(node, "device_type", NULL);
307 if (!type || strcmp(type, "pci")) {
308 dev_err(dev, "invalid \"device_type\" %s\n", type);
309 return -EINVAL;
310 }
311
312 /* map config resource */
313 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
314 "config_axi_slave");
315 pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
316 if (IS_ERR(pcie->config_axi_slave_base))
317 return PTR_ERR(pcie->config_axi_slave_base);
318 pcie->ob_io_res = res;
319
320 /* map csr resource */
321 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
322 "csr_axi_slave");
323 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
324 if (IS_ERR(pcie->csr_axi_slave_base))
325 return PTR_ERR(pcie->csr_axi_slave_base);
326 pcie->pcie_reg_base = res->start;
327
328 /* map MSI config resource */
329 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
330 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
331 if (IS_ERR(pcie->apb_csr_base))
332 return PTR_ERR(pcie->apb_csr_base);
333
334 /* read the number of windows requested */
335 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
336 pcie->apio_wins = MAX_PIO_WINDOWS;
337
338 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
339 pcie->ppio_wins = MAX_PIO_WINDOWS;
340
341 pcie->irq = platform_get_irq(pdev, 0);
342 if (pcie->irq <= 0) {
343 dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
344 return -ENODEV;
345 }
346
347 irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
348
349 return 0;
350 }
351
352 /*
353 * select_paged_register - routine to access paged register of root complex
354 *
355 * registers of RC are paged, for this scheme to work
356 * extracted higher 6 bits of the offset will be written to pg_sel
357 * field of PAB_CTRL register and rest of the lower 10 bits enabled with
358 * PAGE_SEL_EN are used as offset of the register.
359 */
select_paged_register(struct mobiveil_pcie * pcie,u32 offset)360 static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)
361 {
362 int pab_ctrl_dw, pg_sel;
363
364 /* clear pg_sel field */
365 pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);
366 pab_ctrl_dw = (pab_ctrl_dw & ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT));
367
368 /* set pg_sel field */
369 pg_sel = (offset >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK;
370 pab_ctrl_dw |= ((pg_sel << PAGE_SEL_SHIFT));
371 csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);
372 }
373
write_paged_register(struct mobiveil_pcie * pcie,u32 val,u32 offset)374 static void write_paged_register(struct mobiveil_pcie *pcie,
375 u32 val, u32 offset)
376 {
377 u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
378
379 select_paged_register(pcie, offset);
380 csr_writel(pcie, val, off);
381 }
382
read_paged_register(struct mobiveil_pcie * pcie,u32 offset)383 static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)
384 {
385 u32 off = (offset & PAGE_LO_MASK) | PAGE_SEL_EN;
386
387 select_paged_register(pcie, offset);
388 return csr_readl(pcie, off);
389 }
390
program_ib_windows(struct mobiveil_pcie * pcie,int win_num,int pci_addr,u32 type,u64 size)391 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
392 int pci_addr, u32 type, u64 size)
393 {
394 int pio_ctrl_val;
395 int amap_ctrl_dw;
396 u64 size64 = ~(size - 1);
397
398 if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
399 dev_err(&pcie->pdev->dev,
400 "ERROR: max inbound windows reached !\n");
401 return;
402 }
403
404 pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
405 csr_writel(pcie,
406 pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
407 amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));
408 amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
409 amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
410
411 write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),
412 PAB_PEX_AMAP_CTRL(win_num));
413
414 write_paged_register(pcie, upper_32_bits(size64),
415 PAB_EXT_PEX_AMAP_SIZEN(win_num));
416
417 write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
418 write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));
419 write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
420 }
421
422 /*
423 * routine to program the outbound windows
424 */
program_ob_windows(struct mobiveil_pcie * pcie,int win_num,u64 cpu_addr,u64 pci_addr,u32 config_io_bit,u64 size)425 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
426 u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
427 {
428
429 u32 value, type;
430 u64 size64 = ~(size - 1);
431
432 if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
433 dev_err(&pcie->pdev->dev,
434 "ERROR: max outbound windows reached !\n");
435 return;
436 }
437
438 /*
439 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
440 * to 4 KB in PAB_AXI_AMAP_CTRL register
441 */
442 type = config_io_bit;
443 value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
444 csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
445 lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
446
447 write_paged_register(pcie, upper_32_bits(size64),
448 PAB_EXT_AXI_AMAP_SIZE(win_num));
449
450 /*
451 * program AXI window base with appropriate value in
452 * PAB_AXI_AMAP_AXI_WIN0 register
453 */
454 value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
455 csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
456 PAB_AXI_AMAP_AXI_WIN(win_num));
457
458 value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
459
460 csr_writel(pcie, lower_32_bits(pci_addr),
461 PAB_AXI_AMAP_PEX_WIN_L(win_num));
462 csr_writel(pcie, upper_32_bits(pci_addr),
463 PAB_AXI_AMAP_PEX_WIN_H(win_num));
464
465 pcie->ob_wins_configured++;
466 }
467
mobiveil_bringup_link(struct mobiveil_pcie * pcie)468 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
469 {
470 int retries;
471
472 /* check if the link is up or not */
473 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
474 if (mobiveil_pcie_link_up(pcie))
475 return 0;
476
477 usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
478 }
479 dev_err(&pcie->pdev->dev, "link never came up\n");
480 return -ETIMEDOUT;
481 }
482
mobiveil_pcie_enable_msi(struct mobiveil_pcie * pcie)483 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
484 {
485 phys_addr_t msg_addr = pcie->pcie_reg_base;
486 struct mobiveil_msi *msi = &pcie->msi;
487
488 pcie->msi.num_of_vectors = PCI_NUM_MSI;
489 msi->msi_pages_phys = (phys_addr_t)msg_addr;
490
491 writel_relaxed(lower_32_bits(msg_addr),
492 pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
493 writel_relaxed(upper_32_bits(msg_addr),
494 pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
495 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
496 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
497 }
498
mobiveil_host_init(struct mobiveil_pcie * pcie)499 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
500 {
501 u32 value, pab_ctrl, type = 0;
502 int err;
503 struct resource_entry *win, *tmp;
504
505 err = mobiveil_bringup_link(pcie);
506 if (err) {
507 dev_info(&pcie->pdev->dev, "link bring-up failed\n");
508 return err;
509 }
510
511 /*
512 * program Bus Master Enable Bit in Command Register in PAB Config
513 * Space
514 */
515 value = csr_readl(pcie, PCI_COMMAND);
516 csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
517 PCI_COMMAND_MASTER, PCI_COMMAND);
518
519 /*
520 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
521 * register
522 */
523 pab_ctrl = csr_readl(pcie, PAB_CTRL);
524 csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
525 (1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
526
527 csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
528 PAB_INTP_AMBA_MISC_ENB);
529
530 /*
531 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
532 * PAB_AXI_PIO_CTRL Register
533 */
534 value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
535 csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);
536
537 /*
538 * we'll program one outbound window for config reads and
539 * another default inbound window for all the upstream traffic
540 * rest of the outbound windows will be configured according to
541 * the "ranges" field defined in device tree
542 */
543
544 /* config outbound translation window */
545 program_ob_windows(pcie, pcie->ob_wins_configured,
546 pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,
547 resource_size(pcie->ob_io_res));
548
549 /* memory inbound translation window */
550 program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
551
552 /* Get the I/O and memory ranges from DT */
553 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
554 type = 0;
555 if (resource_type(win->res) == IORESOURCE_MEM)
556 type = MEM_WINDOW_TYPE;
557 if (resource_type(win->res) == IORESOURCE_IO)
558 type = IO_WINDOW_TYPE;
559 if (type) {
560 /* configure outbound translation window */
561 program_ob_windows(pcie, pcie->ob_wins_configured,
562 win->res->start, 0, type,
563 resource_size(win->res));
564 }
565 }
566
567 /* setup MSI hardware registers */
568 mobiveil_pcie_enable_msi(pcie);
569
570 return err;
571 }
572
mobiveil_mask_intx_irq(struct irq_data * data)573 static void mobiveil_mask_intx_irq(struct irq_data *data)
574 {
575 struct irq_desc *desc = irq_to_desc(data->irq);
576 struct mobiveil_pcie *pcie;
577 unsigned long flags;
578 u32 mask, shifted_val;
579
580 pcie = irq_desc_get_chip_data(desc);
581 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
582 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
583 shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
584 csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);
585 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
586 }
587
mobiveil_unmask_intx_irq(struct irq_data * data)588 static void mobiveil_unmask_intx_irq(struct irq_data *data)
589 {
590 struct irq_desc *desc = irq_to_desc(data->irq);
591 struct mobiveil_pcie *pcie;
592 unsigned long flags;
593 u32 shifted_val, mask;
594
595 pcie = irq_desc_get_chip_data(desc);
596 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
597 raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
598 shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
599 csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);
600 raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
601 }
602
603 static struct irq_chip intx_irq_chip = {
604 .name = "mobiveil_pcie:intx",
605 .irq_enable = mobiveil_unmask_intx_irq,
606 .irq_disable = mobiveil_mask_intx_irq,
607 .irq_mask = mobiveil_mask_intx_irq,
608 .irq_unmask = mobiveil_unmask_intx_irq,
609 };
610
611 /* routine to setup the INTx related data */
mobiveil_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)612 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
613 irq_hw_number_t hwirq)
614 {
615 irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
616 irq_set_chip_data(irq, domain->host_data);
617 return 0;
618 }
619
620 /* INTx domain operations structure */
621 static const struct irq_domain_ops intx_domain_ops = {
622 .map = mobiveil_pcie_intx_map,
623 };
624
625 static struct irq_chip mobiveil_msi_irq_chip = {
626 .name = "Mobiveil PCIe MSI",
627 .irq_mask = pci_msi_mask_irq,
628 .irq_unmask = pci_msi_unmask_irq,
629 };
630
631 static struct msi_domain_info mobiveil_msi_domain_info = {
632 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
633 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
634 .chip = &mobiveil_msi_irq_chip,
635 };
636
mobiveil_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)637 static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
638 {
639 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
640 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
641
642 msg->address_lo = lower_32_bits(addr);
643 msg->address_hi = upper_32_bits(addr);
644 msg->data = data->hwirq;
645
646 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
647 (int)data->hwirq, msg->address_hi, msg->address_lo);
648 }
649
mobiveil_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)650 static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
651 const struct cpumask *mask, bool force)
652 {
653 return -EINVAL;
654 }
655
656 static struct irq_chip mobiveil_msi_bottom_irq_chip = {
657 .name = "Mobiveil MSI",
658 .irq_compose_msi_msg = mobiveil_compose_msi_msg,
659 .irq_set_affinity = mobiveil_msi_set_affinity,
660 };
661
mobiveil_irq_msi_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)662 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
663 unsigned int virq, unsigned int nr_irqs, void *args)
664 {
665 struct mobiveil_pcie *pcie = domain->host_data;
666 struct mobiveil_msi *msi = &pcie->msi;
667 unsigned long bit;
668
669 WARN_ON(nr_irqs != 1);
670 mutex_lock(&msi->lock);
671
672 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
673 if (bit >= msi->num_of_vectors) {
674 mutex_unlock(&msi->lock);
675 return -ENOSPC;
676 }
677
678 set_bit(bit, msi->msi_irq_in_use);
679
680 mutex_unlock(&msi->lock);
681
682 irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
683 domain->host_data, handle_level_irq,
684 NULL, NULL);
685 return 0;
686 }
687
mobiveil_irq_msi_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)688 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
689 unsigned int virq, unsigned int nr_irqs)
690 {
691 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
692 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
693 struct mobiveil_msi *msi = &pcie->msi;
694
695 mutex_lock(&msi->lock);
696
697 if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
698 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
699 d->hwirq);
700 } else {
701 __clear_bit(d->hwirq, msi->msi_irq_in_use);
702 }
703
704 mutex_unlock(&msi->lock);
705 }
706 static const struct irq_domain_ops msi_domain_ops = {
707 .alloc = mobiveil_irq_msi_domain_alloc,
708 .free = mobiveil_irq_msi_domain_free,
709 };
710
mobiveil_allocate_msi_domains(struct mobiveil_pcie * pcie)711 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
712 {
713 struct device *dev = &pcie->pdev->dev;
714 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
715 struct mobiveil_msi *msi = &pcie->msi;
716
717 mutex_init(&pcie->msi.lock);
718 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
719 &msi_domain_ops, pcie);
720 if (!msi->dev_domain) {
721 dev_err(dev, "failed to create IRQ domain\n");
722 return -ENOMEM;
723 }
724
725 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
726 &mobiveil_msi_domain_info, msi->dev_domain);
727 if (!msi->msi_domain) {
728 dev_err(dev, "failed to create MSI domain\n");
729 irq_domain_remove(msi->dev_domain);
730 return -ENOMEM;
731 }
732 return 0;
733 }
734
mobiveil_pcie_init_irq_domain(struct mobiveil_pcie * pcie)735 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
736 {
737 struct device *dev = &pcie->pdev->dev;
738 struct device_node *node = dev->of_node;
739 int ret;
740
741 /* setup INTx */
742 pcie->intx_domain = irq_domain_add_linear(node,
743 PCI_NUM_INTX, &intx_domain_ops, pcie);
744
745 if (!pcie->intx_domain) {
746 dev_err(dev, "Failed to get a INTx IRQ domain\n");
747 return -ENODEV;
748 }
749
750 raw_spin_lock_init(&pcie->intx_mask_lock);
751
752 /* setup MSI */
753 ret = mobiveil_allocate_msi_domains(pcie);
754 if (ret)
755 return ret;
756
757 return 0;
758 }
759
mobiveil_pcie_probe(struct platform_device * pdev)760 static int mobiveil_pcie_probe(struct platform_device *pdev)
761 {
762 struct mobiveil_pcie *pcie;
763 struct pci_bus *bus;
764 struct pci_bus *child;
765 struct pci_host_bridge *bridge;
766 struct device *dev = &pdev->dev;
767 resource_size_t iobase;
768 int ret;
769
770 /* allocate the PCIe port */
771 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
772 if (!bridge)
773 return -ENODEV;
774
775 pcie = pci_host_bridge_priv(bridge);
776 if (!pcie)
777 return -ENOMEM;
778
779 pcie->pdev = pdev;
780
781 ret = mobiveil_pcie_parse_dt(pcie);
782 if (ret) {
783 dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
784 return ret;
785 }
786
787 INIT_LIST_HEAD(&pcie->resources);
788
789 /* parse the host bridge base addresses from the device tree file */
790 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
791 &pcie->resources, &iobase);
792 if (ret) {
793 dev_err(dev, "Getting bridge resources failed\n");
794 return -ENOMEM;
795 }
796
797 /*
798 * configure all inbound and outbound windows and prepare the RC for
799 * config access
800 */
801 ret = mobiveil_host_init(pcie);
802 if (ret) {
803 dev_err(dev, "Failed to initialize host\n");
804 goto error;
805 }
806
807 /* fixup for PCIe class register */
808 csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
809
810 /* initialize the IRQ domains */
811 ret = mobiveil_pcie_init_irq_domain(pcie);
812 if (ret) {
813 dev_err(dev, "Failed creating IRQ Domain\n");
814 goto error;
815 }
816
817 ret = devm_request_pci_bus_resources(dev, &pcie->resources);
818 if (ret)
819 goto error;
820
821 /* Initialize bridge */
822 list_splice_init(&pcie->resources, &bridge->windows);
823 bridge->dev.parent = dev;
824 bridge->sysdata = pcie;
825 bridge->busnr = pcie->root_bus_nr;
826 bridge->ops = &mobiveil_pcie_ops;
827 bridge->map_irq = of_irq_parse_and_map_pci;
828 bridge->swizzle_irq = pci_common_swizzle;
829
830 /* setup the kernel resources for the newly added PCIe root bus */
831 ret = pci_scan_root_bus_bridge(bridge);
832 if (ret)
833 goto error;
834
835 bus = bridge->bus;
836
837 pci_assign_unassigned_bus_resources(bus);
838 list_for_each_entry(child, &bus->children, node)
839 pcie_bus_configure_settings(child);
840 pci_bus_add_devices(bus);
841
842 return 0;
843 error:
844 pci_free_resource_list(&pcie->resources);
845 return ret;
846 }
847
848 static const struct of_device_id mobiveil_pcie_of_match[] = {
849 {.compatible = "mbvl,gpex40-pcie",},
850 {},
851 };
852
853 MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
854
855 static struct platform_driver mobiveil_pcie_driver = {
856 .probe = mobiveil_pcie_probe,
857 .driver = {
858 .name = "mobiveil-pcie",
859 .of_match_table = mobiveil_pcie_of_match,
860 .suppress_bind_attrs = true,
861 },
862 };
863
864 builtin_platform_driver(mobiveil_pcie_driver);
865
866 MODULE_LICENSE("GPL v2");
867 MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
868 MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
869
