1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
3
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
6 #include <linux/clk.h>
7 #include <linux/compiler.h>
8 #include <linux/delay.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/log2.h>
18 #include <linux/module.h>
19 #include <linux/msi.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24 #include <linux/pci.h>
25 #include <linux/pci-ecam.h>
26 #include <linux/printk.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/sizes.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/types.h>
33
34 #include "../pci.h"
35
36 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
37 #define BRCM_PCIE_CAP_REGS 0x00ac
38
39 /* Broadcom STB PCIe Register Offsets */
40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
42 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
43
44 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
45 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
46
47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
49
50 #define PCIE_RC_DL_MDIO_ADDR 0x1100
51 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
52 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
53
54 #define PCIE_MISC_MISC_CTRL 0x4008
55 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
56 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
57 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
58
59 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
60 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
61 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
62 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
63
64 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
65 #define PCIE_MEM_WIN0_LO(win) \
66 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
67
68 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
69 #define PCIE_MEM_WIN0_HI(win) \
70 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
71
72 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
73 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
74
75 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
76 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
77 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
78
79 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
80 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
81
82 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
83 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
84
85 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
86 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
87 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
88
89 #define PCIE_MISC_PCIE_CTRL 0x4064
90 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
91 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
92
93 #define PCIE_MISC_PCIE_STATUS 0x4068
94 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
95 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
96 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
97 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
98
99 #define PCIE_MISC_REVISION 0x406c
100 #define BRCM_PCIE_HW_REV_33 0x0303
101 #define BRCM_PCIE_HW_REV_3_20 0x0320
102
103 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
105 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
106 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
107 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
108
109 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
110 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
111 #define PCIE_MEM_WIN0_BASE_HI(win) \
112 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
113
114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
115 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
116 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
117 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
118
119 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
120 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
121 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
122 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
123
124
125 #define PCIE_INTR2_CPU_BASE 0x4300
126 #define PCIE_MSI_INTR2_BASE 0x4500
127 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
128 #define MSI_INT_STATUS 0x0
129 #define MSI_INT_CLR 0x8
130 #define MSI_INT_MASK_SET 0x10
131 #define MSI_INT_MASK_CLR 0x14
132
133 #define PCIE_EXT_CFG_DATA 0x8000
134 #define PCIE_EXT_CFG_INDEX 0x9000
135
136 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
137 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
138
139 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
140 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
141 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
142 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
143
144 /* PCIe parameters */
145 #define BRCM_NUM_PCIE_OUT_WINS 0x4
146 #define BRCM_INT_PCI_MSI_NR 32
147 #define BRCM_INT_PCI_MSI_LEGACY_NR 8
148 #define BRCM_INT_PCI_MSI_SHIFT 0
149 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
150 #define BRCM_INT_PCI_MSI_LEGACY_MASK GENMASK(31, \
151 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
152
153 /* MSI target addresses */
154 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
155 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
156
157 /* MDIO registers */
158 #define MDIO_PORT0 0x0
159 #define MDIO_DATA_MASK 0x7fffffff
160 #define MDIO_PORT_MASK 0xf0000
161 #define MDIO_REGAD_MASK 0xffff
162 #define MDIO_CMD_MASK 0xfff00000
163 #define MDIO_CMD_READ 0x1
164 #define MDIO_CMD_WRITE 0x0
165 #define MDIO_DATA_DONE_MASK 0x80000000
166 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
167 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
168 #define SSC_REGS_ADDR 0x1100
169 #define SET_ADDR_OFFSET 0x1f
170 #define SSC_CNTL_OFFSET 0x2
171 #define SSC_CNTL_OVRD_EN_MASK 0x8000
172 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
173 #define SSC_STATUS_OFFSET 0x1
174 #define SSC_STATUS_SSC_MASK 0x400
175 #define SSC_STATUS_PLL_LOCK_MASK 0x800
176 #define PCIE_BRCM_MAX_MEMC 3
177
178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
181
182 /* Rescal registers */
183 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
184 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
185 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
186 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
187 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
188 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
189 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
190 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
191
192 /* Forward declarations */
193 struct brcm_pcie;
194
195 enum {
196 RGR1_SW_INIT_1,
197 EXT_CFG_INDEX,
198 EXT_CFG_DATA,
199 };
200
201 enum {
202 RGR1_SW_INIT_1_INIT_MASK,
203 RGR1_SW_INIT_1_INIT_SHIFT,
204 };
205
206 enum pcie_type {
207 GENERIC,
208 BCM7425,
209 BCM7435,
210 BCM4908,
211 BCM7278,
212 BCM2711,
213 };
214
215 struct pcie_cfg_data {
216 const int *offsets;
217 const enum pcie_type type;
218 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
219 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
220 };
221
222 struct subdev_regulators {
223 unsigned int num_supplies;
224 struct regulator_bulk_data supplies[];
225 };
226
227 struct brcm_msi {
228 struct device *dev;
229 void __iomem *base;
230 struct device_node *np;
231 struct irq_domain *msi_domain;
232 struct irq_domain *inner_domain;
233 struct mutex lock; /* guards the alloc/free operations */
234 u64 target_addr;
235 int irq;
236 DECLARE_BITMAP(used, BRCM_INT_PCI_MSI_NR);
237 bool legacy;
238 /* Some chips have MSIs in bits [31..24] of a shared register. */
239 int legacy_shift;
240 int nr; /* No. of MSI available, depends on chip */
241 /* This is the base pointer for interrupt status/set/clr regs */
242 void __iomem *intr_base;
243 };
244
245 /* Internal PCIe Host Controller Information.*/
246 struct brcm_pcie {
247 struct device *dev;
248 void __iomem *base;
249 struct clk *clk;
250 struct device_node *np;
251 bool ssc;
252 int gen;
253 u64 msi_target_addr;
254 struct brcm_msi *msi;
255 const int *reg_offsets;
256 enum pcie_type type;
257 struct reset_control *rescal;
258 struct reset_control *perst_reset;
259 int num_memc;
260 u64 memc_size[PCIE_BRCM_MAX_MEMC];
261 u32 hw_rev;
262 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
263 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
264 struct subdev_regulators *sr;
265 bool ep_wakeup_capable;
266 };
267
is_bmips(const struct brcm_pcie * pcie)268 static inline bool is_bmips(const struct brcm_pcie *pcie)
269 {
270 return pcie->type == BCM7435 || pcie->type == BCM7425;
271 }
272
273 /*
274 * This is to convert the size of the inbound "BAR" region to the
275 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
276 */
brcm_pcie_encode_ibar_size(u64 size)277 static int brcm_pcie_encode_ibar_size(u64 size)
278 {
279 int log2_in = ilog2(size);
280
281 if (log2_in >= 12 && log2_in <= 15)
282 /* Covers 4KB to 32KB (inclusive) */
283 return (log2_in - 12) + 0x1c;
284 else if (log2_in >= 16 && log2_in <= 35)
285 /* Covers 64KB to 32GB, (inclusive) */
286 return log2_in - 15;
287 /* Something is awry so disable */
288 return 0;
289 }
290
brcm_pcie_mdio_form_pkt(int port,int regad,int cmd)291 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
292 {
293 u32 pkt = 0;
294
295 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
296 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
297 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
298
299 return pkt;
300 }
301
302 /* negative return value indicates error */
brcm_pcie_mdio_read(void __iomem * base,u8 port,u8 regad,u32 * val)303 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
304 {
305 int tries;
306 u32 data;
307
308 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
309 base + PCIE_RC_DL_MDIO_ADDR);
310 readl(base + PCIE_RC_DL_MDIO_ADDR);
311
312 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
313 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
314 udelay(10);
315 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
316 }
317
318 *val = FIELD_GET(MDIO_DATA_MASK, data);
319 return MDIO_RD_DONE(data) ? 0 : -EIO;
320 }
321
322 /* negative return value indicates error */
brcm_pcie_mdio_write(void __iomem * base,u8 port,u8 regad,u16 wrdata)323 static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
324 u8 regad, u16 wrdata)
325 {
326 int tries;
327 u32 data;
328
329 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
330 base + PCIE_RC_DL_MDIO_ADDR);
331 readl(base + PCIE_RC_DL_MDIO_ADDR);
332 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
333
334 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
335 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
336 udelay(10);
337 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
338 }
339
340 return MDIO_WT_DONE(data) ? 0 : -EIO;
341 }
342
343 /*
344 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
345 * return value indicates error.
346 */
brcm_pcie_set_ssc(struct brcm_pcie * pcie)347 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
348 {
349 int pll, ssc;
350 int ret;
351 u32 tmp;
352
353 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
354 SSC_REGS_ADDR);
355 if (ret < 0)
356 return ret;
357
358 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
359 SSC_CNTL_OFFSET, &tmp);
360 if (ret < 0)
361 return ret;
362
363 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
364 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
365 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
366 SSC_CNTL_OFFSET, tmp);
367 if (ret < 0)
368 return ret;
369
370 usleep_range(1000, 2000);
371 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
372 SSC_STATUS_OFFSET, &tmp);
373 if (ret < 0)
374 return ret;
375
376 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
377 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
378
379 return ssc && pll ? 0 : -EIO;
380 }
381
382 /* Limits operation to a specific generation (1, 2, or 3) */
brcm_pcie_set_gen(struct brcm_pcie * pcie,int gen)383 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
384 {
385 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
386 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
387
388 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
389 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
390
391 lnkctl2 = (lnkctl2 & ~0xf) | gen;
392 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
393 }
394
brcm_pcie_set_outbound_win(struct brcm_pcie * pcie,unsigned int win,u64 cpu_addr,u64 pcie_addr,u64 size)395 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
396 unsigned int win, u64 cpu_addr,
397 u64 pcie_addr, u64 size)
398 {
399 u32 cpu_addr_mb_high, limit_addr_mb_high;
400 phys_addr_t cpu_addr_mb, limit_addr_mb;
401 int high_addr_shift;
402 u32 tmp;
403
404 /* Set the base of the pcie_addr window */
405 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
406 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
407
408 /* Write the addr base & limit lower bits (in MBs) */
409 cpu_addr_mb = cpu_addr / SZ_1M;
410 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
411
412 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
413 u32p_replace_bits(&tmp, cpu_addr_mb,
414 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
415 u32p_replace_bits(&tmp, limit_addr_mb,
416 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
417 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
418
419 if (is_bmips(pcie))
420 return;
421
422 /* Write the cpu & limit addr upper bits */
423 high_addr_shift =
424 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
425
426 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
427 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
428 u32p_replace_bits(&tmp, cpu_addr_mb_high,
429 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
430 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
431
432 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
433 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
434 u32p_replace_bits(&tmp, limit_addr_mb_high,
435 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
437 }
438
439 static struct irq_chip brcm_msi_irq_chip = {
440 .name = "BRCM STB PCIe MSI",
441 .irq_ack = irq_chip_ack_parent,
442 .irq_mask = pci_msi_mask_irq,
443 .irq_unmask = pci_msi_unmask_irq,
444 };
445
446 static struct msi_domain_info brcm_msi_domain_info = {
447 /* Multi MSI is supported by the controller, but not by this driver */
448 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
449 .chip = &brcm_msi_irq_chip,
450 };
451
brcm_pcie_msi_isr(struct irq_desc * desc)452 static void brcm_pcie_msi_isr(struct irq_desc *desc)
453 {
454 struct irq_chip *chip = irq_desc_get_chip(desc);
455 unsigned long status;
456 struct brcm_msi *msi;
457 struct device *dev;
458 u32 bit;
459
460 chained_irq_enter(chip, desc);
461 msi = irq_desc_get_handler_data(desc);
462 dev = msi->dev;
463
464 status = readl(msi->intr_base + MSI_INT_STATUS);
465 status >>= msi->legacy_shift;
466
467 for_each_set_bit(bit, &status, msi->nr) {
468 int ret;
469 ret = generic_handle_domain_irq(msi->inner_domain, bit);
470 if (ret)
471 dev_dbg(dev, "unexpected MSI\n");
472 }
473
474 chained_irq_exit(chip, desc);
475 }
476
brcm_msi_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)477 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
478 {
479 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
480
481 msg->address_lo = lower_32_bits(msi->target_addr);
482 msg->address_hi = upper_32_bits(msi->target_addr);
483 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
484 }
485
brcm_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)486 static int brcm_msi_set_affinity(struct irq_data *irq_data,
487 const struct cpumask *mask, bool force)
488 {
489 return -EINVAL;
490 }
491
brcm_msi_ack_irq(struct irq_data * data)492 static void brcm_msi_ack_irq(struct irq_data *data)
493 {
494 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
495 const int shift_amt = data->hwirq + msi->legacy_shift;
496
497 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
498 }
499
500
501 static struct irq_chip brcm_msi_bottom_irq_chip = {
502 .name = "BRCM STB MSI",
503 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
504 .irq_set_affinity = brcm_msi_set_affinity,
505 .irq_ack = brcm_msi_ack_irq,
506 };
507
brcm_msi_alloc(struct brcm_msi * msi)508 static int brcm_msi_alloc(struct brcm_msi *msi)
509 {
510 int hwirq;
511
512 mutex_lock(&msi->lock);
513 hwirq = bitmap_find_free_region(msi->used, msi->nr, 0);
514 mutex_unlock(&msi->lock);
515
516 return hwirq;
517 }
518
brcm_msi_free(struct brcm_msi * msi,unsigned long hwirq)519 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
520 {
521 mutex_lock(&msi->lock);
522 bitmap_release_region(msi->used, hwirq, 0);
523 mutex_unlock(&msi->lock);
524 }
525
brcm_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)526 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
527 unsigned int nr_irqs, void *args)
528 {
529 struct brcm_msi *msi = domain->host_data;
530 int hwirq;
531
532 hwirq = brcm_msi_alloc(msi);
533
534 if (hwirq < 0)
535 return hwirq;
536
537 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
538 &brcm_msi_bottom_irq_chip, domain->host_data,
539 handle_edge_irq, NULL, NULL);
540 return 0;
541 }
542
brcm_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)543 static void brcm_irq_domain_free(struct irq_domain *domain,
544 unsigned int virq, unsigned int nr_irqs)
545 {
546 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
547 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
548
549 brcm_msi_free(msi, d->hwirq);
550 }
551
552 static const struct irq_domain_ops msi_domain_ops = {
553 .alloc = brcm_irq_domain_alloc,
554 .free = brcm_irq_domain_free,
555 };
556
brcm_allocate_domains(struct brcm_msi * msi)557 static int brcm_allocate_domains(struct brcm_msi *msi)
558 {
559 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
560 struct device *dev = msi->dev;
561
562 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
563 if (!msi->inner_domain) {
564 dev_err(dev, "failed to create IRQ domain\n");
565 return -ENOMEM;
566 }
567
568 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
569 &brcm_msi_domain_info,
570 msi->inner_domain);
571 if (!msi->msi_domain) {
572 dev_err(dev, "failed to create MSI domain\n");
573 irq_domain_remove(msi->inner_domain);
574 return -ENOMEM;
575 }
576
577 return 0;
578 }
579
brcm_free_domains(struct brcm_msi * msi)580 static void brcm_free_domains(struct brcm_msi *msi)
581 {
582 irq_domain_remove(msi->msi_domain);
583 irq_domain_remove(msi->inner_domain);
584 }
585
brcm_msi_remove(struct brcm_pcie * pcie)586 static void brcm_msi_remove(struct brcm_pcie *pcie)
587 {
588 struct brcm_msi *msi = pcie->msi;
589
590 if (!msi)
591 return;
592 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
593 brcm_free_domains(msi);
594 }
595
brcm_msi_set_regs(struct brcm_msi * msi)596 static void brcm_msi_set_regs(struct brcm_msi *msi)
597 {
598 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK :
599 BRCM_INT_PCI_MSI_MASK;
600
601 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
602 writel(val, msi->intr_base + MSI_INT_CLR);
603
604 /*
605 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
606 * enable, which we set to 1.
607 */
608 writel(lower_32_bits(msi->target_addr) | 0x1,
609 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
610 writel(upper_32_bits(msi->target_addr),
611 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
612
613 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
614 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
615 }
616
brcm_pcie_enable_msi(struct brcm_pcie * pcie)617 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
618 {
619 struct brcm_msi *msi;
620 int irq, ret;
621 struct device *dev = pcie->dev;
622
623 irq = irq_of_parse_and_map(dev->of_node, 1);
624 if (irq <= 0) {
625 dev_err(dev, "cannot map MSI interrupt\n");
626 return -ENODEV;
627 }
628
629 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
630 if (!msi)
631 return -ENOMEM;
632
633 mutex_init(&msi->lock);
634 msi->dev = dev;
635 msi->base = pcie->base;
636 msi->np = pcie->np;
637 msi->target_addr = pcie->msi_target_addr;
638 msi->irq = irq;
639 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
640
641 /*
642 * Sanity check to make sure that the 'used' bitmap in struct brcm_msi
643 * is large enough.
644 */
645 BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR);
646
647 if (msi->legacy) {
648 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
649 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
650 msi->legacy_shift = 24;
651 } else {
652 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
653 msi->nr = BRCM_INT_PCI_MSI_NR;
654 msi->legacy_shift = 0;
655 }
656
657 ret = brcm_allocate_domains(msi);
658 if (ret)
659 return ret;
660
661 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
662
663 brcm_msi_set_regs(msi);
664 pcie->msi = msi;
665
666 return 0;
667 }
668
669 /* The controller is capable of serving in both RC and EP roles */
brcm_pcie_rc_mode(struct brcm_pcie * pcie)670 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
671 {
672 void __iomem *base = pcie->base;
673 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
674
675 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
676 }
677
brcm_pcie_link_up(struct brcm_pcie * pcie)678 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
679 {
680 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
681 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
682 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
683
684 return dla && plu;
685 }
686
brcm_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)687 static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
688 unsigned int devfn, int where)
689 {
690 struct brcm_pcie *pcie = bus->sysdata;
691 void __iomem *base = pcie->base;
692 int idx;
693
694 /* Accesses to the RC go right to the RC registers if !devfn */
695 if (pci_is_root_bus(bus))
696 return devfn ? NULL : base + PCIE_ECAM_REG(where);
697
698 /* An access to our HW w/o link-up will cause a CPU Abort */
699 if (!brcm_pcie_link_up(pcie))
700 return NULL;
701
702 /* For devices, write to the config space index register */
703 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
704 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
705 return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
706 }
707
brcm7425_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)708 static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
709 unsigned int devfn, int where)
710 {
711 struct brcm_pcie *pcie = bus->sysdata;
712 void __iomem *base = pcie->base;
713 int idx;
714
715 /* Accesses to the RC go right to the RC registers if !devfn */
716 if (pci_is_root_bus(bus))
717 return devfn ? NULL : base + PCIE_ECAM_REG(where);
718
719 /* An access to our HW w/o link-up will cause a CPU Abort */
720 if (!brcm_pcie_link_up(pcie))
721 return NULL;
722
723 /* For devices, write to the config space index register */
724 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where);
725 writel(idx, base + IDX_ADDR(pcie));
726 return base + DATA_ADDR(pcie);
727 }
728
brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie * pcie,u32 val)729 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
730 {
731 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
732 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
733
734 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
735 tmp = (tmp & ~mask) | ((val << shift) & mask);
736 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
737 }
738
brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie * pcie,u32 val)739 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
740 {
741 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
742 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
743
744 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
745 tmp = (tmp & ~mask) | ((val << shift) & mask);
746 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
747 }
748
brcm_pcie_perst_set_4908(struct brcm_pcie * pcie,u32 val)749 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
750 {
751 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
752 return;
753
754 if (val)
755 reset_control_assert(pcie->perst_reset);
756 else
757 reset_control_deassert(pcie->perst_reset);
758 }
759
brcm_pcie_perst_set_7278(struct brcm_pcie * pcie,u32 val)760 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
761 {
762 u32 tmp;
763
764 /* Perst bit has moved and assert value is 0 */
765 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
766 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
767 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
768 }
769
brcm_pcie_perst_set_generic(struct brcm_pcie * pcie,u32 val)770 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
771 {
772 u32 tmp;
773
774 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
775 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
776 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
777 }
778
brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie * pcie,u64 * rc_bar2_size,u64 * rc_bar2_offset)779 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
780 u64 *rc_bar2_size,
781 u64 *rc_bar2_offset)
782 {
783 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
784 struct resource_entry *entry;
785 struct device *dev = pcie->dev;
786 u64 lowest_pcie_addr = ~(u64)0;
787 int ret, i = 0;
788 u64 size = 0;
789
790 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
791 u64 pcie_beg = entry->res->start - entry->offset;
792
793 size += entry->res->end - entry->res->start + 1;
794 if (pcie_beg < lowest_pcie_addr)
795 lowest_pcie_addr = pcie_beg;
796 }
797
798 if (lowest_pcie_addr == ~(u64)0) {
799 dev_err(dev, "DT node has no dma-ranges\n");
800 return -EINVAL;
801 }
802
803 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
804 PCIE_BRCM_MAX_MEMC);
805
806 if (ret <= 0) {
807 /* Make an educated guess */
808 pcie->num_memc = 1;
809 pcie->memc_size[0] = 1ULL << fls64(size - 1);
810 } else {
811 pcie->num_memc = ret;
812 }
813
814 /* Each memc is viewed through a "port" that is a power of 2 */
815 for (i = 0, size = 0; i < pcie->num_memc; i++)
816 size += pcie->memc_size[i];
817
818 /* System memory starts at this address in PCIe-space */
819 *rc_bar2_offset = lowest_pcie_addr;
820 /* The sum of all memc views must also be a power of 2 */
821 *rc_bar2_size = 1ULL << fls64(size - 1);
822
823 /*
824 * We validate the inbound memory view even though we should trust
825 * whatever the device-tree provides. This is because of an HW issue on
826 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
827 * firmware has to dynamically edit dma-ranges due to a bug on the
828 * PCIe controller integration, which prohibits any access above the
829 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
830 * in check, avoiding hard to debug device-tree related issues in the
831 * future:
832 *
833 * The PCIe host controller by design must set the inbound viewport to
834 * be a contiguous arrangement of all of the system's memory. In
835 * addition, its size mut be a power of two. To further complicate
836 * matters, the viewport must start on a pcie-address that is aligned
837 * on a multiple of its size. If a portion of the viewport does not
838 * represent system memory -- e.g. 3GB of memory requires a 4GB
839 * viewport -- we can map the outbound memory in or after 3GB and even
840 * though the viewport will overlap the outbound memory the controller
841 * will know to send outbound memory downstream and everything else
842 * upstream.
843 *
844 * For example:
845 *
846 * - The best-case scenario, memory up to 3GB, is to place the inbound
847 * region in the first 4GB of pcie-space, as some legacy devices can
848 * only address 32bits. We would also like to put the MSI under 4GB
849 * as well, since some devices require a 32bit MSI target address.
850 *
851 * - If the system memory is 4GB or larger we cannot start the inbound
852 * region at location 0 (since we have to allow some space for
853 * outbound memory @ 3GB). So instead it will start at the 1x
854 * multiple of its size
855 */
856 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
857 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
858 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
859 *rc_bar2_size, *rc_bar2_offset);
860 return -EINVAL;
861 }
862
863 return 0;
864 }
865
brcm_pcie_setup(struct brcm_pcie * pcie)866 static int brcm_pcie_setup(struct brcm_pcie *pcie)
867 {
868 u64 rc_bar2_offset, rc_bar2_size;
869 void __iomem *base = pcie->base;
870 struct pci_host_bridge *bridge;
871 struct resource_entry *entry;
872 u32 tmp, burst, aspm_support;
873 int num_out_wins = 0;
874 int ret, memc;
875
876 /* Reset the bridge */
877 pcie->bridge_sw_init_set(pcie, 1);
878 usleep_range(100, 200);
879
880 /* Take the bridge out of reset */
881 pcie->bridge_sw_init_set(pcie, 0);
882
883 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
884 if (is_bmips(pcie))
885 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
886 else
887 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
888 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
889 /* Wait for SerDes to be stable */
890 usleep_range(100, 200);
891
892 /*
893 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
894 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
895 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
896 */
897 if (is_bmips(pcie))
898 burst = 0x1; /* 256 bytes */
899 else if (pcie->type == BCM2711)
900 burst = 0x0; /* 128 bytes */
901 else if (pcie->type == BCM7278)
902 burst = 0x3; /* 512 bytes */
903 else
904 burst = 0x2; /* 512 bytes */
905
906 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
907 tmp = readl(base + PCIE_MISC_MISC_CTRL);
908 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
909 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
910 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
911 writel(tmp, base + PCIE_MISC_MISC_CTRL);
912
913 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
914 &rc_bar2_offset);
915 if (ret)
916 return ret;
917
918 tmp = lower_32_bits(rc_bar2_offset);
919 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
920 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
921 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
922 writel(upper_32_bits(rc_bar2_offset),
923 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
924
925 tmp = readl(base + PCIE_MISC_MISC_CTRL);
926 for (memc = 0; memc < pcie->num_memc; memc++) {
927 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
928
929 if (memc == 0)
930 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
931 else if (memc == 1)
932 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
933 else if (memc == 2)
934 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
935 }
936 writel(tmp, base + PCIE_MISC_MISC_CTRL);
937
938 /*
939 * We ideally want the MSI target address to be located in the 32bit
940 * addressable memory area. Some devices might depend on it. This is
941 * possible either when the inbound window is located above the lower
942 * 4GB or when the inbound area is smaller than 4GB (taking into
943 * account the rounding-up we're forced to perform).
944 */
945 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
946 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
947 else
948 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
949
950 if (!brcm_pcie_rc_mode(pcie)) {
951 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
952 return -EINVAL;
953 }
954
955 /* disable the PCIe->GISB memory window (RC_BAR1) */
956 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
957 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
958 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
959
960 /* disable the PCIe->SCB memory window (RC_BAR3) */
961 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
962 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
963 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
964
965 /* Don't advertise L0s capability if 'aspm-no-l0s' */
966 aspm_support = PCIE_LINK_STATE_L1;
967 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
968 aspm_support |= PCIE_LINK_STATE_L0S;
969 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
970 u32p_replace_bits(&tmp, aspm_support,
971 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
972 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
973
974 /*
975 * For config space accesses on the RC, show the right class for
976 * a PCIe-PCIe bridge (the default setting is to be EP mode).
977 */
978 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
979 u32p_replace_bits(&tmp, 0x060400,
980 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
981 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
982
983 bridge = pci_host_bridge_from_priv(pcie);
984 resource_list_for_each_entry(entry, &bridge->windows) {
985 struct resource *res = entry->res;
986
987 if (resource_type(res) != IORESOURCE_MEM)
988 continue;
989
990 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
991 dev_err(pcie->dev, "too many outbound wins\n");
992 return -EINVAL;
993 }
994
995 if (is_bmips(pcie)) {
996 u64 start = res->start;
997 unsigned int j, nwins = resource_size(res) / SZ_128M;
998
999 /* bmips PCIe outbound windows have a 128MB max size */
1000 if (nwins > BRCM_NUM_PCIE_OUT_WINS)
1001 nwins = BRCM_NUM_PCIE_OUT_WINS;
1002 for (j = 0; j < nwins; j++, start += SZ_128M)
1003 brcm_pcie_set_outbound_win(pcie, j, start,
1004 start - entry->offset,
1005 SZ_128M);
1006 break;
1007 }
1008 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1009 res->start - entry->offset,
1010 resource_size(res));
1011 num_out_wins++;
1012 }
1013
1014 /* PCIe->SCB endian mode for BAR */
1015 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1016 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1017 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1018 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1019
1020 return 0;
1021 }
1022
brcm_pcie_start_link(struct brcm_pcie * pcie)1023 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1024 {
1025 struct device *dev = pcie->dev;
1026 void __iomem *base = pcie->base;
1027 u16 nlw, cls, lnksta;
1028 bool ssc_good = false;
1029 u32 tmp;
1030 int ret, i;
1031
1032 /* Unassert the fundamental reset */
1033 pcie->perst_set(pcie, 0);
1034
1035 /*
1036 * Give the RC/EP time to wake up, before trying to configure RC.
1037 * Intermittently check status for link-up, up to a total of 100ms.
1038 */
1039 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1040 msleep(5);
1041
1042 if (!brcm_pcie_link_up(pcie)) {
1043 dev_err(dev, "link down\n");
1044 return -ENODEV;
1045 }
1046
1047 if (pcie->gen)
1048 brcm_pcie_set_gen(pcie, pcie->gen);
1049
1050 if (pcie->ssc) {
1051 ret = brcm_pcie_set_ssc(pcie);
1052 if (ret == 0)
1053 ssc_good = true;
1054 else
1055 dev_err(dev, "failed attempt to enter ssc mode\n");
1056 }
1057
1058 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1059 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1060 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1061 dev_info(dev, "link up, %s x%u %s\n",
1062 pci_speed_string(pcie_link_speed[cls]), nlw,
1063 ssc_good ? "(SSC)" : "(!SSC)");
1064
1065 /*
1066 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
1067 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
1068 */
1069 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1070 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1071 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1072
1073 return 0;
1074 }
1075
1076 static const char * const supplies[] = {
1077 "vpcie3v3",
1078 "vpcie3v3aux",
1079 "vpcie12v",
1080 };
1081
alloc_subdev_regulators(struct device * dev)1082 static void *alloc_subdev_regulators(struct device *dev)
1083 {
1084 const size_t size = sizeof(struct subdev_regulators) +
1085 sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
1086 struct subdev_regulators *sr;
1087 int i;
1088
1089 sr = devm_kzalloc(dev, size, GFP_KERNEL);
1090 if (sr) {
1091 sr->num_supplies = ARRAY_SIZE(supplies);
1092 for (i = 0; i < ARRAY_SIZE(supplies); i++)
1093 sr->supplies[i].supply = supplies[i];
1094 }
1095
1096 return sr;
1097 }
1098
brcm_pcie_add_bus(struct pci_bus * bus)1099 static int brcm_pcie_add_bus(struct pci_bus *bus)
1100 {
1101 struct brcm_pcie *pcie = bus->sysdata;
1102 struct device *dev = &bus->dev;
1103 struct subdev_regulators *sr;
1104 int ret;
1105
1106 if (!bus->parent || !pci_is_root_bus(bus->parent))
1107 return 0;
1108
1109 if (dev->of_node) {
1110 sr = alloc_subdev_regulators(dev);
1111 if (!sr) {
1112 dev_info(dev, "Can't allocate regulators for downstream device\n");
1113 goto no_regulators;
1114 }
1115
1116 pcie->sr = sr;
1117
1118 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
1119 if (ret) {
1120 dev_info(dev, "No regulators for downstream device\n");
1121 goto no_regulators;
1122 }
1123
1124 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
1125 if (ret) {
1126 dev_err(dev, "Can't enable regulators for downstream device\n");
1127 regulator_bulk_free(sr->num_supplies, sr->supplies);
1128 pcie->sr = NULL;
1129 }
1130 }
1131
1132 no_regulators:
1133 brcm_pcie_start_link(pcie);
1134 return 0;
1135 }
1136
brcm_pcie_remove_bus(struct pci_bus * bus)1137 static void brcm_pcie_remove_bus(struct pci_bus *bus)
1138 {
1139 struct brcm_pcie *pcie = bus->sysdata;
1140 struct subdev_regulators *sr = pcie->sr;
1141 struct device *dev = &bus->dev;
1142
1143 if (!sr)
1144 return;
1145
1146 if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
1147 dev_err(dev, "Failed to disable regulators for downstream device\n");
1148 regulator_bulk_free(sr->num_supplies, sr->supplies);
1149 pcie->sr = NULL;
1150 }
1151
1152 /* L23 is a low-power PCIe link state */
brcm_pcie_enter_l23(struct brcm_pcie * pcie)1153 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1154 {
1155 void __iomem *base = pcie->base;
1156 int l23, i;
1157 u32 tmp;
1158
1159 /* Assert request for L23 */
1160 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1161 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1162 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1163
1164 /* Wait up to 36 msec for L23 */
1165 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1166 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1167 for (i = 0; i < 15 && !l23; i++) {
1168 usleep_range(2000, 2400);
1169 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1170 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1171 tmp);
1172 }
1173
1174 if (!l23)
1175 dev_err(pcie->dev, "failed to enter low-power link state\n");
1176 }
1177
brcm_phy_cntl(struct brcm_pcie * pcie,const int start)1178 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1179 {
1180 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1181 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1182 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1183 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1184 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1185 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1186 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1187 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1188 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1189 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1190 u32 tmp, combined_mask = 0;
1191 u32 val;
1192 void __iomem *base = pcie->base;
1193 int i, ret;
1194
1195 for (i = beg; i != end; start ? i++ : i--) {
1196 val = start ? BIT_MASK(shifts[i]) : 0;
1197 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1198 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1199 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1200 usleep_range(50, 200);
1201 combined_mask |= masks[i];
1202 }
1203
1204 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1205 val = start ? combined_mask : 0;
1206
1207 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1208 if (ret)
1209 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1210
1211 return ret;
1212 }
1213
brcm_phy_start(struct brcm_pcie * pcie)1214 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1215 {
1216 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1217 }
1218
brcm_phy_stop(struct brcm_pcie * pcie)1219 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1220 {
1221 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1222 }
1223
brcm_pcie_turn_off(struct brcm_pcie * pcie)1224 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1225 {
1226 void __iomem *base = pcie->base;
1227 int tmp;
1228
1229 if (brcm_pcie_link_up(pcie))
1230 brcm_pcie_enter_l23(pcie);
1231 /* Assert fundamental reset */
1232 pcie->perst_set(pcie, 1);
1233
1234 /* Deassert request for L23 in case it was asserted */
1235 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1236 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1237 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1238
1239 /* Turn off SerDes */
1240 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1241 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1242 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1243
1244 /* Shutdown PCIe bridge */
1245 pcie->bridge_sw_init_set(pcie, 1);
1246 }
1247
pci_dev_may_wakeup(struct pci_dev * dev,void * data)1248 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
1249 {
1250 bool *ret = data;
1251
1252 if (device_may_wakeup(&dev->dev)) {
1253 *ret = true;
1254 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n");
1255 }
1256 return (int) *ret;
1257 }
1258
brcm_pcie_suspend_noirq(struct device * dev)1259 static int brcm_pcie_suspend_noirq(struct device *dev)
1260 {
1261 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1262 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1263 int ret;
1264
1265 brcm_pcie_turn_off(pcie);
1266 /*
1267 * If brcm_phy_stop() returns an error, just dev_err(). If we
1268 * return the error it will cause the suspend to fail and this is a
1269 * forgivable offense that will probably be erased on resume.
1270 */
1271 if (brcm_phy_stop(pcie))
1272 dev_err(dev, "Could not stop phy for suspend\n");
1273
1274 ret = reset_control_rearm(pcie->rescal);
1275 if (ret) {
1276 dev_err(dev, "Could not rearm rescal reset\n");
1277 return ret;
1278 }
1279
1280 if (pcie->sr) {
1281 /*
1282 * Now turn off the regulators, but if at least one
1283 * downstream device is enabled as a wake-up source, do not
1284 * turn off regulators.
1285 */
1286 pcie->ep_wakeup_capable = false;
1287 pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
1288 &pcie->ep_wakeup_capable);
1289 if (!pcie->ep_wakeup_capable) {
1290 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1291 pcie->sr->supplies);
1292 if (ret) {
1293 dev_err(dev, "Could not turn off regulators\n");
1294 reset_control_reset(pcie->rescal);
1295 return ret;
1296 }
1297 }
1298 }
1299 clk_disable_unprepare(pcie->clk);
1300
1301 return 0;
1302 }
1303
brcm_pcie_resume_noirq(struct device * dev)1304 static int brcm_pcie_resume_noirq(struct device *dev)
1305 {
1306 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1307 void __iomem *base;
1308 u32 tmp;
1309 int ret;
1310
1311 base = pcie->base;
1312 ret = clk_prepare_enable(pcie->clk);
1313 if (ret)
1314 return ret;
1315
1316 ret = reset_control_reset(pcie->rescal);
1317 if (ret)
1318 goto err_disable_clk;
1319
1320 ret = brcm_phy_start(pcie);
1321 if (ret)
1322 goto err_reset;
1323
1324 /* Take bridge out of reset so we can access the SERDES reg */
1325 pcie->bridge_sw_init_set(pcie, 0);
1326
1327 /* SERDES_IDDQ = 0 */
1328 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1329 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1330 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1331
1332 /* wait for serdes to be stable */
1333 udelay(100);
1334
1335 ret = brcm_pcie_setup(pcie);
1336 if (ret)
1337 goto err_reset;
1338
1339 if (pcie->sr) {
1340 if (pcie->ep_wakeup_capable) {
1341 /*
1342 * We are resuming from a suspend. In the suspend we
1343 * did not disable the power supplies, so there is
1344 * no need to enable them (and falsely increase their
1345 * usage count).
1346 */
1347 pcie->ep_wakeup_capable = false;
1348 } else {
1349 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1350 pcie->sr->supplies);
1351 if (ret) {
1352 dev_err(dev, "Could not turn on regulators\n");
1353 goto err_reset;
1354 }
1355 }
1356 }
1357
1358 ret = brcm_pcie_start_link(pcie);
1359 if (ret)
1360 goto err_regulator;
1361
1362 if (pcie->msi)
1363 brcm_msi_set_regs(pcie->msi);
1364
1365 return 0;
1366
1367 err_regulator:
1368 if (pcie->sr)
1369 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1370 err_reset:
1371 reset_control_rearm(pcie->rescal);
1372 err_disable_clk:
1373 clk_disable_unprepare(pcie->clk);
1374 return ret;
1375 }
1376
__brcm_pcie_remove(struct brcm_pcie * pcie)1377 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1378 {
1379 brcm_msi_remove(pcie);
1380 brcm_pcie_turn_off(pcie);
1381 if (brcm_phy_stop(pcie))
1382 dev_err(pcie->dev, "Could not stop phy\n");
1383 if (reset_control_rearm(pcie->rescal))
1384 dev_err(pcie->dev, "Could not rearm rescal reset\n");
1385 clk_disable_unprepare(pcie->clk);
1386 }
1387
brcm_pcie_remove(struct platform_device * pdev)1388 static int brcm_pcie_remove(struct platform_device *pdev)
1389 {
1390 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1391 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1392
1393 pci_stop_root_bus(bridge->bus);
1394 pci_remove_root_bus(bridge->bus);
1395 __brcm_pcie_remove(pcie);
1396
1397 return 0;
1398 }
1399
1400 static const int pcie_offsets[] = {
1401 [RGR1_SW_INIT_1] = 0x9210,
1402 [EXT_CFG_INDEX] = 0x9000,
1403 [EXT_CFG_DATA] = 0x9004,
1404 };
1405
1406 static const int pcie_offsets_bmips_7425[] = {
1407 [RGR1_SW_INIT_1] = 0x8010,
1408 [EXT_CFG_INDEX] = 0x8300,
1409 [EXT_CFG_DATA] = 0x8304,
1410 };
1411
1412 static const struct pcie_cfg_data generic_cfg = {
1413 .offsets = pcie_offsets,
1414 .type = GENERIC,
1415 .perst_set = brcm_pcie_perst_set_generic,
1416 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1417 };
1418
1419 static const struct pcie_cfg_data bcm7425_cfg = {
1420 .offsets = pcie_offsets_bmips_7425,
1421 .type = BCM7425,
1422 .perst_set = brcm_pcie_perst_set_generic,
1423 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1424 };
1425
1426 static const struct pcie_cfg_data bcm7435_cfg = {
1427 .offsets = pcie_offsets,
1428 .type = BCM7435,
1429 .perst_set = brcm_pcie_perst_set_generic,
1430 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1431 };
1432
1433 static const struct pcie_cfg_data bcm4908_cfg = {
1434 .offsets = pcie_offsets,
1435 .type = BCM4908,
1436 .perst_set = brcm_pcie_perst_set_4908,
1437 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1438 };
1439
1440 static const int pcie_offset_bcm7278[] = {
1441 [RGR1_SW_INIT_1] = 0xc010,
1442 [EXT_CFG_INDEX] = 0x9000,
1443 [EXT_CFG_DATA] = 0x9004,
1444 };
1445
1446 static const struct pcie_cfg_data bcm7278_cfg = {
1447 .offsets = pcie_offset_bcm7278,
1448 .type = BCM7278,
1449 .perst_set = brcm_pcie_perst_set_7278,
1450 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
1451 };
1452
1453 static const struct pcie_cfg_data bcm2711_cfg = {
1454 .offsets = pcie_offsets,
1455 .type = BCM2711,
1456 .perst_set = brcm_pcie_perst_set_generic,
1457 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1458 };
1459
1460 static const struct of_device_id brcm_pcie_match[] = {
1461 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1462 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1463 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1464 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1465 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1466 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1467 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1468 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1469 {},
1470 };
1471
1472 static struct pci_ops brcm_pcie_ops = {
1473 .map_bus = brcm_pcie_map_bus,
1474 .read = pci_generic_config_read,
1475 .write = pci_generic_config_write,
1476 .add_bus = brcm_pcie_add_bus,
1477 .remove_bus = brcm_pcie_remove_bus,
1478 };
1479
1480 static struct pci_ops brcm7425_pcie_ops = {
1481 .map_bus = brcm7425_pcie_map_bus,
1482 .read = pci_generic_config_read32,
1483 .write = pci_generic_config_write32,
1484 .add_bus = brcm_pcie_add_bus,
1485 .remove_bus = brcm_pcie_remove_bus,
1486 };
1487
brcm_pcie_probe(struct platform_device * pdev)1488 static int brcm_pcie_probe(struct platform_device *pdev)
1489 {
1490 struct device_node *np = pdev->dev.of_node, *msi_np;
1491 struct pci_host_bridge *bridge;
1492 const struct pcie_cfg_data *data;
1493 struct brcm_pcie *pcie;
1494 int ret;
1495
1496 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1497 if (!bridge)
1498 return -ENOMEM;
1499
1500 data = of_device_get_match_data(&pdev->dev);
1501 if (!data) {
1502 pr_err("failed to look up compatible string\n");
1503 return -EINVAL;
1504 }
1505
1506 pcie = pci_host_bridge_priv(bridge);
1507 pcie->dev = &pdev->dev;
1508 pcie->np = np;
1509 pcie->reg_offsets = data->offsets;
1510 pcie->type = data->type;
1511 pcie->perst_set = data->perst_set;
1512 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1513
1514 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1515 if (IS_ERR(pcie->base))
1516 return PTR_ERR(pcie->base);
1517
1518 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1519 if (IS_ERR(pcie->clk))
1520 return PTR_ERR(pcie->clk);
1521
1522 ret = of_pci_get_max_link_speed(np);
1523 pcie->gen = (ret < 0) ? 0 : ret;
1524
1525 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1526
1527 ret = clk_prepare_enable(pcie->clk);
1528 if (ret) {
1529 dev_err(&pdev->dev, "could not enable clock\n");
1530 return ret;
1531 }
1532 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1533 if (IS_ERR(pcie->rescal)) {
1534 clk_disable_unprepare(pcie->clk);
1535 return PTR_ERR(pcie->rescal);
1536 }
1537 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1538 if (IS_ERR(pcie->perst_reset)) {
1539 clk_disable_unprepare(pcie->clk);
1540 return PTR_ERR(pcie->perst_reset);
1541 }
1542
1543 ret = reset_control_reset(pcie->rescal);
1544 if (ret)
1545 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1546
1547 ret = brcm_phy_start(pcie);
1548 if (ret) {
1549 reset_control_rearm(pcie->rescal);
1550 clk_disable_unprepare(pcie->clk);
1551 return ret;
1552 }
1553
1554 ret = brcm_pcie_setup(pcie);
1555 if (ret)
1556 goto fail;
1557
1558 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1559 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1560 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1561 ret = -ENODEV;
1562 goto fail;
1563 }
1564
1565 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1566 if (pci_msi_enabled() && msi_np == pcie->np) {
1567 ret = brcm_pcie_enable_msi(pcie);
1568 if (ret) {
1569 dev_err(pcie->dev, "probe of internal MSI failed");
1570 goto fail;
1571 }
1572 }
1573
1574 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1575 bridge->sysdata = pcie;
1576
1577 platform_set_drvdata(pdev, pcie);
1578
1579 ret = pci_host_probe(bridge);
1580 if (!ret && !brcm_pcie_link_up(pcie))
1581 ret = -ENODEV;
1582
1583 if (ret) {
1584 brcm_pcie_remove(pdev);
1585 return ret;
1586 }
1587
1588 return 0;
1589
1590 fail:
1591 __brcm_pcie_remove(pcie);
1592 return ret;
1593 }
1594
1595 MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1596
1597 static const struct dev_pm_ops brcm_pcie_pm_ops = {
1598 .suspend_noirq = brcm_pcie_suspend_noirq,
1599 .resume_noirq = brcm_pcie_resume_noirq,
1600 };
1601
1602 static struct platform_driver brcm_pcie_driver = {
1603 .probe = brcm_pcie_probe,
1604 .remove = brcm_pcie_remove,
1605 .driver = {
1606 .name = "brcm-pcie",
1607 .of_match_table = brcm_pcie_match,
1608 .pm = &brcm_pcie_pm_ops,
1609 },
1610 };
1611 module_platform_driver(brcm_pcie_driver);
1612
1613 MODULE_LICENSE("GPL");
1614 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1615 MODULE_AUTHOR("Broadcom");
1616
