1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/module.h>
25
26 #include "pcie-designware.h"
27
28 /* PARF registers */
29 #define PARF_SYS_CTRL 0x00
30 #define PARF_DB_CTRL 0x10
31 #define PARF_PM_CTRL 0x20
32 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
33 #define PARF_MHI_BASE_ADDR_LOWER 0x178
34 #define PARF_MHI_BASE_ADDR_UPPER 0x17c
35 #define PARF_DEBUG_INT_EN 0x190
36 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
37 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
38 #define PARF_Q2A_FLUSH 0x1ac
39 #define PARF_LTSSM 0x1b0
40 #define PARF_CFG_BITS 0x210
41 #define PARF_INT_ALL_STATUS 0x224
42 #define PARF_INT_ALL_CLEAR 0x228
43 #define PARF_INT_ALL_MASK 0x22c
44 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0
45 #define PARF_DBI_BASE_ADDR 0x350
46 #define PARF_DBI_BASE_ADDR_HI 0x354
47 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
48 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
49 #define PARF_ATU_BASE_ADDR 0x634
50 #define PARF_ATU_BASE_ADDR_HI 0x638
51 #define PARF_SRIS_MODE 0x644
52 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
53 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
54 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
55 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
56 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
57 #define PARF_DEVICE_TYPE 0x1000
58 #define PARF_BDF_TO_SID_CFG 0x2c00
59
60 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
61 #define PARF_INT_ALL_LINK_DOWN BIT(1)
62 #define PARF_INT_ALL_BME BIT(2)
63 #define PARF_INT_ALL_PM_TURNOFF BIT(3)
64 #define PARF_INT_ALL_DEBUG BIT(4)
65 #define PARF_INT_ALL_LTR BIT(5)
66 #define PARF_INT_ALL_MHI_Q6 BIT(6)
67 #define PARF_INT_ALL_MHI_A7 BIT(7)
68 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
69 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
70 #define PARF_INT_ALL_MMIO_WRITE BIT(10)
71 #define PARF_INT_ALL_CFG_WRITE BIT(11)
72 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
73 #define PARF_INT_ALL_LINK_UP BIT(13)
74 #define PARF_INT_ALL_AER_LEGACY BIT(14)
75 #define PARF_INT_ALL_PLS_ERR BIT(15)
76 #define PARF_INT_ALL_PME_LEGACY BIT(16)
77 #define PARF_INT_ALL_PLS_PME BIT(17)
78 #define PARF_INT_ALL_EDMA BIT(22)
79
80 /* PARF_BDF_TO_SID_CFG register fields */
81 #define PARF_BDF_TO_SID_BYPASS BIT(0)
82
83 /* PARF_DEBUG_INT_EN register fields */
84 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
85 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
86 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
87
88 /* PARF_DEVICE_TYPE register fields */
89 #define PARF_DEVICE_TYPE_EP 0x0
90
91 /* PARF_PM_CTRL register fields */
92 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
93 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
94 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
95
96 /* PARF_MHI_CLOCK_RESET_CTRL fields */
97 #define PARF_MSTR_AXI_CLK_EN BIT(1)
98
99 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
100 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
101
102 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
103 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
104
105 /* PARF_Q2A_FLUSH register fields */
106 #define PARF_Q2A_FLUSH_EN BIT(16)
107
108 /* PARF_SYS_CTRL register fields */
109 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
110 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
111 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
112 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
113
114 /* PARF_DB_CTRL register fields */
115 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
116 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
117 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
118 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
119 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
120
121 /* PARF_CFG_BITS register fields */
122 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
123
124 /* ELBI registers */
125 #define ELBI_SYS_STTS 0x08
126
127 /* DBI registers */
128 #define DBI_CON_STATUS 0x44
129
130 /* DBI register fields */
131 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
132
133 #define XMLH_LINK_UP 0x400
134 #define CORE_RESET_TIME_US_MIN 1000
135 #define CORE_RESET_TIME_US_MAX 1005
136 #define WAKE_DELAY_US 2000 /* 2 ms */
137
138 #define PCIE_GEN1_BW_MBPS 250
139 #define PCIE_GEN2_BW_MBPS 500
140 #define PCIE_GEN3_BW_MBPS 985
141 #define PCIE_GEN4_BW_MBPS 1969
142
143 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
144
145 enum qcom_pcie_ep_link_status {
146 QCOM_PCIE_EP_LINK_DISABLED,
147 QCOM_PCIE_EP_LINK_ENABLED,
148 QCOM_PCIE_EP_LINK_UP,
149 QCOM_PCIE_EP_LINK_DOWN,
150 };
151
152 /**
153 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
154 * @pci: Designware PCIe controller struct
155 * @parf: Qualcomm PCIe specific PARF register base
156 * @elbi: Designware PCIe specific ELBI register base
157 * @mmio: MMIO register base
158 * @perst_map: PERST regmap
159 * @mmio_res: MMIO region resource
160 * @core_reset: PCIe Endpoint core reset
161 * @reset: PERST# GPIO
162 * @wake: WAKE# GPIO
163 * @phy: PHY controller block
164 * @debugfs: PCIe Endpoint Debugfs directory
165 * @icc_mem: Handle to an interconnect path between PCIe and MEM
166 * @clks: PCIe clocks
167 * @num_clks: PCIe clocks count
168 * @perst_en: Flag for PERST enable
169 * @perst_sep_en: Flag for PERST separation enable
170 * @link_status: PCIe Link status
171 * @global_irq: Qualcomm PCIe specific Global IRQ
172 * @perst_irq: PERST# IRQ
173 */
174 struct qcom_pcie_ep {
175 struct dw_pcie pci;
176
177 void __iomem *parf;
178 void __iomem *elbi;
179 void __iomem *mmio;
180 struct regmap *perst_map;
181 struct resource *mmio_res;
182
183 struct reset_control *core_reset;
184 struct gpio_desc *reset;
185 struct gpio_desc *wake;
186 struct phy *phy;
187 struct dentry *debugfs;
188
189 struct icc_path *icc_mem;
190
191 struct clk_bulk_data *clks;
192 int num_clks;
193
194 u32 perst_en;
195 u32 perst_sep_en;
196
197 enum qcom_pcie_ep_link_status link_status;
198 int global_irq;
199 int perst_irq;
200 };
201
qcom_pcie_ep_core_reset(struct qcom_pcie_ep * pcie_ep)202 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
203 {
204 struct dw_pcie *pci = &pcie_ep->pci;
205 struct device *dev = pci->dev;
206 int ret;
207
208 ret = reset_control_assert(pcie_ep->core_reset);
209 if (ret) {
210 dev_err(dev, "Cannot assert core reset\n");
211 return ret;
212 }
213
214 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
215
216 ret = reset_control_deassert(pcie_ep->core_reset);
217 if (ret) {
218 dev_err(dev, "Cannot de-assert core reset\n");
219 return ret;
220 }
221
222 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
223
224 return 0;
225 }
226
227 /*
228 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
229 * device reset during host reboot and hibernation. The driver is
230 * expected to handle this situation.
231 */
qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep * pcie_ep)232 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
233 {
234 if (pcie_ep->perst_map) {
235 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
236 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
237 }
238 }
239
qcom_pcie_dw_link_up(struct dw_pcie * pci)240 static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
241 {
242 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
243 u32 reg;
244
245 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
246
247 return reg & XMLH_LINK_UP;
248 }
249
qcom_pcie_dw_start_link(struct dw_pcie * pci)250 static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
251 {
252 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
253
254 enable_irq(pcie_ep->perst_irq);
255
256 return 0;
257 }
258
qcom_pcie_dw_stop_link(struct dw_pcie * pci)259 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
260 {
261 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
262
263 disable_irq(pcie_ep->perst_irq);
264 }
265
qcom_pcie_ep_icc_update(struct qcom_pcie_ep * pcie_ep)266 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
267 {
268 struct dw_pcie *pci = &pcie_ep->pci;
269 u32 offset, status, bw;
270 int speed, width;
271 int ret;
272
273 if (!pcie_ep->icc_mem)
274 return;
275
276 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
277 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
278
279 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
280 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
281
282 switch (speed) {
283 case 1:
284 bw = MBps_to_icc(PCIE_GEN1_BW_MBPS);
285 break;
286 case 2:
287 bw = MBps_to_icc(PCIE_GEN2_BW_MBPS);
288 break;
289 case 3:
290 bw = MBps_to_icc(PCIE_GEN3_BW_MBPS);
291 break;
292 default:
293 dev_warn(pci->dev, "using default GEN4 bandwidth\n");
294 fallthrough;
295 case 4:
296 bw = MBps_to_icc(PCIE_GEN4_BW_MBPS);
297 break;
298 }
299
300 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw);
301 if (ret)
302 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
303 ret);
304 }
305
qcom_pcie_enable_resources(struct qcom_pcie_ep * pcie_ep)306 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
307 {
308 struct dw_pcie *pci = &pcie_ep->pci;
309 int ret;
310
311 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
312 if (ret)
313 return ret;
314
315 ret = qcom_pcie_ep_core_reset(pcie_ep);
316 if (ret)
317 goto err_disable_clk;
318
319 ret = phy_init(pcie_ep->phy);
320 if (ret)
321 goto err_disable_clk;
322
323 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
324 if (ret)
325 goto err_phy_exit;
326
327 ret = phy_power_on(pcie_ep->phy);
328 if (ret)
329 goto err_phy_exit;
330
331 /*
332 * Some Qualcomm platforms require interconnect bandwidth constraints
333 * to be set before enabling interconnect clocks.
334 *
335 * Set an initial peak bandwidth corresponding to single-lane Gen 1
336 * for the pcie-mem path.
337 */
338 ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS));
339 if (ret) {
340 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
341 ret);
342 goto err_phy_off;
343 }
344
345 return 0;
346
347 err_phy_off:
348 phy_power_off(pcie_ep->phy);
349 err_phy_exit:
350 phy_exit(pcie_ep->phy);
351 err_disable_clk:
352 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
353
354 return ret;
355 }
356
qcom_pcie_disable_resources(struct qcom_pcie_ep * pcie_ep)357 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
358 {
359 icc_set_bw(pcie_ep->icc_mem, 0, 0);
360 phy_power_off(pcie_ep->phy);
361 phy_exit(pcie_ep->phy);
362 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
363 }
364
qcom_pcie_perst_deassert(struct dw_pcie * pci)365 static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
366 {
367 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
368 struct device *dev = pci->dev;
369 u32 val, offset;
370 int ret;
371
372 ret = qcom_pcie_enable_resources(pcie_ep);
373 if (ret) {
374 dev_err(dev, "Failed to enable resources: %d\n", ret);
375 return ret;
376 }
377
378 /* Assert WAKE# to RC to indicate device is ready */
379 gpiod_set_value_cansleep(pcie_ep->wake, 1);
380 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
381 gpiod_set_value_cansleep(pcie_ep->wake, 0);
382
383 qcom_pcie_ep_configure_tcsr(pcie_ep);
384
385 /* Disable BDF to SID mapping */
386 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
387 val |= PARF_BDF_TO_SID_BYPASS;
388 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
389
390 /* Enable debug IRQ */
391 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
392 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
393 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
394 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
395 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
396
397 /* Configure PCIe to endpoint mode */
398 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
399
400 /* Allow entering L1 state */
401 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
402 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
403 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
404
405 /* Read halts write */
406 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
407 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
408 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
409
410 /* Write after write halt */
411 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
412 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
413 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
414
415 /* Q2A flush disable */
416 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
417 val &= ~PARF_Q2A_FLUSH_EN;
418 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
419
420 /*
421 * Disable Master AXI clock during idle. Do not allow DBI access
422 * to take the core out of L1. Disable core clock gating that
423 * gates PIPE clock from propagating to core clock. Report to the
424 * host that Vaux is present.
425 */
426 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
427 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
428 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
429 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
430 PARF_SYS_CTRL_AUX_PWR_DET;
431 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
432
433 /* Disable the debouncers */
434 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
435 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
436 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
437 PARF_DB_CTRL_MST_WKP_BLOCK;
438 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
439
440 /* Request to exit from L1SS for MSI and LTR MSG */
441 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
442 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
443 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
444
445 dw_pcie_dbi_ro_wr_en(pci);
446
447 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
448 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
449 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
450 val &= ~PCI_EXP_LNKCAP_L0SEL;
451 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
452 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
453
454 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
455 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
456 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
457 val &= ~PCI_EXP_LNKCAP_L1EL;
458 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
459 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
460
461 dw_pcie_dbi_ro_wr_dis(pci);
462
463 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
464 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
465 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
466 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
467 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
468
469 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
470 if (ret) {
471 dev_err(dev, "Failed to complete initialization: %d\n", ret);
472 goto err_disable_resources;
473 }
474
475 /*
476 * The physical address of the MMIO region which is exposed as the BAR
477 * should be written to MHI BASE registers.
478 */
479 writel_relaxed(pcie_ep->mmio_res->start,
480 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
481 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
482
483 /* Gate Master AXI clock to MHI bus during L1SS */
484 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
485 val &= ~PARF_MSTR_AXI_CLK_EN;
486 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
487
488 dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
489
490 /* Enable LTSSM */
491 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
492 val |= BIT(8);
493 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
494
495 return 0;
496
497 err_disable_resources:
498 qcom_pcie_disable_resources(pcie_ep);
499
500 return ret;
501 }
502
qcom_pcie_perst_assert(struct dw_pcie * pci)503 static void qcom_pcie_perst_assert(struct dw_pcie *pci)
504 {
505 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
506 struct device *dev = pci->dev;
507
508 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) {
509 dev_dbg(dev, "Link is already disabled\n");
510 return;
511 }
512
513 qcom_pcie_disable_resources(pcie_ep);
514 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
515 }
516
517 /* Common DWC controller ops */
518 static const struct dw_pcie_ops pci_ops = {
519 .link_up = qcom_pcie_dw_link_up,
520 .start_link = qcom_pcie_dw_start_link,
521 .stop_link = qcom_pcie_dw_stop_link,
522 };
523
qcom_pcie_ep_get_io_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)524 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
525 struct qcom_pcie_ep *pcie_ep)
526 {
527 struct device *dev = &pdev->dev;
528 struct dw_pcie *pci = &pcie_ep->pci;
529 struct device_node *syscon;
530 struct resource *res;
531 int ret;
532
533 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
534 if (IS_ERR(pcie_ep->parf))
535 return PTR_ERR(pcie_ep->parf);
536
537 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
538 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
539 if (IS_ERR(pci->dbi_base))
540 return PTR_ERR(pci->dbi_base);
541 pci->dbi_base2 = pci->dbi_base;
542
543 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
544 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
545 if (IS_ERR(pcie_ep->elbi))
546 return PTR_ERR(pcie_ep->elbi);
547
548 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
549 "mmio");
550 if (!pcie_ep->mmio_res) {
551 dev_err(dev, "Failed to get mmio resource\n");
552 return -EINVAL;
553 }
554
555 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
556 if (IS_ERR(pcie_ep->mmio))
557 return PTR_ERR(pcie_ep->mmio);
558
559 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
560 if (!syscon) {
561 dev_dbg(dev, "PERST separation not available\n");
562 return 0;
563 }
564
565 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
566 of_node_put(syscon);
567 if (IS_ERR(pcie_ep->perst_map))
568 return PTR_ERR(pcie_ep->perst_map);
569
570 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
571 1, &pcie_ep->perst_en);
572 if (ret < 0) {
573 dev_err(dev, "No Perst Enable offset in syscon\n");
574 return ret;
575 }
576
577 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
578 2, &pcie_ep->perst_sep_en);
579 if (ret < 0) {
580 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
581 return ret;
582 }
583
584 return 0;
585 }
586
qcom_pcie_ep_get_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)587 static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
588 struct qcom_pcie_ep *pcie_ep)
589 {
590 struct device *dev = &pdev->dev;
591 int ret;
592
593 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
594 if (ret) {
595 dev_err(dev, "Failed to get io resources %d\n", ret);
596 return ret;
597 }
598
599 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
600 if (pcie_ep->num_clks < 0) {
601 dev_err(dev, "Failed to get clocks\n");
602 return pcie_ep->num_clks;
603 }
604
605 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
606 if (IS_ERR(pcie_ep->core_reset))
607 return PTR_ERR(pcie_ep->core_reset);
608
609 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
610 if (IS_ERR(pcie_ep->reset))
611 return PTR_ERR(pcie_ep->reset);
612
613 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
614 if (IS_ERR(pcie_ep->wake))
615 return PTR_ERR(pcie_ep->wake);
616
617 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
618 if (IS_ERR(pcie_ep->phy))
619 ret = PTR_ERR(pcie_ep->phy);
620
621 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
622 if (IS_ERR(pcie_ep->icc_mem))
623 ret = PTR_ERR(pcie_ep->icc_mem);
624
625 return ret;
626 }
627
628 /* TODO: Notify clients about PCIe state change */
qcom_pcie_ep_global_irq_thread(int irq,void * data)629 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
630 {
631 struct qcom_pcie_ep *pcie_ep = data;
632 struct dw_pcie *pci = &pcie_ep->pci;
633 struct device *dev = pci->dev;
634 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
635 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK);
636 u32 dstate, val;
637
638 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
639 status &= mask;
640
641 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
642 dev_dbg(dev, "Received Linkdown event\n");
643 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
644 pci_epc_linkdown(pci->ep.epc);
645 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
646 dev_dbg(dev, "Received BME event. Link is enabled!\n");
647 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
648 qcom_pcie_ep_icc_update(pcie_ep);
649 pci_epc_bme_notify(pci->ep.epc);
650 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
651 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
652 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
653 val |= PARF_PM_CTRL_READY_ENTR_L23;
654 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
655 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
656 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
657 DBI_CON_STATUS_POWER_STATE_MASK;
658 dev_dbg(dev, "Received D%d state event\n", dstate);
659 if (dstate == 3) {
660 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
661 val |= PARF_PM_CTRL_REQ_EXIT_L1;
662 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
663 }
664 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
665 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
666 dw_pcie_ep_linkup(&pci->ep);
667 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
668 } else {
669 dev_err(dev, "Received unknown event: %d\n", status);
670 }
671
672 return IRQ_HANDLED;
673 }
674
qcom_pcie_ep_perst_irq_thread(int irq,void * data)675 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
676 {
677 struct qcom_pcie_ep *pcie_ep = data;
678 struct dw_pcie *pci = &pcie_ep->pci;
679 struct device *dev = pci->dev;
680 u32 perst;
681
682 perst = gpiod_get_value(pcie_ep->reset);
683 if (perst) {
684 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
685 qcom_pcie_perst_assert(pci);
686 } else {
687 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
688 qcom_pcie_perst_deassert(pci);
689 }
690
691 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
692 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
693
694 return IRQ_HANDLED;
695 }
696
qcom_pcie_ep_enable_irq_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)697 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
698 struct qcom_pcie_ep *pcie_ep)
699 {
700 int ret;
701
702 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
703 if (pcie_ep->global_irq < 0)
704 return pcie_ep->global_irq;
705
706 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
707 qcom_pcie_ep_global_irq_thread,
708 IRQF_ONESHOT,
709 "global_irq", pcie_ep);
710 if (ret) {
711 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
712 return ret;
713 }
714
715 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
716 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
717 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
718 qcom_pcie_ep_perst_irq_thread,
719 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
720 "perst_irq", pcie_ep);
721 if (ret) {
722 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
723 disable_irq(pcie_ep->global_irq);
724 return ret;
725 }
726
727 return 0;
728 }
729
qcom_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,enum pci_epc_irq_type type,u16 interrupt_num)730 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
731 enum pci_epc_irq_type type, u16 interrupt_num)
732 {
733 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
734
735 switch (type) {
736 case PCI_EPC_IRQ_LEGACY:
737 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
738 case PCI_EPC_IRQ_MSI:
739 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
740 default:
741 dev_err(pci->dev, "Unknown IRQ type\n");
742 return -EINVAL;
743 }
744 }
745
qcom_pcie_ep_link_transition_count(struct seq_file * s,void * data)746 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
747 {
748 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
749 dev_get_drvdata(s->private);
750
751 seq_printf(s, "L0s transition count: %u\n",
752 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
753
754 seq_printf(s, "L1 transition count: %u\n",
755 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
756
757 seq_printf(s, "L1.1 transition count: %u\n",
758 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
759
760 seq_printf(s, "L1.2 transition count: %u\n",
761 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
762
763 seq_printf(s, "L2 transition count: %u\n",
764 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
765
766 return 0;
767 }
768
qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep * pcie_ep)769 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
770 {
771 struct dw_pcie *pci = &pcie_ep->pci;
772
773 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
774 qcom_pcie_ep_link_transition_count);
775 }
776
777 static const struct pci_epc_features qcom_pcie_epc_features = {
778 .linkup_notifier = true,
779 .core_init_notifier = true,
780 .msi_capable = true,
781 .msix_capable = false,
782 .align = SZ_4K,
783 };
784
785 static const struct pci_epc_features *
qcom_pcie_epc_get_features(struct dw_pcie_ep * pci_ep)786 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
787 {
788 return &qcom_pcie_epc_features;
789 }
790
qcom_pcie_ep_init(struct dw_pcie_ep * ep)791 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
792 {
793 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
794 enum pci_barno bar;
795
796 for (bar = BAR_0; bar <= BAR_5; bar++)
797 dw_pcie_ep_reset_bar(pci, bar);
798 }
799
800 static const struct dw_pcie_ep_ops pci_ep_ops = {
801 .ep_init = qcom_pcie_ep_init,
802 .raise_irq = qcom_pcie_ep_raise_irq,
803 .get_features = qcom_pcie_epc_get_features,
804 };
805
qcom_pcie_ep_probe(struct platform_device * pdev)806 static int qcom_pcie_ep_probe(struct platform_device *pdev)
807 {
808 struct device *dev = &pdev->dev;
809 struct qcom_pcie_ep *pcie_ep;
810 char *name;
811 int ret;
812
813 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
814 if (!pcie_ep)
815 return -ENOMEM;
816
817 pcie_ep->pci.dev = dev;
818 pcie_ep->pci.ops = &pci_ops;
819 pcie_ep->pci.ep.ops = &pci_ep_ops;
820 pcie_ep->pci.edma.nr_irqs = 1;
821 platform_set_drvdata(pdev, pcie_ep);
822
823 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
824 if (ret)
825 return ret;
826
827 ret = qcom_pcie_enable_resources(pcie_ep);
828 if (ret) {
829 dev_err(dev, "Failed to enable resources: %d\n", ret);
830 return ret;
831 }
832
833 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
834 if (ret) {
835 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
836 goto err_disable_resources;
837 }
838
839 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
840 if (ret)
841 goto err_disable_resources;
842
843 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
844 if (!name) {
845 ret = -ENOMEM;
846 goto err_disable_irqs;
847 }
848
849 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
850 qcom_pcie_ep_init_debugfs(pcie_ep);
851
852 return 0;
853
854 err_disable_irqs:
855 disable_irq(pcie_ep->global_irq);
856 disable_irq(pcie_ep->perst_irq);
857
858 err_disable_resources:
859 qcom_pcie_disable_resources(pcie_ep);
860
861 return ret;
862 }
863
qcom_pcie_ep_remove(struct platform_device * pdev)864 static void qcom_pcie_ep_remove(struct platform_device *pdev)
865 {
866 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
867
868 disable_irq(pcie_ep->global_irq);
869 disable_irq(pcie_ep->perst_irq);
870
871 debugfs_remove_recursive(pcie_ep->debugfs);
872
873 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
874 return;
875
876 qcom_pcie_disable_resources(pcie_ep);
877 }
878
879 static const struct of_device_id qcom_pcie_ep_match[] = {
880 { .compatible = "qcom,sdx55-pcie-ep", },
881 { .compatible = "qcom,sm8450-pcie-ep", },
882 { }
883 };
884 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
885
886 static struct platform_driver qcom_pcie_ep_driver = {
887 .probe = qcom_pcie_ep_probe,
888 .remove_new = qcom_pcie_ep_remove,
889 .driver = {
890 .name = "qcom-pcie-ep",
891 .of_match_table = qcom_pcie_ep_match,
892 },
893 };
894 builtin_platform_driver(qcom_pcie_ep_driver);
895
896 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
897 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
898 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
899 MODULE_LICENSE("GPL v2");
900
