1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/io.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pci.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22
23 #include "../../pci.h"
24 #include "pcie-cadence.h"
25
26 #define ENABLE_REG_SYS_2 0x108
27 #define STATUS_REG_SYS_2 0x508
28 #define STATUS_CLR_REG_SYS_2 0x708
29 #define LINK_DOWN BIT(1)
30 #define J7200_LINK_DOWN BIT(10)
31
32 #define J721E_PCIE_USER_CMD_STATUS 0x4
33 #define LINK_TRAINING_ENABLE BIT(0)
34
35 #define J721E_PCIE_USER_LINKSTATUS 0x14
36 #define LINK_STATUS GENMASK(1, 0)
37
38 enum link_status {
39 NO_RECEIVERS_DETECTED,
40 LINK_TRAINING_IN_PROGRESS,
41 LINK_UP_DL_IN_PROGRESS,
42 LINK_UP_DL_COMPLETED,
43 };
44
45 #define J721E_MODE_RC BIT(7)
46 #define LANE_COUNT_MASK BIT(8)
47 #define LANE_COUNT(n) ((n) << 8)
48
49 #define GENERATION_SEL_MASK GENMASK(1, 0)
50
51 #define MAX_LANES 2
52
53 struct j721e_pcie {
54 struct cdns_pcie *cdns_pcie;
55 struct clk *refclk;
56 u32 mode;
57 u32 num_lanes;
58 void __iomem *user_cfg_base;
59 void __iomem *intd_cfg_base;
60 u32 linkdown_irq_regfield;
61 };
62
63 enum j721e_pcie_mode {
64 PCI_MODE_RC,
65 PCI_MODE_EP,
66 };
67
68 struct j721e_pcie_data {
69 enum j721e_pcie_mode mode;
70 unsigned int quirk_retrain_flag:1;
71 unsigned int quirk_detect_quiet_flag:1;
72 unsigned int quirk_disable_flr:1;
73 u32 linkdown_irq_regfield;
74 unsigned int byte_access_allowed:1;
75 };
76
j721e_pcie_user_readl(struct j721e_pcie * pcie,u32 offset)77 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
78 {
79 return readl(pcie->user_cfg_base + offset);
80 }
81
j721e_pcie_user_writel(struct j721e_pcie * pcie,u32 offset,u32 value)82 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
83 u32 value)
84 {
85 writel(value, pcie->user_cfg_base + offset);
86 }
87
j721e_pcie_intd_readl(struct j721e_pcie * pcie,u32 offset)88 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
89 {
90 return readl(pcie->intd_cfg_base + offset);
91 }
92
j721e_pcie_intd_writel(struct j721e_pcie * pcie,u32 offset,u32 value)93 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
94 u32 value)
95 {
96 writel(value, pcie->intd_cfg_base + offset);
97 }
98
j721e_pcie_link_irq_handler(int irq,void * priv)99 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
100 {
101 struct j721e_pcie *pcie = priv;
102 struct device *dev = pcie->cdns_pcie->dev;
103 u32 reg;
104
105 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
106 if (!(reg & pcie->linkdown_irq_regfield))
107 return IRQ_NONE;
108
109 dev_err(dev, "LINK DOWN!\n");
110
111 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
112 return IRQ_HANDLED;
113 }
114
j721e_pcie_config_link_irq(struct j721e_pcie * pcie)115 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
116 {
117 u32 reg;
118
119 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
120 reg |= pcie->linkdown_irq_regfield;
121 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
122 }
123
j721e_pcie_start_link(struct cdns_pcie * cdns_pcie)124 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
125 {
126 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
127 u32 reg;
128
129 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
130 reg |= LINK_TRAINING_ENABLE;
131 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
132
133 return 0;
134 }
135
j721e_pcie_stop_link(struct cdns_pcie * cdns_pcie)136 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
137 {
138 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
139 u32 reg;
140
141 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
142 reg &= ~LINK_TRAINING_ENABLE;
143 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
144 }
145
j721e_pcie_link_up(struct cdns_pcie * cdns_pcie)146 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
147 {
148 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
149 u32 reg;
150
151 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
152 reg &= LINK_STATUS;
153 if (reg == LINK_UP_DL_COMPLETED)
154 return true;
155
156 return false;
157 }
158
159 static const struct cdns_pcie_ops j721e_pcie_ops = {
160 .start_link = j721e_pcie_start_link,
161 .stop_link = j721e_pcie_stop_link,
162 .link_up = j721e_pcie_link_up,
163 };
164
j721e_pcie_set_mode(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)165 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
166 unsigned int offset)
167 {
168 struct device *dev = pcie->cdns_pcie->dev;
169 u32 mask = J721E_MODE_RC;
170 u32 mode = pcie->mode;
171 u32 val = 0;
172 int ret = 0;
173
174 if (mode == PCI_MODE_RC)
175 val = J721E_MODE_RC;
176
177 ret = regmap_update_bits(syscon, offset, mask, val);
178 if (ret)
179 dev_err(dev, "failed to set pcie mode\n");
180
181 return ret;
182 }
183
j721e_pcie_set_link_speed(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)184 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
185 struct regmap *syscon, unsigned int offset)
186 {
187 struct device *dev = pcie->cdns_pcie->dev;
188 struct device_node *np = dev->of_node;
189 int link_speed;
190 u32 val = 0;
191 int ret;
192
193 link_speed = of_pci_get_max_link_speed(np);
194 if (link_speed < 2)
195 link_speed = 2;
196
197 val = link_speed - 1;
198 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
199 if (ret)
200 dev_err(dev, "failed to set link speed\n");
201
202 return ret;
203 }
204
j721e_pcie_set_lane_count(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)205 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
206 struct regmap *syscon, unsigned int offset)
207 {
208 struct device *dev = pcie->cdns_pcie->dev;
209 u32 lanes = pcie->num_lanes;
210 u32 val = 0;
211 int ret;
212
213 val = LANE_COUNT(lanes - 1);
214 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
215 if (ret)
216 dev_err(dev, "failed to set link count\n");
217
218 return ret;
219 }
220
j721e_pcie_ctrl_init(struct j721e_pcie * pcie)221 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
222 {
223 struct device *dev = pcie->cdns_pcie->dev;
224 struct device_node *node = dev->of_node;
225 struct of_phandle_args args;
226 unsigned int offset = 0;
227 struct regmap *syscon;
228 int ret;
229
230 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
231 if (IS_ERR(syscon)) {
232 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
233 return PTR_ERR(syscon);
234 }
235
236 /* Do not error out to maintain old DT compatibility */
237 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
238 0, &args);
239 if (!ret)
240 offset = args.args[0];
241
242 ret = j721e_pcie_set_mode(pcie, syscon, offset);
243 if (ret < 0) {
244 dev_err(dev, "Failed to set pci mode\n");
245 return ret;
246 }
247
248 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
249 if (ret < 0) {
250 dev_err(dev, "Failed to set link speed\n");
251 return ret;
252 }
253
254 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
255 if (ret < 0) {
256 dev_err(dev, "Failed to set num-lanes\n");
257 return ret;
258 }
259
260 return 0;
261 }
262
cdns_ti_pcie_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)263 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
264 int where, int size, u32 *value)
265 {
266 if (pci_is_root_bus(bus))
267 return pci_generic_config_read32(bus, devfn, where, size,
268 value);
269
270 return pci_generic_config_read(bus, devfn, where, size, value);
271 }
272
cdns_ti_pcie_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)273 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
274 int where, int size, u32 value)
275 {
276 if (pci_is_root_bus(bus))
277 return pci_generic_config_write32(bus, devfn, where, size,
278 value);
279
280 return pci_generic_config_write(bus, devfn, where, size, value);
281 }
282
283 static struct pci_ops cdns_ti_pcie_host_ops = {
284 .map_bus = cdns_pci_map_bus,
285 .read = cdns_ti_pcie_config_read,
286 .write = cdns_ti_pcie_config_write,
287 };
288
289 static const struct j721e_pcie_data j721e_pcie_rc_data = {
290 .mode = PCI_MODE_RC,
291 .quirk_retrain_flag = true,
292 .byte_access_allowed = false,
293 .linkdown_irq_regfield = LINK_DOWN,
294 };
295
296 static const struct j721e_pcie_data j721e_pcie_ep_data = {
297 .mode = PCI_MODE_EP,
298 .linkdown_irq_regfield = LINK_DOWN,
299 };
300
301 static const struct j721e_pcie_data j7200_pcie_rc_data = {
302 .mode = PCI_MODE_RC,
303 .quirk_detect_quiet_flag = true,
304 .linkdown_irq_regfield = J7200_LINK_DOWN,
305 .byte_access_allowed = true,
306 };
307
308 static const struct j721e_pcie_data j7200_pcie_ep_data = {
309 .mode = PCI_MODE_EP,
310 .quirk_detect_quiet_flag = true,
311 .quirk_disable_flr = true,
312 };
313
314 static const struct j721e_pcie_data am64_pcie_rc_data = {
315 .mode = PCI_MODE_RC,
316 .linkdown_irq_regfield = J7200_LINK_DOWN,
317 .byte_access_allowed = true,
318 };
319
320 static const struct j721e_pcie_data am64_pcie_ep_data = {
321 .mode = PCI_MODE_EP,
322 .linkdown_irq_regfield = J7200_LINK_DOWN,
323 };
324
325 static const struct of_device_id of_j721e_pcie_match[] = {
326 {
327 .compatible = "ti,j721e-pcie-host",
328 .data = &j721e_pcie_rc_data,
329 },
330 {
331 .compatible = "ti,j721e-pcie-ep",
332 .data = &j721e_pcie_ep_data,
333 },
334 {
335 .compatible = "ti,j7200-pcie-host",
336 .data = &j7200_pcie_rc_data,
337 },
338 {
339 .compatible = "ti,j7200-pcie-ep",
340 .data = &j7200_pcie_ep_data,
341 },
342 {
343 .compatible = "ti,am64-pcie-host",
344 .data = &am64_pcie_rc_data,
345 },
346 {
347 .compatible = "ti,am64-pcie-ep",
348 .data = &am64_pcie_ep_data,
349 },
350 {},
351 };
352
j721e_pcie_probe(struct platform_device * pdev)353 static int j721e_pcie_probe(struct platform_device *pdev)
354 {
355 struct device *dev = &pdev->dev;
356 struct device_node *node = dev->of_node;
357 struct pci_host_bridge *bridge;
358 const struct j721e_pcie_data *data;
359 struct cdns_pcie *cdns_pcie;
360 struct j721e_pcie *pcie;
361 struct cdns_pcie_rc *rc = NULL;
362 struct cdns_pcie_ep *ep = NULL;
363 struct gpio_desc *gpiod;
364 void __iomem *base;
365 struct clk *clk;
366 u32 num_lanes;
367 u32 mode;
368 int ret;
369 int irq;
370
371 data = of_device_get_match_data(dev);
372 if (!data)
373 return -EINVAL;
374
375 mode = (u32)data->mode;
376
377 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
378 if (!pcie)
379 return -ENOMEM;
380
381 switch (mode) {
382 case PCI_MODE_RC:
383 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))
384 return -ENODEV;
385
386 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
387 if (!bridge)
388 return -ENOMEM;
389
390 if (!data->byte_access_allowed)
391 bridge->ops = &cdns_ti_pcie_host_ops;
392 rc = pci_host_bridge_priv(bridge);
393 rc->quirk_retrain_flag = data->quirk_retrain_flag;
394 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
395
396 cdns_pcie = &rc->pcie;
397 cdns_pcie->dev = dev;
398 cdns_pcie->ops = &j721e_pcie_ops;
399 pcie->cdns_pcie = cdns_pcie;
400 break;
401 case PCI_MODE_EP:
402 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))
403 return -ENODEV;
404
405 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
406 if (!ep)
407 return -ENOMEM;
408
409 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
410 ep->quirk_disable_flr = data->quirk_disable_flr;
411
412 cdns_pcie = &ep->pcie;
413 cdns_pcie->dev = dev;
414 cdns_pcie->ops = &j721e_pcie_ops;
415 pcie->cdns_pcie = cdns_pcie;
416 break;
417 default:
418 dev_err(dev, "INVALID device type %d\n", mode);
419 return 0;
420 }
421
422 pcie->mode = mode;
423 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
424
425 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
426 if (IS_ERR(base))
427 return PTR_ERR(base);
428 pcie->intd_cfg_base = base;
429
430 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
431 if (IS_ERR(base))
432 return PTR_ERR(base);
433 pcie->user_cfg_base = base;
434
435 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
436 if (ret || num_lanes > MAX_LANES)
437 num_lanes = 1;
438 pcie->num_lanes = num_lanes;
439
440 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
441 return -EINVAL;
442
443 irq = platform_get_irq_byname(pdev, "link_state");
444 if (irq < 0)
445 return irq;
446
447 dev_set_drvdata(dev, pcie);
448 pm_runtime_enable(dev);
449 ret = pm_runtime_get_sync(dev);
450 if (ret < 0) {
451 dev_err(dev, "pm_runtime_get_sync failed\n");
452 goto err_get_sync;
453 }
454
455 ret = j721e_pcie_ctrl_init(pcie);
456 if (ret < 0) {
457 dev_err(dev, "pm_runtime_get_sync failed\n");
458 goto err_get_sync;
459 }
460
461 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
462 "j721e-pcie-link-down-irq", pcie);
463 if (ret < 0) {
464 dev_err(dev, "failed to request link state IRQ %d\n", irq);
465 goto err_get_sync;
466 }
467
468 j721e_pcie_config_link_irq(pcie);
469
470 switch (mode) {
471 case PCI_MODE_RC:
472 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
473 if (IS_ERR(gpiod)) {
474 ret = PTR_ERR(gpiod);
475 if (ret != -EPROBE_DEFER)
476 dev_err(dev, "Failed to get reset GPIO\n");
477 goto err_get_sync;
478 }
479
480 ret = cdns_pcie_init_phy(dev, cdns_pcie);
481 if (ret) {
482 dev_err(dev, "Failed to init phy\n");
483 goto err_get_sync;
484 }
485
486 clk = devm_clk_get_optional(dev, "pcie_refclk");
487 if (IS_ERR(clk)) {
488 ret = PTR_ERR(clk);
489 dev_err(dev, "failed to get pcie_refclk\n");
490 goto err_pcie_setup;
491 }
492
493 ret = clk_prepare_enable(clk);
494 if (ret) {
495 dev_err(dev, "failed to enable pcie_refclk\n");
496 goto err_pcie_setup;
497 }
498 pcie->refclk = clk;
499
500 /*
501 * "Power Sequencing and Reset Signal Timings" table in
502 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
503 * indicates PERST# should be deasserted after minimum of 100us
504 * once REFCLK is stable. The REFCLK to the connector in RC
505 * mode is selected while enabling the PHY. So deassert PERST#
506 * after 100 us.
507 */
508 if (gpiod) {
509 usleep_range(100, 200);
510 gpiod_set_value_cansleep(gpiod, 1);
511 }
512
513 ret = cdns_pcie_host_setup(rc);
514 if (ret < 0) {
515 clk_disable_unprepare(pcie->refclk);
516 goto err_pcie_setup;
517 }
518
519 break;
520 case PCI_MODE_EP:
521 ret = cdns_pcie_init_phy(dev, cdns_pcie);
522 if (ret) {
523 dev_err(dev, "Failed to init phy\n");
524 goto err_get_sync;
525 }
526
527 ret = cdns_pcie_ep_setup(ep);
528 if (ret < 0)
529 goto err_pcie_setup;
530
531 break;
532 }
533
534 return 0;
535
536 err_pcie_setup:
537 cdns_pcie_disable_phy(cdns_pcie);
538
539 err_get_sync:
540 pm_runtime_put(dev);
541 pm_runtime_disable(dev);
542
543 return ret;
544 }
545
j721e_pcie_remove(struct platform_device * pdev)546 static int j721e_pcie_remove(struct platform_device *pdev)
547 {
548 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
549 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
550 struct device *dev = &pdev->dev;
551
552 clk_disable_unprepare(pcie->refclk);
553 cdns_pcie_disable_phy(cdns_pcie);
554 pm_runtime_put(dev);
555 pm_runtime_disable(dev);
556
557 return 0;
558 }
559
560 static struct platform_driver j721e_pcie_driver = {
561 .probe = j721e_pcie_probe,
562 .remove = j721e_pcie_remove,
563 .driver = {
564 .name = "j721e-pcie",
565 .of_match_table = of_j721e_pcie_match,
566 .suppress_bind_attrs = true,
567 },
568 };
569 builtin_platform_driver(j721e_pcie_driver);
570
