1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Goramo PCI200SYN synchronous serial card driver for Linux
4 *
5 * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
8 *
9 * Sources of information:
10 * Hitachi HD64572 SCA-II User's Manual
11 * PLX Technology Inc. PCI9052 Data Book
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/capability.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/in.h>
23 #include <linux/string.h>
24 #include <linux/errno.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/netdevice.h>
28 #include <linux/hdlc.h>
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <asm/io.h>
32
33 #include "hd64572.h"
34
35 #undef DEBUG_PKT
36 #define DEBUG_RINGS
37
38 #define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */
39 #define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */
40 #define MAX_TX_BUFFERS 10
41
42 static int pci_clock_freq = 33000000;
43 #define CLOCK_BASE pci_clock_freq
44
45 /* PLX PCI9052 local configuration and shared runtime registers.
46 * This structure can be used to access 9052 registers (memory mapped).
47 */
48 typedef struct {
49 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
50 u32 loc_rom_range; /* 10h : Local ROM Range */
51 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
52 u32 loc_rom_base; /* 24h : Local ROM Base */
53 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
54 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
55 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
56 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
57 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
58 } plx9052;
59
60 typedef struct port_s {
61 struct napi_struct napi;
62 struct net_device *netdev;
63 struct card_s *card;
64 spinlock_t lock; /* TX lock */
65 sync_serial_settings settings;
66 int rxpart; /* partial frame received, next frame invalid*/
67 unsigned short encoding;
68 unsigned short parity;
69 u16 rxin; /* rx ring buffer 'in' pointer */
70 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
71 u16 txlast;
72 u8 rxs, txs, tmc; /* SCA registers */
73 u8 chan; /* physical port # - 0 or 1 */
74 } port_t;
75
76 typedef struct card_s {
77 u8 __iomem *rambase; /* buffer memory base (virtual) */
78 u8 __iomem *scabase; /* SCA memory base (virtual) */
79 plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
80 u16 rx_ring_buffers; /* number of buffers in a ring */
81 u16 tx_ring_buffers;
82 u16 buff_offset; /* offset of first buffer of first channel */
83 u8 irq; /* interrupt request level */
84
85 port_t ports[2];
86 } card_t;
87
88 #define get_port(card, port) (&(card)->ports[port])
89 #define sca_flush(card) (sca_in(IER0, card))
90
new_memcpy_toio(char __iomem * dest,char * src,int length)91 static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
92 {
93 int len;
94
95 do {
96 len = length > 256 ? 256 : length;
97 memcpy_toio(dest, src, len);
98 dest += len;
99 src += len;
100 length -= len;
101 readb(dest);
102 } while (len);
103 }
104
105 #undef memcpy_toio
106 #define memcpy_toio new_memcpy_toio
107
108 #include "hd64572.c"
109
pci200_set_iface(port_t * port)110 static void pci200_set_iface(port_t *port)
111 {
112 card_t *card = port->card;
113 u16 msci = get_msci(port);
114 u8 rxs = port->rxs & CLK_BRG_MASK;
115 u8 txs = port->txs & CLK_BRG_MASK;
116
117 sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
118 port->card);
119 switch (port->settings.clock_type) {
120 case CLOCK_INT:
121 rxs |= CLK_BRG; /* BRG output */
122 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
123 break;
124
125 case CLOCK_TXINT:
126 rxs |= CLK_LINE; /* RXC input */
127 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
128 break;
129
130 case CLOCK_TXFROMRX:
131 rxs |= CLK_LINE; /* RXC input */
132 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
133 break;
134
135 default: /* EXTernal clock */
136 rxs |= CLK_LINE; /* RXC input */
137 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
138 break;
139 }
140
141 port->rxs = rxs;
142 port->txs = txs;
143 sca_out(rxs, msci + RXS, card);
144 sca_out(txs, msci + TXS, card);
145 sca_set_port(port);
146 }
147
pci200_open(struct net_device * dev)148 static int pci200_open(struct net_device *dev)
149 {
150 port_t *port = dev_to_port(dev);
151 int result = hdlc_open(dev);
152
153 if (result)
154 return result;
155
156 sca_open(dev);
157 pci200_set_iface(port);
158 sca_flush(port->card);
159 return 0;
160 }
161
pci200_close(struct net_device * dev)162 static int pci200_close(struct net_device *dev)
163 {
164 sca_close(dev);
165 sca_flush(dev_to_port(dev)->card);
166 hdlc_close(dev);
167 return 0;
168 }
169
pci200_siocdevprivate(struct net_device * dev,struct ifreq * ifr,void __user * data,int cmd)170 static int pci200_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
171 void __user *data, int cmd)
172 {
173 #ifdef DEBUG_RINGS
174 if (cmd == SIOCDEVPRIVATE) {
175 sca_dump_rings(dev);
176 return 0;
177 }
178 #endif
179 return -EOPNOTSUPP;
180 }
181
pci200_ioctl(struct net_device * dev,struct if_settings * ifs)182 static int pci200_ioctl(struct net_device *dev, struct if_settings *ifs)
183 {
184 const size_t size = sizeof(sync_serial_settings);
185 sync_serial_settings new_line;
186 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
187 port_t *port = dev_to_port(dev);
188
189 switch (ifs->type) {
190 case IF_GET_IFACE:
191 ifs->type = IF_IFACE_V35;
192 if (ifs->size < size) {
193 ifs->size = size; /* data size wanted */
194 return -ENOBUFS;
195 }
196 if (copy_to_user(line, &port->settings, size))
197 return -EFAULT;
198 return 0;
199
200 case IF_IFACE_V35:
201 case IF_IFACE_SYNC_SERIAL:
202 if (!capable(CAP_NET_ADMIN))
203 return -EPERM;
204
205 if (copy_from_user(&new_line, line, size))
206 return -EFAULT;
207
208 if (new_line.clock_type != CLOCK_EXT &&
209 new_line.clock_type != CLOCK_TXFROMRX &&
210 new_line.clock_type != CLOCK_INT &&
211 new_line.clock_type != CLOCK_TXINT)
212 return -EINVAL; /* No such clock setting */
213
214 if (new_line.loopback != 0 && new_line.loopback != 1)
215 return -EINVAL;
216
217 memcpy(&port->settings, &new_line, size); /* Update settings */
218 pci200_set_iface(port);
219 sca_flush(port->card);
220 return 0;
221
222 default:
223 return hdlc_ioctl(dev, ifs);
224 }
225 }
226
pci200_pci_remove_one(struct pci_dev * pdev)227 static void pci200_pci_remove_one(struct pci_dev *pdev)
228 {
229 int i;
230 card_t *card = pci_get_drvdata(pdev);
231
232 for (i = 0; i < 2; i++)
233 if (card->ports[i].card)
234 unregister_hdlc_device(card->ports[i].netdev);
235
236 if (card->irq)
237 free_irq(card->irq, card);
238
239 if (card->rambase)
240 iounmap(card->rambase);
241 if (card->scabase)
242 iounmap(card->scabase);
243 if (card->plxbase)
244 iounmap(card->plxbase);
245
246 pci_release_regions(pdev);
247 pci_disable_device(pdev);
248 if (card->ports[0].netdev)
249 free_netdev(card->ports[0].netdev);
250 if (card->ports[1].netdev)
251 free_netdev(card->ports[1].netdev);
252 kfree(card);
253 }
254
255 static const struct net_device_ops pci200_ops = {
256 .ndo_open = pci200_open,
257 .ndo_stop = pci200_close,
258 .ndo_start_xmit = hdlc_start_xmit,
259 .ndo_siocwandev = pci200_ioctl,
260 .ndo_siocdevprivate = pci200_siocdevprivate,
261 };
262
pci200_pci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)263 static int pci200_pci_init_one(struct pci_dev *pdev,
264 const struct pci_device_id *ent)
265 {
266 card_t *card;
267 u32 __iomem *p;
268 int i;
269 u32 ramsize;
270 u32 ramphys; /* buffer memory base */
271 u32 scaphys; /* SCA memory base */
272 u32 plxphys; /* PLX registers memory base */
273
274 i = pci_enable_device(pdev);
275 if (i)
276 return i;
277
278 i = pci_request_regions(pdev, "PCI200SYN");
279 if (i) {
280 pci_disable_device(pdev);
281 return i;
282 }
283
284 card = kzalloc(sizeof(card_t), GFP_KERNEL);
285 if (!card) {
286 pci_release_regions(pdev);
287 pci_disable_device(pdev);
288 return -ENOBUFS;
289 }
290 pci_set_drvdata(pdev, card);
291 card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
292 card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
293 if (!card->ports[0].netdev || !card->ports[1].netdev) {
294 pr_err("unable to allocate memory\n");
295 pci200_pci_remove_one(pdev);
296 return -ENOMEM;
297 }
298
299 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
300 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
301 pci_resource_len(pdev, 3) < 16384) {
302 pr_err("invalid card EEPROM parameters\n");
303 pci200_pci_remove_one(pdev);
304 return -EFAULT;
305 }
306
307 plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
308 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
309
310 scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
311 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
312
313 ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
314 card->rambase = pci_ioremap_bar(pdev, 3);
315
316 if (!card->plxbase || !card->scabase || !card->rambase) {
317 pr_err("ioremap() failed\n");
318 pci200_pci_remove_one(pdev);
319 return -EFAULT;
320 }
321
322 /* Reset PLX */
323 p = &card->plxbase->init_ctrl;
324 writel(readl(p) | 0x40000000, p);
325 readl(p); /* Flush the write - do not use sca_flush */
326 udelay(1);
327
328 writel(readl(p) & ~0x40000000, p);
329 readl(p); /* Flush the write - do not use sca_flush */
330 udelay(1);
331
332 ramsize = sca_detect_ram(card, card->rambase,
333 pci_resource_len(pdev, 3));
334
335 /* number of TX + RX buffers for one port - this is dual port card */
336 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
337 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
338 card->rx_ring_buffers = i - card->tx_ring_buffers;
339
340 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
341 card->rx_ring_buffers);
342
343 pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
344 ramsize / 1024, ramphys,
345 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
346
347 if (card->tx_ring_buffers < 1) {
348 pr_err("RAM test failed\n");
349 pci200_pci_remove_one(pdev);
350 return -EFAULT;
351 }
352
353 /* Enable interrupts on the PCI bridge */
354 p = &card->plxbase->intr_ctrl_stat;
355 writew(readw(p) | 0x0040, p);
356
357 /* Allocate IRQ */
358 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
359 pr_warn("could not allocate IRQ%d\n", pdev->irq);
360 pci200_pci_remove_one(pdev);
361 return -EBUSY;
362 }
363 card->irq = pdev->irq;
364
365 sca_init(card, 0);
366
367 for (i = 0; i < 2; i++) {
368 port_t *port = &card->ports[i];
369 struct net_device *dev = port->netdev;
370 hdlc_device *hdlc = dev_to_hdlc(dev);
371
372 port->chan = i;
373
374 spin_lock_init(&port->lock);
375 dev->irq = card->irq;
376 dev->mem_start = ramphys;
377 dev->mem_end = ramphys + ramsize - 1;
378 dev->tx_queue_len = 50;
379 dev->netdev_ops = &pci200_ops;
380 hdlc->attach = sca_attach;
381 hdlc->xmit = sca_xmit;
382 port->settings.clock_type = CLOCK_EXT;
383 port->card = card;
384 sca_init_port(port);
385 if (register_hdlc_device(dev)) {
386 pr_err("unable to register hdlc device\n");
387 port->card = NULL;
388 pci200_pci_remove_one(pdev);
389 return -ENOBUFS;
390 }
391
392 netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
393 }
394
395 sca_flush(card);
396 return 0;
397 }
398
399 static const struct pci_device_id pci200_pci_tbl[] = {
400 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
401 PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
402 { 0, }
403 };
404
405 static struct pci_driver pci200_pci_driver = {
406 .name = "PCI200SYN",
407 .id_table = pci200_pci_tbl,
408 .probe = pci200_pci_init_one,
409 .remove = pci200_pci_remove_one,
410 };
411
pci200_init_module(void)412 static int __init pci200_init_module(void)
413 {
414 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
415 pr_err("Invalid PCI clock frequency\n");
416 return -EINVAL;
417 }
418 return pci_register_driver(&pci200_pci_driver);
419 }
420
pci200_cleanup_module(void)421 static void __exit pci200_cleanup_module(void)
422 {
423 pci_unregister_driver(&pci200_pci_driver);
424 }
425
426 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
427 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
428 MODULE_LICENSE("GPL v2");
429 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
430 module_param(pci_clock_freq, int, 0444);
431 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
432 module_init(pci200_init_module);
433 module_exit(pci200_cleanup_module);
434
