1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/pcs/pcs-xpcs.h>
11 #include <linux/mdio.h>
12 #include <linux/phylink.h>
13 #include <linux/workqueue.h>
14 #include "pcs-xpcs.h"
15
16 #define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
18
19 static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
28 };
29
30 static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
35 };
36
37 static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
65 };
66
67 static const int xpcs_10gbaser_features[] = {
68 ETHTOOL_LINK_MODE_Pause_BIT,
69 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
70 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
71 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
72 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
73 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
75 };
76
77 static const int xpcs_sgmii_features[] = {
78 ETHTOOL_LINK_MODE_Pause_BIT,
79 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
80 ETHTOOL_LINK_MODE_Autoneg_BIT,
81 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
82 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
83 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
84 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
85 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
86 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
87 __ETHTOOL_LINK_MODE_MASK_NBITS,
88 };
89
90 static const int xpcs_1000basex_features[] = {
91 ETHTOOL_LINK_MODE_Pause_BIT,
92 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
93 ETHTOOL_LINK_MODE_Autoneg_BIT,
94 ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
95 __ETHTOOL_LINK_MODE_MASK_NBITS,
96 };
97
98 static const int xpcs_2500basex_features[] = {
99 ETHTOOL_LINK_MODE_Pause_BIT,
100 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
101 ETHTOOL_LINK_MODE_Autoneg_BIT,
102 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
103 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
104 __ETHTOOL_LINK_MODE_MASK_NBITS,
105 };
106
107 static const phy_interface_t xpcs_usxgmii_interfaces[] = {
108 PHY_INTERFACE_MODE_USXGMII,
109 };
110
111 static const phy_interface_t xpcs_10gkr_interfaces[] = {
112 PHY_INTERFACE_MODE_10GKR,
113 };
114
115 static const phy_interface_t xpcs_xlgmii_interfaces[] = {
116 PHY_INTERFACE_MODE_XLGMII,
117 };
118
119 static const phy_interface_t xpcs_10gbaser_interfaces[] = {
120 PHY_INTERFACE_MODE_10GBASER,
121 };
122
123 static const phy_interface_t xpcs_sgmii_interfaces[] = {
124 PHY_INTERFACE_MODE_SGMII,
125 };
126
127 static const phy_interface_t xpcs_1000basex_interfaces[] = {
128 PHY_INTERFACE_MODE_1000BASEX,
129 };
130
131 static const phy_interface_t xpcs_2500basex_interfaces[] = {
132 PHY_INTERFACE_MODE_2500BASEX,
133 PHY_INTERFACE_MODE_MAX,
134 };
135
136 enum {
137 DW_XPCS_USXGMII,
138 DW_XPCS_10GKR,
139 DW_XPCS_XLGMII,
140 DW_XPCS_10GBASER,
141 DW_XPCS_SGMII,
142 DW_XPCS_1000BASEX,
143 DW_XPCS_2500BASEX,
144 DW_XPCS_INTERFACE_MAX,
145 };
146
147 struct xpcs_compat {
148 const int *supported;
149 const phy_interface_t *interface;
150 int num_interfaces;
151 int an_mode;
152 int (*pma_config)(struct dw_xpcs *xpcs);
153 };
154
155 struct xpcs_id {
156 u32 id;
157 u32 mask;
158 const struct xpcs_compat *compat;
159 };
160
xpcs_find_compat(const struct xpcs_id * id,phy_interface_t interface)161 static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
162 phy_interface_t interface)
163 {
164 int i, j;
165
166 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
167 const struct xpcs_compat *compat = &id->compat[i];
168
169 for (j = 0; j < compat->num_interfaces; j++)
170 if (compat->interface[j] == interface)
171 return compat;
172 }
173
174 return NULL;
175 }
176
xpcs_get_an_mode(struct dw_xpcs * xpcs,phy_interface_t interface)177 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
178 {
179 const struct xpcs_compat *compat;
180
181 compat = xpcs_find_compat(xpcs->id, interface);
182 if (!compat)
183 return -ENODEV;
184
185 return compat->an_mode;
186 }
187 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
188
__xpcs_linkmode_supported(const struct xpcs_compat * compat,enum ethtool_link_mode_bit_indices linkmode)189 static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
190 enum ethtool_link_mode_bit_indices linkmode)
191 {
192 int i;
193
194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
195 if (compat->supported[i] == linkmode)
196 return true;
197
198 return false;
199 }
200
201 #define xpcs_linkmode_supported(compat, mode) \
202 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
203
xpcs_read(struct dw_xpcs * xpcs,int dev,u32 reg)204 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
205 {
206 return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
207 }
208
xpcs_write(struct dw_xpcs * xpcs,int dev,u32 reg,u16 val)209 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
210 {
211 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
212 }
213
xpcs_modify_changed(struct dw_xpcs * xpcs,int dev,u32 reg,u16 mask,u16 set)214 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
215 u16 mask, u16 set)
216 {
217 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
218 }
219
xpcs_read_vendor(struct dw_xpcs * xpcs,int dev,u32 reg)220 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
221 {
222 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
223 }
224
xpcs_write_vendor(struct dw_xpcs * xpcs,int dev,int reg,u16 val)225 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
226 u16 val)
227 {
228 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
229 }
230
xpcs_read_vpcs(struct dw_xpcs * xpcs,int reg)231 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
232 {
233 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
234 }
235
xpcs_write_vpcs(struct dw_xpcs * xpcs,int reg,u16 val)236 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
237 {
238 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
239 }
240
xpcs_dev_flag(struct dw_xpcs * xpcs)241 static int xpcs_dev_flag(struct dw_xpcs *xpcs)
242 {
243 int ret, oui;
244
245 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1);
246 if (ret < 0)
247 return ret;
248
249 oui = ret;
250
251 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2);
252 if (ret < 0)
253 return ret;
254
255 ret = (ret >> 10) & 0x3F;
256 oui |= ret << 16;
257
258 if (oui == DW_OUI_WX)
259 xpcs->dev_flag = DW_DEV_TXGBE;
260
261 return 0;
262 }
263
xpcs_poll_reset(struct dw_xpcs * xpcs,int dev)264 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
265 {
266 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
267 unsigned int retries = 12;
268 int ret;
269
270 do {
271 msleep(50);
272 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
273 if (ret < 0)
274 return ret;
275 } while (ret & MDIO_CTRL1_RESET && --retries);
276
277 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
278 }
279
xpcs_soft_reset(struct dw_xpcs * xpcs,const struct xpcs_compat * compat)280 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
281 const struct xpcs_compat *compat)
282 {
283 int ret, dev;
284
285 switch (compat->an_mode) {
286 case DW_AN_C73:
287 case DW_10GBASER:
288 dev = MDIO_MMD_PCS;
289 break;
290 case DW_AN_C37_SGMII:
291 case DW_2500BASEX:
292 case DW_AN_C37_1000BASEX:
293 dev = MDIO_MMD_VEND2;
294 break;
295 default:
296 return -1;
297 }
298
299 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
300 if (ret < 0)
301 return ret;
302
303 return xpcs_poll_reset(xpcs, dev);
304 }
305
306 #define xpcs_warn(__xpcs, __state, __args...) \
307 ({ \
308 if ((__state)->link) \
309 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
310 })
311
xpcs_read_fault_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,u16 pcs_stat1)312 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
313 struct phylink_link_state *state,
314 u16 pcs_stat1)
315 {
316 int ret;
317
318 if (pcs_stat1 & MDIO_STAT1_FAULT) {
319 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
320 return -EFAULT;
321 }
322
323 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
324 if (ret < 0)
325 return ret;
326
327 if (ret & MDIO_STAT2_RXFAULT)
328 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
329 if (ret & MDIO_STAT2_TXFAULT)
330 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
331
332 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
333 if (ret < 0)
334 return ret;
335
336 if (ret & DW_RXFIFO_ERR) {
337 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
338 return -EFAULT;
339 }
340
341 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
342 if (ret < 0)
343 return ret;
344
345 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
346 xpcs_warn(xpcs, state, "Link is not locked!\n");
347
348 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
349 if (ret < 0)
350 return ret;
351
352 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
353 xpcs_warn(xpcs, state, "Link has errors!\n");
354 return -EFAULT;
355 }
356
357 return 0;
358 }
359
xpcs_config_usxgmii(struct dw_xpcs * xpcs,int speed)360 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
361 {
362 int ret, speed_sel;
363
364 switch (speed) {
365 case SPEED_10:
366 speed_sel = DW_USXGMII_10;
367 break;
368 case SPEED_100:
369 speed_sel = DW_USXGMII_100;
370 break;
371 case SPEED_1000:
372 speed_sel = DW_USXGMII_1000;
373 break;
374 case SPEED_2500:
375 speed_sel = DW_USXGMII_2500;
376 break;
377 case SPEED_5000:
378 speed_sel = DW_USXGMII_5000;
379 break;
380 case SPEED_10000:
381 speed_sel = DW_USXGMII_10000;
382 break;
383 default:
384 /* Nothing to do here */
385 return;
386 }
387
388 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
389 if (ret < 0)
390 goto out;
391
392 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
393 if (ret < 0)
394 goto out;
395
396 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
397 if (ret < 0)
398 goto out;
399
400 ret &= ~DW_USXGMII_SS_MASK;
401 ret |= speed_sel | DW_USXGMII_FULL;
402
403 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
404 if (ret < 0)
405 goto out;
406
407 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
408 if (ret < 0)
409 goto out;
410
411 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
412 if (ret < 0)
413 goto out;
414
415 return;
416
417 out:
418 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
419 }
420
_xpcs_config_aneg_c73(struct dw_xpcs * xpcs,const struct xpcs_compat * compat)421 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
422 const struct xpcs_compat *compat)
423 {
424 int ret, adv;
425
426 /* By default, in USXGMII mode XPCS operates at 10G baud and
427 * replicates data to achieve lower speeds. Hereby, in this
428 * default configuration we need to advertise all supported
429 * modes and not only the ones we want to use.
430 */
431
432 /* SR_AN_ADV3 */
433 adv = 0;
434 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
435 adv |= DW_C73_2500KX;
436
437 /* TODO: 5000baseKR */
438
439 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
440 if (ret < 0)
441 return ret;
442
443 /* SR_AN_ADV2 */
444 adv = 0;
445 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
446 adv |= DW_C73_1000KX;
447 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
448 adv |= DW_C73_10000KX4;
449 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
450 adv |= DW_C73_10000KR;
451
452 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
453 if (ret < 0)
454 return ret;
455
456 /* SR_AN_ADV1 */
457 adv = DW_C73_AN_ADV_SF;
458 if (xpcs_linkmode_supported(compat, Pause))
459 adv |= DW_C73_PAUSE;
460 if (xpcs_linkmode_supported(compat, Asym_Pause))
461 adv |= DW_C73_ASYM_PAUSE;
462
463 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
464 }
465
xpcs_config_aneg_c73(struct dw_xpcs * xpcs,const struct xpcs_compat * compat)466 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
467 const struct xpcs_compat *compat)
468 {
469 int ret;
470
471 ret = _xpcs_config_aneg_c73(xpcs, compat);
472 if (ret < 0)
473 return ret;
474
475 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
476 if (ret < 0)
477 return ret;
478
479 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
480
481 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
482 }
483
xpcs_aneg_done_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,const struct xpcs_compat * compat,u16 an_stat1)484 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
485 struct phylink_link_state *state,
486 const struct xpcs_compat *compat, u16 an_stat1)
487 {
488 int ret;
489
490 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
491 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
492 if (ret < 0)
493 return ret;
494
495 /* Check if Aneg outcome is valid */
496 if (!(ret & DW_C73_AN_ADV_SF)) {
497 xpcs_config_aneg_c73(xpcs, compat);
498 return 0;
499 }
500
501 return 1;
502 }
503
504 return 0;
505 }
506
xpcs_read_lpa_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,u16 an_stat1)507 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
508 struct phylink_link_state *state, u16 an_stat1)
509 {
510 u16 lpa[3];
511 int i, ret;
512
513 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
514 phylink_clear(state->lp_advertising, Autoneg);
515 return 0;
516 }
517
518 phylink_set(state->lp_advertising, Autoneg);
519
520 /* Read Clause 73 link partner advertisement */
521 for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
522 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
523 if (ret < 0)
524 return ret;
525
526 lpa[i] = ret;
527 }
528
529 mii_c73_mod_linkmode(state->lp_advertising, lpa);
530
531 return 0;
532 }
533
xpcs_get_max_xlgmii_speed(struct dw_xpcs * xpcs,struct phylink_link_state * state)534 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
535 struct phylink_link_state *state)
536 {
537 unsigned long *adv = state->advertising;
538 int speed = SPEED_UNKNOWN;
539 int bit;
540
541 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
542 int new_speed = SPEED_UNKNOWN;
543
544 switch (bit) {
545 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
546 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
547 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
548 new_speed = SPEED_25000;
549 break;
550 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
551 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
552 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
553 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
554 new_speed = SPEED_40000;
555 break;
556 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
557 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
558 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
559 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
560 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
561 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
562 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
563 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
564 new_speed = SPEED_50000;
565 break;
566 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
567 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
568 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
569 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
570 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
571 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
572 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
573 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
574 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
575 new_speed = SPEED_100000;
576 break;
577 default:
578 continue;
579 }
580
581 if (new_speed > speed)
582 speed = new_speed;
583 }
584
585 return speed;
586 }
587
xpcs_resolve_pma(struct dw_xpcs * xpcs,struct phylink_link_state * state)588 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
589 struct phylink_link_state *state)
590 {
591 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
592 state->duplex = DUPLEX_FULL;
593
594 switch (state->interface) {
595 case PHY_INTERFACE_MODE_10GKR:
596 state->speed = SPEED_10000;
597 break;
598 case PHY_INTERFACE_MODE_XLGMII:
599 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
600 break;
601 default:
602 state->speed = SPEED_UNKNOWN;
603 break;
604 }
605 }
606
xpcs_validate(struct phylink_pcs * pcs,unsigned long * supported,const struct phylink_link_state * state)607 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
608 const struct phylink_link_state *state)
609 {
610 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
611 const struct xpcs_compat *compat;
612 struct dw_xpcs *xpcs;
613 int i;
614
615 xpcs = phylink_pcs_to_xpcs(pcs);
616 compat = xpcs_find_compat(xpcs->id, state->interface);
617
618 /* Populate the supported link modes for this PHY interface type.
619 * FIXME: what about the port modes and autoneg bit? This masks
620 * all those away.
621 */
622 if (compat)
623 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
624 set_bit(compat->supported[i], xpcs_supported);
625
626 linkmode_and(supported, supported, xpcs_supported);
627
628 return 0;
629 }
630
xpcs_get_interfaces(struct dw_xpcs * xpcs,unsigned long * interfaces)631 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
632 {
633 int i, j;
634
635 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
636 const struct xpcs_compat *compat = &xpcs->id->compat[i];
637
638 for (j = 0; j < compat->num_interfaces; j++)
639 if (compat->interface[j] < PHY_INTERFACE_MODE_MAX)
640 __set_bit(compat->interface[j], interfaces);
641 }
642 }
643 EXPORT_SYMBOL_GPL(xpcs_get_interfaces);
644
xpcs_config_eee(struct dw_xpcs * xpcs,int mult_fact_100ns,int enable)645 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
646 {
647 int ret;
648
649 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
650 if (ret < 0)
651 return ret;
652
653 if (enable) {
654 /* Enable EEE */
655 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
656 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
657 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
658 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
659 } else {
660 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
661 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
662 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
663 DW_VR_MII_EEE_MULT_FACT_100NS);
664 }
665
666 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
667 if (ret < 0)
668 return ret;
669
670 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
671 if (ret < 0)
672 return ret;
673
674 if (enable)
675 ret |= DW_VR_MII_EEE_TRN_LPI;
676 else
677 ret &= ~DW_VR_MII_EEE_TRN_LPI;
678
679 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
680 }
681 EXPORT_SYMBOL_GPL(xpcs_config_eee);
682
xpcs_config_aneg_c37_sgmii(struct dw_xpcs * xpcs,unsigned int neg_mode)683 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
684 unsigned int neg_mode)
685 {
686 int ret, mdio_ctrl, tx_conf;
687
688 if (xpcs->dev_flag == DW_DEV_TXGBE)
689 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
690
691 /* For AN for C37 SGMII mode, the settings are :-
692 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
693 it is already enabled)
694 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
695 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
696 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
697 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
698 * speed/duplex mode change by HW after SGMII AN complete)
699 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
700 *
701 * Note: Since it is MAC side SGMII, there is no need to set
702 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
703 * PHY about the link state change after C28 AN is completed
704 * between PHY and Link Partner. There is also no need to
705 * trigger AN restart for MAC-side SGMII.
706 */
707 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
708 if (mdio_ctrl < 0)
709 return mdio_ctrl;
710
711 if (mdio_ctrl & AN_CL37_EN) {
712 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
713 mdio_ctrl & ~AN_CL37_EN);
714 if (ret < 0)
715 return ret;
716 }
717
718 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
719 if (ret < 0)
720 return ret;
721
722 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
723 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
724 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
725 DW_VR_MII_PCS_MODE_MASK);
726 if (xpcs->dev_flag == DW_DEV_TXGBE) {
727 ret |= DW_VR_MII_AN_CTRL_8BIT;
728 /* Hardware requires it to be PHY side SGMII */
729 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
730 } else {
731 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
732 }
733 ret |= tx_conf << DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
734 DW_VR_MII_TX_CONFIG_MASK;
735 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
736 if (ret < 0)
737 return ret;
738
739 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
740 if (ret < 0)
741 return ret;
742
743 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
744 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
745 else
746 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
747
748 if (xpcs->dev_flag == DW_DEV_TXGBE)
749 ret |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
750
751 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
752 if (ret < 0)
753 return ret;
754
755 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
756 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
757 mdio_ctrl | AN_CL37_EN);
758
759 return ret;
760 }
761
xpcs_config_aneg_c37_1000basex(struct dw_xpcs * xpcs,unsigned int neg_mode,const unsigned long * advertising)762 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
763 unsigned int neg_mode,
764 const unsigned long *advertising)
765 {
766 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
767 int ret, mdio_ctrl, adv;
768 bool changed = 0;
769
770 if (xpcs->dev_flag == DW_DEV_TXGBE)
771 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
772
773 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
774 * be disabled first:-
775 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
776 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
777 */
778 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
779 if (mdio_ctrl < 0)
780 return mdio_ctrl;
781
782 if (mdio_ctrl & AN_CL37_EN) {
783 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
784 mdio_ctrl & ~AN_CL37_EN);
785 if (ret < 0)
786 return ret;
787 }
788
789 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
790 if (ret < 0)
791 return ret;
792
793 ret &= ~DW_VR_MII_PCS_MODE_MASK;
794 if (!xpcs->pcs.poll)
795 ret |= DW_VR_MII_AN_INTR_EN;
796 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
797 if (ret < 0)
798 return ret;
799
800 /* Check for advertising changes and update the C45 MII ADV
801 * register accordingly.
802 */
803 adv = phylink_mii_c22_pcs_encode_advertisement(interface,
804 advertising);
805 if (adv >= 0) {
806 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
807 MII_ADVERTISE, 0xffff, adv);
808 if (ret < 0)
809 return ret;
810
811 changed = ret;
812 }
813
814 /* Clear CL37 AN complete status */
815 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
816 if (ret < 0)
817 return ret;
818
819 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
820 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
821 mdio_ctrl | AN_CL37_EN);
822 if (ret < 0)
823 return ret;
824 }
825
826 return changed;
827 }
828
xpcs_config_2500basex(struct dw_xpcs * xpcs)829 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
830 {
831 int ret;
832
833 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
834 if (ret < 0)
835 return ret;
836 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
837 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
838 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
839 if (ret < 0)
840 return ret;
841
842 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
843 if (ret < 0)
844 return ret;
845 ret &= ~AN_CL37_EN;
846 ret |= SGMII_SPEED_SS6;
847 ret &= ~SGMII_SPEED_SS13;
848 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
849 }
850
xpcs_do_config(struct dw_xpcs * xpcs,phy_interface_t interface,const unsigned long * advertising,unsigned int neg_mode)851 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
852 const unsigned long *advertising, unsigned int neg_mode)
853 {
854 const struct xpcs_compat *compat;
855 int ret;
856
857 compat = xpcs_find_compat(xpcs->id, interface);
858 if (!compat)
859 return -ENODEV;
860
861 if (xpcs->dev_flag == DW_DEV_TXGBE) {
862 ret = txgbe_xpcs_switch_mode(xpcs, interface);
863 if (ret)
864 return ret;
865 }
866
867 switch (compat->an_mode) {
868 case DW_10GBASER:
869 break;
870 case DW_AN_C73:
871 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
872 ret = xpcs_config_aneg_c73(xpcs, compat);
873 if (ret)
874 return ret;
875 }
876 break;
877 case DW_AN_C37_SGMII:
878 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
879 if (ret)
880 return ret;
881 break;
882 case DW_AN_C37_1000BASEX:
883 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
884 advertising);
885 if (ret)
886 return ret;
887 break;
888 case DW_2500BASEX:
889 ret = xpcs_config_2500basex(xpcs);
890 if (ret)
891 return ret;
892 break;
893 default:
894 return -1;
895 }
896
897 if (compat->pma_config) {
898 ret = compat->pma_config(xpcs);
899 if (ret)
900 return ret;
901 }
902
903 return 0;
904 }
905 EXPORT_SYMBOL_GPL(xpcs_do_config);
906
xpcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)907 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
908 phy_interface_t interface,
909 const unsigned long *advertising,
910 bool permit_pause_to_mac)
911 {
912 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
913
914 return xpcs_do_config(xpcs, interface, advertising, neg_mode);
915 }
916
xpcs_get_state_c73(struct dw_xpcs * xpcs,struct phylink_link_state * state,const struct xpcs_compat * compat)917 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
918 struct phylink_link_state *state,
919 const struct xpcs_compat *compat)
920 {
921 bool an_enabled;
922 int pcs_stat1;
923 int an_stat1;
924 int ret;
925
926 /* The link status bit is latching-low, so it is important to
927 * avoid unnecessary re-reads of this register to avoid missing
928 * a link-down event.
929 */
930 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
931 if (pcs_stat1 < 0) {
932 state->link = false;
933 return pcs_stat1;
934 }
935
936 /* Link needs to be read first ... */
937 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
938
939 /* ... and then we check the faults. */
940 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
941 if (ret) {
942 ret = xpcs_soft_reset(xpcs, compat);
943 if (ret)
944 return ret;
945
946 state->link = 0;
947
948 return xpcs_do_config(xpcs, state->interface, NULL,
949 PHYLINK_PCS_NEG_INBAND_ENABLED);
950 }
951
952 /* There is no point doing anything else if the link is down. */
953 if (!state->link)
954 return 0;
955
956 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
957 state->advertising);
958 if (an_enabled) {
959 /* The link status bit is latching-low, so it is important to
960 * avoid unnecessary re-reads of this register to avoid missing
961 * a link-down event.
962 */
963 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
964 if (an_stat1 < 0) {
965 state->link = false;
966 return an_stat1;
967 }
968
969 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
970 an_stat1);
971 if (!state->an_complete) {
972 state->link = false;
973 return 0;
974 }
975
976 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
977 if (ret < 0) {
978 state->link = false;
979 return ret;
980 }
981
982 phylink_resolve_c73(state);
983 } else {
984 xpcs_resolve_pma(xpcs, state);
985 }
986
987 return 0;
988 }
989
xpcs_get_state_c37_sgmii(struct dw_xpcs * xpcs,struct phylink_link_state * state)990 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
991 struct phylink_link_state *state)
992 {
993 int ret;
994
995 /* Reset link_state */
996 state->link = false;
997 state->speed = SPEED_UNKNOWN;
998 state->duplex = DUPLEX_UNKNOWN;
999 state->pause = 0;
1000
1001 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
1002 * status, speed and duplex.
1003 */
1004 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1005 if (ret < 0)
1006 return ret;
1007
1008 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
1009 int speed_value;
1010
1011 state->link = true;
1012
1013 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
1014 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
1015 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
1016 state->speed = SPEED_1000;
1017 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
1018 state->speed = SPEED_100;
1019 else
1020 state->speed = SPEED_10;
1021
1022 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
1023 state->duplex = DUPLEX_FULL;
1024 else
1025 state->duplex = DUPLEX_HALF;
1026 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1027 int speed, duplex;
1028
1029 state->link = true;
1030
1031 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1032 if (speed < 0)
1033 return speed;
1034
1035 speed &= SGMII_SPEED_SS13 | SGMII_SPEED_SS6;
1036 if (speed == SGMII_SPEED_SS6)
1037 state->speed = SPEED_1000;
1038 else if (speed == SGMII_SPEED_SS13)
1039 state->speed = SPEED_100;
1040 else if (speed == 0)
1041 state->speed = SPEED_10;
1042
1043 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
1044 if (duplex < 0)
1045 return duplex;
1046
1047 if (duplex & DW_FULL_DUPLEX)
1048 state->duplex = DUPLEX_FULL;
1049 else if (duplex & DW_HALF_DUPLEX)
1050 state->duplex = DUPLEX_HALF;
1051
1052 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
1053 }
1054
1055 return 0;
1056 }
1057
xpcs_get_state_c37_1000basex(struct dw_xpcs * xpcs,struct phylink_link_state * state)1058 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
1059 struct phylink_link_state *state)
1060 {
1061 int lpa, bmsr;
1062
1063 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1064 state->advertising)) {
1065 /* Reset link state */
1066 state->link = false;
1067
1068 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
1069 if (lpa < 0 || lpa & LPA_RFAULT)
1070 return lpa;
1071
1072 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1073 if (bmsr < 0)
1074 return bmsr;
1075
1076 /* Clear AN complete interrupt */
1077 if (!xpcs->pcs.poll) {
1078 int an_intr;
1079
1080 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1081 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1082 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR;
1083 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr);
1084 }
1085 }
1086
1087 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
1088 }
1089
1090 return 0;
1091 }
1092
xpcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)1093 static void xpcs_get_state(struct phylink_pcs *pcs,
1094 struct phylink_link_state *state)
1095 {
1096 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1097 const struct xpcs_compat *compat;
1098 int ret;
1099
1100 compat = xpcs_find_compat(xpcs->id, state->interface);
1101 if (!compat)
1102 return;
1103
1104 switch (compat->an_mode) {
1105 case DW_10GBASER:
1106 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1107 break;
1108 case DW_AN_C73:
1109 ret = xpcs_get_state_c73(xpcs, state, compat);
1110 if (ret) {
1111 pr_err("xpcs_get_state_c73 returned %pe\n",
1112 ERR_PTR(ret));
1113 return;
1114 }
1115 break;
1116 case DW_AN_C37_SGMII:
1117 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1118 if (ret) {
1119 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
1120 ERR_PTR(ret));
1121 }
1122 break;
1123 case DW_AN_C37_1000BASEX:
1124 ret = xpcs_get_state_c37_1000basex(xpcs, state);
1125 if (ret) {
1126 pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
1127 ERR_PTR(ret));
1128 }
1129 break;
1130 default:
1131 return;
1132 }
1133 }
1134
xpcs_link_up_sgmii(struct dw_xpcs * xpcs,unsigned int neg_mode,int speed,int duplex)1135 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode,
1136 int speed, int duplex)
1137 {
1138 int val, ret;
1139
1140 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1141 return;
1142
1143 val = mii_bmcr_encode_fixed(speed, duplex);
1144 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1145 if (ret)
1146 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1147 }
1148
xpcs_link_up_1000basex(struct dw_xpcs * xpcs,unsigned int neg_mode,int speed,int duplex)1149 static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode,
1150 int speed, int duplex)
1151 {
1152 int val, ret;
1153
1154 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1155 return;
1156
1157 switch (speed) {
1158 case SPEED_1000:
1159 val = BMCR_SPEED1000;
1160 break;
1161 case SPEED_100:
1162 case SPEED_10:
1163 default:
1164 pr_err("%s: speed = %d\n", __func__, speed);
1165 return;
1166 }
1167
1168 if (duplex == DUPLEX_FULL)
1169 val |= BMCR_FULLDPLX;
1170 else
1171 pr_err("%s: half duplex not supported\n", __func__);
1172
1173 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1174 if (ret)
1175 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1176 }
1177
xpcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)1178 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
1179 phy_interface_t interface, int speed, int duplex)
1180 {
1181 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1182
1183 if (interface == PHY_INTERFACE_MODE_USXGMII)
1184 return xpcs_config_usxgmii(xpcs, speed);
1185 if (interface == PHY_INTERFACE_MODE_SGMII)
1186 return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex);
1187 if (interface == PHY_INTERFACE_MODE_1000BASEX)
1188 return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex);
1189 }
1190 EXPORT_SYMBOL_GPL(xpcs_link_up);
1191
xpcs_an_restart(struct phylink_pcs * pcs)1192 static void xpcs_an_restart(struct phylink_pcs *pcs)
1193 {
1194 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1195 int ret;
1196
1197 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1198 if (ret >= 0) {
1199 ret |= BMCR_ANRESTART;
1200 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
1201 }
1202 }
1203
xpcs_get_id(struct dw_xpcs * xpcs)1204 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
1205 {
1206 int ret;
1207 u32 id;
1208
1209 /* First, search C73 PCS using PCS MMD */
1210 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1211 if (ret < 0)
1212 return 0xffffffff;
1213
1214 id = ret << 16;
1215
1216 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1217 if (ret < 0)
1218 return 0xffffffff;
1219
1220 /* If Device IDs are not all zeros or all ones,
1221 * we found C73 AN-type device
1222 */
1223 if ((id | ret) && (id | ret) != 0xffffffff)
1224 return id | ret;
1225
1226 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1227 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1228 if (ret < 0)
1229 return 0xffffffff;
1230
1231 id = ret << 16;
1232
1233 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1234 if (ret < 0)
1235 return 0xffffffff;
1236
1237 /* If Device IDs are not all zeros, we found C37 AN-type device */
1238 if (id | ret)
1239 return id | ret;
1240
1241 return 0xffffffff;
1242 }
1243
1244 static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1245 [DW_XPCS_USXGMII] = {
1246 .supported = xpcs_usxgmii_features,
1247 .interface = xpcs_usxgmii_interfaces,
1248 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1249 .an_mode = DW_AN_C73,
1250 },
1251 [DW_XPCS_10GKR] = {
1252 .supported = xpcs_10gkr_features,
1253 .interface = xpcs_10gkr_interfaces,
1254 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1255 .an_mode = DW_AN_C73,
1256 },
1257 [DW_XPCS_XLGMII] = {
1258 .supported = xpcs_xlgmii_features,
1259 .interface = xpcs_xlgmii_interfaces,
1260 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1261 .an_mode = DW_AN_C73,
1262 },
1263 [DW_XPCS_10GBASER] = {
1264 .supported = xpcs_10gbaser_features,
1265 .interface = xpcs_10gbaser_interfaces,
1266 .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
1267 .an_mode = DW_10GBASER,
1268 },
1269 [DW_XPCS_SGMII] = {
1270 .supported = xpcs_sgmii_features,
1271 .interface = xpcs_sgmii_interfaces,
1272 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1273 .an_mode = DW_AN_C37_SGMII,
1274 },
1275 [DW_XPCS_1000BASEX] = {
1276 .supported = xpcs_1000basex_features,
1277 .interface = xpcs_1000basex_interfaces,
1278 .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
1279 .an_mode = DW_AN_C37_1000BASEX,
1280 },
1281 [DW_XPCS_2500BASEX] = {
1282 .supported = xpcs_2500basex_features,
1283 .interface = xpcs_2500basex_interfaces,
1284 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1285 .an_mode = DW_2500BASEX,
1286 },
1287 };
1288
1289 static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1290 [DW_XPCS_SGMII] = {
1291 .supported = xpcs_sgmii_features,
1292 .interface = xpcs_sgmii_interfaces,
1293 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1294 .an_mode = DW_AN_C37_SGMII,
1295 .pma_config = nxp_sja1105_sgmii_pma_config,
1296 },
1297 };
1298
1299 static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1300 [DW_XPCS_SGMII] = {
1301 .supported = xpcs_sgmii_features,
1302 .interface = xpcs_sgmii_interfaces,
1303 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1304 .an_mode = DW_AN_C37_SGMII,
1305 .pma_config = nxp_sja1110_sgmii_pma_config,
1306 },
1307 [DW_XPCS_2500BASEX] = {
1308 .supported = xpcs_2500basex_features,
1309 .interface = xpcs_2500basex_interfaces,
1310 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1311 .an_mode = DW_2500BASEX,
1312 .pma_config = nxp_sja1110_2500basex_pma_config,
1313 },
1314 };
1315
1316 static const struct xpcs_id xpcs_id_list[] = {
1317 {
1318 .id = SYNOPSYS_XPCS_ID,
1319 .mask = SYNOPSYS_XPCS_MASK,
1320 .compat = synopsys_xpcs_compat,
1321 }, {
1322 .id = NXP_SJA1105_XPCS_ID,
1323 .mask = SYNOPSYS_XPCS_MASK,
1324 .compat = nxp_sja1105_xpcs_compat,
1325 }, {
1326 .id = NXP_SJA1110_XPCS_ID,
1327 .mask = SYNOPSYS_XPCS_MASK,
1328 .compat = nxp_sja1110_xpcs_compat,
1329 },
1330 };
1331
1332 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1333 .pcs_validate = xpcs_validate,
1334 .pcs_config = xpcs_config,
1335 .pcs_get_state = xpcs_get_state,
1336 .pcs_an_restart = xpcs_an_restart,
1337 .pcs_link_up = xpcs_link_up,
1338 };
1339
xpcs_create(struct mdio_device * mdiodev,phy_interface_t interface)1340 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1341 phy_interface_t interface)
1342 {
1343 struct dw_xpcs *xpcs;
1344 u32 xpcs_id;
1345 int i, ret;
1346
1347 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1348 if (!xpcs)
1349 return ERR_PTR(-ENOMEM);
1350
1351 mdio_device_get(mdiodev);
1352 xpcs->mdiodev = mdiodev;
1353
1354 xpcs_id = xpcs_get_id(xpcs);
1355
1356 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1357 const struct xpcs_id *entry = &xpcs_id_list[i];
1358 const struct xpcs_compat *compat;
1359
1360 if ((xpcs_id & entry->mask) != entry->id)
1361 continue;
1362
1363 xpcs->id = entry;
1364
1365 compat = xpcs_find_compat(entry, interface);
1366 if (!compat) {
1367 ret = -ENODEV;
1368 goto out;
1369 }
1370
1371 ret = xpcs_dev_flag(xpcs);
1372 if (ret)
1373 goto out;
1374
1375 xpcs->pcs.ops = &xpcs_phylink_ops;
1376 xpcs->pcs.neg_mode = true;
1377
1378 if (xpcs->dev_flag != DW_DEV_TXGBE) {
1379 xpcs->pcs.poll = true;
1380
1381 ret = xpcs_soft_reset(xpcs, compat);
1382 if (ret)
1383 goto out;
1384 }
1385
1386 return xpcs;
1387 }
1388
1389 ret = -ENODEV;
1390
1391 out:
1392 mdio_device_put(mdiodev);
1393 kfree(xpcs);
1394
1395 return ERR_PTR(ret);
1396 }
1397
xpcs_destroy(struct dw_xpcs * xpcs)1398 void xpcs_destroy(struct dw_xpcs *xpcs)
1399 {
1400 if (xpcs)
1401 mdio_device_put(xpcs->mdiodev);
1402 kfree(xpcs);
1403 }
1404 EXPORT_SYMBOL_GPL(xpcs_destroy);
1405
xpcs_create_mdiodev(struct mii_bus * bus,int addr,phy_interface_t interface)1406 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr,
1407 phy_interface_t interface)
1408 {
1409 struct mdio_device *mdiodev;
1410 struct dw_xpcs *xpcs;
1411
1412 mdiodev = mdio_device_create(bus, addr);
1413 if (IS_ERR(mdiodev))
1414 return ERR_CAST(mdiodev);
1415
1416 xpcs = xpcs_create(mdiodev, interface);
1417
1418 /* xpcs_create() has taken a refcount on the mdiodev if it was
1419 * successful. If xpcs_create() fails, this will free the mdio
1420 * device here. In any case, we don't need to hold our reference
1421 * anymore, and putting it here will allow mdio_device_put() in
1422 * xpcs_destroy() to automatically free the mdio device.
1423 */
1424 mdio_device_put(mdiodev);
1425
1426 return xpcs;
1427 }
1428 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1429
1430 MODULE_LICENSE("GPL v2");
1431
