1 /* 2 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller 3 * 4 * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 #ifndef _MCR20A_H 17 #define _MCR20A_H 18 19 /* Direct Accress Register */ 20 #define DAR_IRQ_STS1 0x00 21 #define DAR_IRQ_STS2 0x01 22 #define DAR_IRQ_STS3 0x02 23 #define DAR_PHY_CTRL1 0x03 24 #define DAR_PHY_CTRL2 0x04 25 #define DAR_PHY_CTRL3 0x05 26 #define DAR_RX_FRM_LEN 0x06 27 #define DAR_PHY_CTRL4 0x07 28 #define DAR_SRC_CTRL 0x08 29 #define DAR_SRC_ADDRS_SUM_LSB 0x09 30 #define DAR_SRC_ADDRS_SUM_MSB 0x0A 31 #define DAR_CCA1_ED_FNL 0x0B 32 #define DAR_EVENT_TMR_LSB 0x0C 33 #define DAR_EVENT_TMR_MSB 0x0D 34 #define DAR_EVENT_TMR_USB 0x0E 35 #define DAR_TIMESTAMP_LSB 0x0F 36 #define DAR_TIMESTAMP_MSB 0x10 37 #define DAR_TIMESTAMP_USB 0x11 38 #define DAR_T3CMP_LSB 0x12 39 #define DAR_T3CMP_MSB 0x13 40 #define DAR_T3CMP_USB 0x14 41 #define DAR_T2PRIMECMP_LSB 0x15 42 #define DAR_T2PRIMECMP_MSB 0x16 43 #define DAR_T1CMP_LSB 0x17 44 #define DAR_T1CMP_MSB 0x18 45 #define DAR_T1CMP_USB 0x19 46 #define DAR_T2CMP_LSB 0x1A 47 #define DAR_T2CMP_MSB 0x1B 48 #define DAR_T2CMP_USB 0x1C 49 #define DAR_T4CMP_LSB 0x1D 50 #define DAR_T4CMP_MSB 0x1E 51 #define DAR_T4CMP_USB 0x1F 52 #define DAR_PLL_INT0 0x20 53 #define DAR_PLL_FRAC0_LSB 0x21 54 #define DAR_PLL_FRAC0_MSB 0x22 55 #define DAR_PA_PWR 0x23 56 #define DAR_SEQ_STATE 0x24 57 #define DAR_LQI_VALUE 0x25 58 #define DAR_RSSI_CCA_CONT 0x26 59 /*------------------ 0x27 */ 60 #define DAR_ASM_CTRL1 0x28 61 #define DAR_ASM_CTRL2 0x29 62 #define DAR_ASM_DATA_0 0x2A 63 #define DAR_ASM_DATA_1 0x2B 64 #define DAR_ASM_DATA_2 0x2C 65 #define DAR_ASM_DATA_3 0x2D 66 #define DAR_ASM_DATA_4 0x2E 67 #define DAR_ASM_DATA_5 0x2F 68 #define DAR_ASM_DATA_6 0x30 69 #define DAR_ASM_DATA_7 0x31 70 #define DAR_ASM_DATA_8 0x32 71 #define DAR_ASM_DATA_9 0x33 72 #define DAR_ASM_DATA_A 0x34 73 #define DAR_ASM_DATA_B 0x35 74 #define DAR_ASM_DATA_C 0x36 75 #define DAR_ASM_DATA_D 0x37 76 #define DAR_ASM_DATA_E 0x38 77 #define DAR_ASM_DATA_F 0x39 78 /*----------------------- 0x3A */ 79 #define DAR_OVERWRITE_VER 0x3B 80 #define DAR_CLK_OUT_CTRL 0x3C 81 #define DAR_PWR_MODES 0x3D 82 #define IAR_INDEX 0x3E 83 #define IAR_DATA 0x3F 84 85 /* Indirect Resgister Memory */ 86 #define IAR_PART_ID 0x00 87 #define IAR_XTAL_TRIM 0x01 88 #define IAR_PMC_LP_TRIM 0x02 89 #define IAR_MACPANID0_LSB 0x03 90 #define IAR_MACPANID0_MSB 0x04 91 #define IAR_MACSHORTADDRS0_LSB 0x05 92 #define IAR_MACSHORTADDRS0_MSB 0x06 93 #define IAR_MACLONGADDRS0_0 0x07 94 #define IAR_MACLONGADDRS0_8 0x08 95 #define IAR_MACLONGADDRS0_16 0x09 96 #define IAR_MACLONGADDRS0_24 0x0A 97 #define IAR_MACLONGADDRS0_32 0x0B 98 #define IAR_MACLONGADDRS0_40 0x0C 99 #define IAR_MACLONGADDRS0_48 0x0D 100 #define IAR_MACLONGADDRS0_56 0x0E 101 #define IAR_RX_FRAME_FILTER 0x0F 102 #define IAR_PLL_INT1 0x10 103 #define IAR_PLL_FRAC1_LSB 0x11 104 #define IAR_PLL_FRAC1_MSB 0x12 105 #define IAR_MACPANID1_LSB 0x13 106 #define IAR_MACPANID1_MSB 0x14 107 #define IAR_MACSHORTADDRS1_LSB 0x15 108 #define IAR_MACSHORTADDRS1_MSB 0x16 109 #define IAR_MACLONGADDRS1_0 0x17 110 #define IAR_MACLONGADDRS1_8 0x18 111 #define IAR_MACLONGADDRS1_16 0x19 112 #define IAR_MACLONGADDRS1_24 0x1A 113 #define IAR_MACLONGADDRS1_32 0x1B 114 #define IAR_MACLONGADDRS1_40 0x1C 115 #define IAR_MACLONGADDRS1_48 0x1D 116 #define IAR_MACLONGADDRS1_56 0x1E 117 #define IAR_DUAL_PAN_CTRL 0x1F 118 #define IAR_DUAL_PAN_DWELL 0x20 119 #define IAR_DUAL_PAN_STS 0x21 120 #define IAR_CCA1_THRESH 0x22 121 #define IAR_CCA1_ED_OFFSET_COMP 0x23 122 #define IAR_LQI_OFFSET_COMP 0x24 123 #define IAR_CCA_CTRL 0x25 124 #define IAR_CCA2_CORR_PEAKS 0x26 125 #define IAR_CCA2_CORR_THRESH 0x27 126 #define IAR_TMR_PRESCALE 0x28 127 /*-------------------- 0x29 */ 128 #define IAR_GPIO_DATA 0x2A 129 #define IAR_GPIO_DIR 0x2B 130 #define IAR_GPIO_PUL_EN 0x2C 131 #define IAR_GPIO_PUL_SEL 0x2D 132 #define IAR_GPIO_DS 0x2E 133 /*------------------ 0x2F */ 134 #define IAR_ANT_PAD_CTRL 0x30 135 #define IAR_MISC_PAD_CTRL 0x31 136 #define IAR_BSM_CTRL 0x32 137 /*------------------- 0x33 */ 138 #define IAR_RNG 0x34 139 #define IAR_RX_BYTE_COUNT 0x35 140 #define IAR_RX_WTR_MARK 0x36 141 #define IAR_SOFT_RESET 0x37 142 #define IAR_TXDELAY 0x38 143 #define IAR_ACKDELAY 0x39 144 #define IAR_SEQ_MGR_CTRL 0x3A 145 #define IAR_SEQ_MGR_STS 0x3B 146 #define IAR_SEQ_T_STS 0x3C 147 #define IAR_ABORT_STS 0x3D 148 #define IAR_CCCA_BUSY_CNT 0x3E 149 #define IAR_SRC_ADDR_CHECKSUM1 0x3F 150 #define IAR_SRC_ADDR_CHECKSUM2 0x40 151 #define IAR_SRC_TBL_VALID1 0x41 152 #define IAR_SRC_TBL_VALID2 0x42 153 #define IAR_FILTERFAIL_CODE1 0x43 154 #define IAR_FILTERFAIL_CODE2 0x44 155 #define IAR_SLOT_PRELOAD 0x45 156 /*-------------------- 0x46 */ 157 #define IAR_CORR_VT 0x47 158 #define IAR_SYNC_CTRL 0x48 159 #define IAR_PN_LSB_0 0x49 160 #define IAR_PN_LSB_1 0x4A 161 #define IAR_PN_MSB_0 0x4B 162 #define IAR_PN_MSB_1 0x4C 163 #define IAR_CORR_NVAL 0x4D 164 #define IAR_TX_MODE_CTRL 0x4E 165 #define IAR_SNF_THR 0x4F 166 #define IAR_FAD_THR 0x50 167 #define IAR_ANT_AGC_CTRL 0x51 168 #define IAR_AGC_THR1 0x52 169 #define IAR_AGC_THR2 0x53 170 #define IAR_AGC_HYS 0x54 171 #define IAR_AFC 0x55 172 /*------------------- 0x56 */ 173 /*------------------- 0x57 */ 174 #define IAR_PHY_STS 0x58 175 #define IAR_RX_MAX_CORR 0x59 176 #define IAR_RX_MAX_PREAMBLE 0x5A 177 #define IAR_RSSI 0x5B 178 /*------------------- 0x5C */ 179 /*------------------- 0x5D */ 180 #define IAR_PLL_DIG_CTRL 0x5E 181 #define IAR_VCO_CAL 0x5F 182 #define IAR_VCO_BEST_DIFF 0x60 183 #define IAR_VCO_BIAS 0x61 184 #define IAR_KMOD_CTRL 0x62 185 #define IAR_KMOD_CAL 0x63 186 #define IAR_PA_CAL 0x64 187 #define IAR_PA_PWRCAL 0x65 188 #define IAR_ATT_RSSI1 0x66 189 #define IAR_ATT_RSSI2 0x67 190 #define IAR_RSSI_OFFSET 0x68 191 #define IAR_RSSI_SLOPE 0x69 192 #define IAR_RSSI_CAL1 0x6A 193 #define IAR_RSSI_CAL2 0x6B 194 /*------------------- 0x6C */ 195 /*------------------- 0x6D */ 196 #define IAR_XTAL_CTRL 0x6E 197 #define IAR_XTAL_COMP_MIN 0x6F 198 #define IAR_XTAL_COMP_MAX 0x70 199 #define IAR_XTAL_GM 0x71 200 /*------------------- 0x72 */ 201 /*------------------- 0x73 */ 202 #define IAR_LNA_TUNE 0x74 203 #define IAR_LNA_AGCGAIN 0x75 204 /*------------------- 0x76 */ 205 /*------------------- 0x77 */ 206 #define IAR_CHF_PMA_GAIN 0x78 207 #define IAR_CHF_IBUF 0x79 208 #define IAR_CHF_QBUF 0x7A 209 #define IAR_CHF_IRIN 0x7B 210 #define IAR_CHF_QRIN 0x7C 211 #define IAR_CHF_IL 0x7D 212 #define IAR_CHF_QL 0x7E 213 #define IAR_CHF_CC1 0x7F 214 #define IAR_CHF_CCL 0x80 215 #define IAR_CHF_CC2 0x81 216 #define IAR_CHF_IROUT 0x82 217 #define IAR_CHF_QROUT 0x83 218 /*------------------- 0x84 */ 219 /*------------------- 0x85 */ 220 #define IAR_RSSI_CTRL 0x86 221 /*------------------- 0x87 */ 222 /*------------------- 0x88 */ 223 #define IAR_PA_BIAS 0x89 224 #define IAR_PA_TUNING 0x8A 225 /*------------------- 0x8B */ 226 /*------------------- 0x8C */ 227 #define IAR_PMC_HP_TRIM 0x8D 228 #define IAR_VREGA_TRIM 0x8E 229 /*------------------- 0x8F */ 230 /*------------------- 0x90 */ 231 #define IAR_VCO_CTRL1 0x91 232 #define IAR_VCO_CTRL2 0x92 233 /*------------------- 0x93 */ 234 /*------------------- 0x94 */ 235 #define IAR_ANA_SPARE_OUT1 0x95 236 #define IAR_ANA_SPARE_OUT2 0x96 237 #define IAR_ANA_SPARE_IN 0x97 238 #define IAR_MISCELLANEOUS 0x98 239 /*------------------- 0x99 */ 240 #define IAR_SEQ_MGR_OVRD0 0x9A 241 #define IAR_SEQ_MGR_OVRD1 0x9B 242 #define IAR_SEQ_MGR_OVRD2 0x9C 243 #define IAR_SEQ_MGR_OVRD3 0x9D 244 #define IAR_SEQ_MGR_OVRD4 0x9E 245 #define IAR_SEQ_MGR_OVRD5 0x9F 246 #define IAR_SEQ_MGR_OVRD6 0xA0 247 #define IAR_SEQ_MGR_OVRD7 0xA1 248 /*------------------- 0xA2 */ 249 #define IAR_TESTMODE_CTRL 0xA3 250 #define IAR_DTM_CTRL1 0xA4 251 #define IAR_DTM_CTRL2 0xA5 252 #define IAR_ATM_CTRL1 0xA6 253 #define IAR_ATM_CTRL2 0xA7 254 #define IAR_ATM_CTRL3 0xA8 255 /*------------------- 0xA9 */ 256 #define IAR_LIM_FE_TEST_CTRL 0xAA 257 #define IAR_CHF_TEST_CTRL 0xAB 258 #define IAR_VCO_TEST_CTRL 0xAC 259 #define IAR_PLL_TEST_CTRL 0xAD 260 #define IAR_PA_TEST_CTRL 0xAE 261 #define IAR_PMC_TEST_CTRL 0xAF 262 #define IAR_SCAN_DTM_PROTECT_1 0xFE 263 #define IAR_SCAN_DTM_PROTECT_0 0xFF 264 265 /* IRQSTS1 bits */ 266 #define DAR_IRQSTS1_RX_FRM_PEND BIT(7) 267 #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6) 268 #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5) 269 #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4) 270 #define DAR_IRQSTS1_CCAIRQ BIT(3) 271 #define DAR_IRQSTS1_RXIRQ BIT(2) 272 #define DAR_IRQSTS1_TXIRQ BIT(1) 273 #define DAR_IRQSTS1_SEQIRQ BIT(0) 274 275 /* IRQSTS2 bits */ 276 #define DAR_IRQSTS2_CRCVALID BIT(7) 277 #define DAR_IRQSTS2_CCA BIT(6) 278 #define DAR_IRQSTS2_SRCADDR BIT(5) 279 #define DAR_IRQSTS2_PI BIT(4) 280 #define DAR_IRQSTS2_TMRSTATUS BIT(3) 281 #define DAR_IRQSTS2_ASM_IRQ BIT(2) 282 #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1) 283 #define DAR_IRQSTS2_WAKE_IRQ BIT(0) 284 285 /* IRQSTS3 bits */ 286 #define DAR_IRQSTS3_TMR4MSK BIT(7) 287 #define DAR_IRQSTS3_TMR3MSK BIT(6) 288 #define DAR_IRQSTS3_TMR2MSK BIT(5) 289 #define DAR_IRQSTS3_TMR1MSK BIT(4) 290 #define DAR_IRQSTS3_TMR4IRQ BIT(3) 291 #define DAR_IRQSTS3_TMR3IRQ BIT(2) 292 #define DAR_IRQSTS3_TMR2IRQ BIT(1) 293 #define DAR_IRQSTS3_TMR1IRQ BIT(0) 294 295 /* PHY_CTRL1 bits */ 296 #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7) 297 #define DAR_PHY_CTRL1_SLOTTED BIT(6) 298 #define DAR_PHY_CTRL1_CCABFRTX BIT(5) 299 #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5 300 #define DAR_PHY_CTRL1_RXACKRQD BIT(4) 301 #define DAR_PHY_CTRL1_AUTOACK BIT(3) 302 #define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07 303 304 /* PHY_CTRL2 bits */ 305 #define DAR_PHY_CTRL2_CRC_MSK BIT(7) 306 #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6) 307 #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5) 308 #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4) 309 #define DAR_PHY_CTRL2_CCAMSK BIT(3) 310 #define DAR_PHY_CTRL2_RXMSK BIT(2) 311 #define DAR_PHY_CTRL2_TXMSK BIT(1) 312 #define DAR_PHY_CTRL2_SEQMSK BIT(0) 313 314 /* PHY_CTRL3 bits */ 315 #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7) 316 #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6) 317 #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5) 318 #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4) 319 #define DAR_PHY_CTRL3_ASM_MSK BIT(2) 320 #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1) 321 #define DAR_PHY_CTRL3_WAKE_MSK BIT(0) 322 323 /* RX_FRM_LEN bits */ 324 #define DAR_RX_FRAME_LENGTH_MASK (0x7F) 325 326 /* PHY_CTRL4 bits */ 327 #define DAR_PHY_CTRL4_TRCV_MSK BIT(7) 328 #define DAR_PHY_CTRL4_TC3TMOUT BIT(6) 329 #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5) 330 #define DAR_PHY_CTRL4_CCATYPE (3) 331 #define DAR_PHY_CTRL4_CCATYPE_SHIFT (3) 332 #define DAR_PHY_CTRL4_CCATYPE_MASK (0x18) 333 #define DAR_PHY_CTRL4_TMRLOAD BIT(2) 334 #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1) 335 #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0) 336 337 /* SRC_CTRL bits */ 338 #define DAR_SRC_CTRL_INDEX (0x0F) 339 #define DAR_SRC_CTRL_INDEX_SHIFT (4) 340 #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3) 341 #define DAR_SRC_CTRL_SRCADDR_EN BIT(2) 342 #define DAR_SRC_CTRL_INDEX_EN BIT(1) 343 #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0) 344 345 /* DAR_ASM_CTRL1 bits */ 346 #define DAR_ASM_CTRL1_CLEAR BIT(7) 347 #define DAR_ASM_CTRL1_START BIT(6) 348 #define DAR_ASM_CTRL1_SELFTST BIT(5) 349 #define DAR_ASM_CTRL1_CTR BIT(4) 350 #define DAR_ASM_CTRL1_CBC BIT(3) 351 #define DAR_ASM_CTRL1_AES BIT(2) 352 #define DAR_ASM_CTRL1_LOAD_MAC BIT(1) 353 354 /* DAR_ASM_CTRL2 bits */ 355 #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7) 356 #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5) 357 #define DAR_ASM_CTRL2_TSTPAS BIT(1) 358 359 /* DAR_CLK_OUT_CTRL bits */ 360 #define DAR_CLK_OUT_CTRL_EXTEND BIT(7) 361 #define DAR_CLK_OUT_CTRL_HIZ BIT(6) 362 #define DAR_CLK_OUT_CTRL_SR BIT(5) 363 #define DAR_CLK_OUT_CTRL_DS BIT(4) 364 #define DAR_CLK_OUT_CTRL_EN BIT(3) 365 #define DAR_CLK_OUT_CTRL_DIV (7) 366 367 /* DAR_PWR_MODES bits */ 368 #define DAR_PWR_MODES_XTAL_READY BIT(5) 369 #define DAR_PWR_MODES_XTALEN BIT(4) 370 #define DAR_PWR_MODES_ASM_CLK_EN BIT(3) 371 #define DAR_PWR_MODES_AUTODOZE BIT(1) 372 #define DAR_PWR_MODES_PMC_MODE BIT(0) 373 374 /* RX_FRAME_FILTER bits */ 375 #define IAR_RX_FRAME_FLT_FRM_VER (0xC0) 376 #define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6) 377 #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5) 378 #define IAR_RX_FRAME_FLT_NS_FT BIT(4) 379 #define IAR_RX_FRAME_FLT_CMD_FT BIT(3) 380 #define IAR_RX_FRAME_FLT_ACK_FT BIT(2) 381 #define IAR_RX_FRAME_FLT_DATA_FT BIT(1) 382 #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0) 383 384 /* DUAL_PAN_CTRL bits */ 385 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0) 386 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4) 387 #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3) 388 #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2) 389 #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1) 390 #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0) 391 392 /* DUAL_PAN_STS bits */ 393 #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7) 394 #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6) 395 #define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F) 396 397 /* CCA_CTRL bits */ 398 #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6) 399 #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5) 400 #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4) 401 #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3) 402 #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2) 403 #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1) 404 #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0) 405 406 /* ANT_PAD_CTRL bits */ 407 #define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F) 408 #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4) 409 #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3) 410 #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2) 411 #define IAR_ANT_PAD_CTRL_ANTX_EN (3) 412 413 /* MISC_PAD_CTRL bits */ 414 #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3) 415 #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2) 416 #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) 417 #define IAR_MISC_PAD_CTRL_ANTX_CURR (1) 418 419 /* ANT_AGC_CTRL bits */ 420 #define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0) 421 #define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1) 422 #define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1) 423 #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT) 424 425 /* BSM_CTRL bits */ 426 #define BSM_CTRL_BSM_EN (1) 427 428 /* SOFT_RESET bits */ 429 #define IAR_SOFT_RESET_SOG_RST BIT(7) 430 #define IAR_SOFT_RESET_REGS_RST BIT(4) 431 #define IAR_SOFT_RESET_PLL_RST BIT(3) 432 #define IAR_SOFT_RESET_TX_RST BIT(2) 433 #define IAR_SOFT_RESET_RX_RST BIT(1) 434 #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0) 435 436 /* SEQ_MGR_CTRL bits */ 437 #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3) 438 #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6) 439 #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5) 440 #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4) 441 #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3) 442 #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2) 443 #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1) 444 #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0) 445 446 /* SEQ_MGR_STS bits */ 447 #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7) 448 #define IAR_SEQ_MGR_STS_RX_MODE BIT(6) 449 #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5) 450 #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4) 451 #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3) 452 #define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7) 453 454 /* ABORT_STS bits */ 455 #define IAR_ABORT_STS_PLL_ABORTED BIT(2) 456 #define IAR_ABORT_STS_TC3_ABORTED BIT(1) 457 #define IAR_ABORT_STS_SW_ABORTED BIT(0) 458 459 /* IAR_FILTERFAIL_CODE2 bits */ 460 #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7) 461 #define IAR_FILTERFAIL_CODE2_9_8 (3) 462 463 /* PHY_STS bits */ 464 #define IAR_PHY_STS_PLL_UNLOCK BIT(7) 465 #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6) 466 #define IAR_PHY_STS_PLL_LOCK BIT(5) 467 #define IAR_PHY_STS_CRCVALID BIT(3) 468 #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2) 469 #define IAR_PHY_STS_SFD_DET BIT(1) 470 #define IAR_PHY_STS_PREAMBLE_DET BIT(0) 471 472 /* TESTMODE_CTRL bits */ 473 #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4) 474 #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3) 475 #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2) 476 #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1) 477 #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0) 478 479 /* DTM_CTRL1 bits */ 480 #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7) 481 #define IAR_DTM_CTRL1_DTM_EN BIT(6) 482 #define IAR_DTM_CTRL1_PAGE5 BIT(5) 483 #define IAR_DTM_CTRL1_PAGE4 BIT(4) 484 #define IAR_DTM_CTRL1_PAGE3 BIT(3) 485 #define IAR_DTM_CTRL1_PAGE2 BIT(2) 486 #define IAR_DTM_CTRL1_PAGE1 BIT(1) 487 #define IAR_DTM_CTRL1_PAGE0 BIT(0) 488 489 /* TX_MODE_CTRL */ 490 #define IAR_TX_MODE_CTRL_TX_INV BIT(4) 491 #define IAR_TX_MODE_CTRL_BT_EN BIT(3) 492 #define IAR_TX_MODE_CTRL_DTS2 BIT(2) 493 #define IAR_TX_MODE_CTRL_DTS1 BIT(1) 494 #define IAR_TX_MODE_CTRL_DTS0 BIT(0) 495 496 #define TX_MODE_CTRL_DTS_MASK (7) 497 498 #endif /* _MCR20A_H */ 499
