1 /*
2 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver
3 *
4 * Copyright 2009-2017 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 *
8 * http://www.analog.com/ADF7242
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/delay.h>
15 #include <linux/mutex.h>
16 #include <linux/workqueue.h>
17 #include <linux/spinlock.h>
18 #include <linux/firmware.h>
19 #include <linux/spi/spi.h>
20 #include <linux/skbuff.h>
21 #include <linux/of.h>
22 #include <linux/irq.h>
23 #include <linux/debugfs.h>
24 #include <linux/bitops.h>
25 #include <linux/ieee802154.h>
26 #include <net/mac802154.h>
27 #include <net/cfg802154.h>
28
29 #define FIRMWARE "adf7242_firmware.bin"
30 #define MAX_POLL_LOOPS 200
31
32 /* All Registers */
33
34 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
35 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
36 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
37 #define REG_CCA2 0x106 /* RW CCA mode configuration */
38 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
39 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
40 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
41 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
42 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
43 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
44 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */
45 #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */
46 #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */
47 #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */
48 #define REG_RC_VAR44 0x13F /* RW RESERVED */
49 #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */
50 #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */
51 #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */
52 #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */
53 #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */
54 #define REG_TX_M 0x306 /* RW TX Mode Register */
55 #define REG_RX_M 0x307 /* RW RX Mode Register */
56 #define REG_RRB 0x30C /* R RSSI Readback Register */
57 #define REG_LRB 0x30D /* R Link Quality Readback Register */
58 #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */
59 #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */
60 #define REG_PRAMPG 0x313 /* RW RESERVED */
61 #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */
62 #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */
63 #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */
64 #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */
65 #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */
66 #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */
67 #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */
68 #define REG_PD_AUX 0x31E /* RW Battmon enable */
69 #define REG_GP_CFG 0x32C /* RW GPIO Configuration */
70 #define REG_GP_OUT 0x32D /* RW GPIO Configuration */
71 #define REG_GP_IN 0x32E /* R GPIO Configuration */
72 #define REG_SYNT 0x335 /* RW bandwidth calibration timers */
73 #define REG_CAL_CFG 0x33D /* RW Calibration Settings */
74 #define REG_PA_BIAS 0x36E /* RW PA BIAS */
75 #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */
76 #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */
77 #define REG_CDR_CFG 0x38A /* RW CDR kVCO */
78 #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */
79 #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */
80 #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */
81 #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */
82 #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */
83 #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */
84 #define REG_PA_CFG 0x3A8 /* RW PA enable */
85 #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */
86 #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */
87 #define REG_ADC_RBK 0x3AE /* R Readback temp */
88 #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */
89 #define REG_AGC_MAX 0x3B4 /* RW Slew rate */
90 #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */
91 #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */
92 #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */
93 #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */
94 #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */
95 #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */
96 #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */
97 #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */
98 #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */
99 #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */
100 #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */
101 #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */
102 #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */
103 #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */
104 #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */
105 #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */
106 #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */
107 #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */
108 #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */
109 #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */
110 #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */
111 #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */
112 #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */
113 #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */
114 #define REG_AFC_RANGE 0x3F9 /* RW AFC range */
115 #define REG_AFC_READ 0x3FA /* RW Readback frequency error */
116
117 /* REG_EXTPA_MSC */
118 #define PA_PWR(x) (((x) & 0xF) << 4)
119 #define EXTPA_BIAS_SRC BIT(3)
120 #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0)
121
122 /* REG_PA_CFG */
123 #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0)
124 #define PA_DBIAS_HIGH_POWER 21
125 #define PA_DBIAS_LOW_POWER 13
126
127 /* REG_PA_BIAS */
128 #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1)
129 #define REG_PA_BIAS_DFL BIT(0)
130 #define PA_BIAS_HIGH_POWER 63
131 #define PA_BIAS_LOW_POWER 55
132
133 #define REG_PAN_ID0 0x112
134 #define REG_PAN_ID1 0x113
135 #define REG_SHORT_ADDR_0 0x114
136 #define REG_SHORT_ADDR_1 0x115
137 #define REG_IEEE_ADDR_0 0x116
138 #define REG_IEEE_ADDR_1 0x117
139 #define REG_IEEE_ADDR_2 0x118
140 #define REG_IEEE_ADDR_3 0x119
141 #define REG_IEEE_ADDR_4 0x11A
142 #define REG_IEEE_ADDR_5 0x11B
143 #define REG_IEEE_ADDR_6 0x11C
144 #define REG_IEEE_ADDR_7 0x11D
145 #define REG_FFILT_CFG 0x11E
146 #define REG_AUTO_CFG 0x11F
147 #define REG_AUTO_TX1 0x120
148 #define REG_AUTO_TX2 0x121
149 #define REG_AUTO_STATUS 0x122
150
151 /* REG_FFILT_CFG */
152 #define ACCEPT_BEACON_FRAMES BIT(0)
153 #define ACCEPT_DATA_FRAMES BIT(1)
154 #define ACCEPT_ACK_FRAMES BIT(2)
155 #define ACCEPT_MACCMD_FRAMES BIT(3)
156 #define ACCEPT_RESERVED_FRAMES BIT(4)
157 #define ACCEPT_ALL_ADDRESS BIT(5)
158
159 /* REG_AUTO_CFG */
160 #define AUTO_ACK_FRAMEPEND BIT(0)
161 #define IS_PANCOORD BIT(1)
162 #define RX_AUTO_ACK_EN BIT(3)
163 #define CSMA_CA_RX_TURNAROUND BIT(4)
164
165 /* REG_AUTO_TX1 */
166 #define MAX_FRAME_RETRIES(x) ((x) & 0xF)
167 #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4)
168
169 /* REG_AUTO_TX2 */
170 #define CSMA_MAX_BE(x) ((x) & 0xF)
171 #define CSMA_MIN_BE(x) (((x) & 0xF) << 4)
172
173 #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */
174 #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM
175 * starting from the TX packet base address
176 * pointer tx_packet_base
177 */
178 #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM
179 * starting from RX packet base address
180 * pointer rxpb.rx_packet_base
181 */
182 #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or
183 * Packet RAM sequentially
184 */
185 #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or
186 * Packet RAM sequentially
187 */
188 #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet
189 * RAM as random block
190 */
191 #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or
192 * Packet RAM random block
193 */
194 #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current
195 * PRAM page selected
196 */
197 #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current
198 * PRAM page selected
199 */
200 #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller
201 * into SLEEP state
202 */
203 #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller
204 * into IDLE state
205 */
206 #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller
207 * into PHY_RDY state
208 */
209 #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller
210 * into RX state
211 */
212 #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller
213 * into TX state
214 */
215 #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller
216 * into MEAS state
217 */
218 #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */
219 #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access
220 * sequence and frame transmission
221 */
222 #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */
223 #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in
224 * the sleep state
225 */
226 #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31))
227
228 /* STATUS */
229
230 #define STAT_SPI_READY BIT(7)
231 #define STAT_IRQ_STATUS BIT(6)
232 #define STAT_RC_READY BIT(5)
233 #define STAT_CCA_RESULT BIT(4)
234 #define RC_STATUS_IDLE 1
235 #define RC_STATUS_MEAS 2
236 #define RC_STATUS_PHY_RDY 3
237 #define RC_STATUS_RX 4
238 #define RC_STATUS_TX 5
239 #define RC_STATUS_MASK 0xF
240
241 /* AUTO_STATUS */
242
243 #define SUCCESS 0
244 #define SUCCESS_DATPEND 1
245 #define FAILURE_CSMACA 2
246 #define FAILURE_NOACK 3
247 #define AUTO_STATUS_MASK 0x3
248
249 #define PRAM_PAGESIZE 256
250
251 /* IRQ1 */
252
253 #define IRQ_CCA_COMPLETE BIT(0)
254 #define IRQ_SFD_RX BIT(1)
255 #define IRQ_SFD_TX BIT(2)
256 #define IRQ_RX_PKT_RCVD BIT(3)
257 #define IRQ_TX_PKT_SENT BIT(4)
258 #define IRQ_FRAME_VALID BIT(5)
259 #define IRQ_ADDRESS_VALID BIT(6)
260 #define IRQ_CSMA_CA BIT(7)
261
262 #define AUTO_TX_TURNAROUND BIT(3)
263 #define ADDON_EN BIT(4)
264
265 #define FLAG_XMIT 0
266 #define FLAG_START 1
267
268 #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */
269
270 struct adf7242_local {
271 struct spi_device *spi;
272 struct completion tx_complete;
273 struct ieee802154_hw *hw;
274 struct mutex bmux; /* protect SPI messages */
275 struct spi_message stat_msg;
276 struct spi_transfer stat_xfer;
277 struct dentry *debugfs_root;
278 struct delayed_work work;
279 struct workqueue_struct *wqueue;
280 unsigned long flags;
281 int tx_stat;
282 bool promiscuous;
283 s8 rssi;
284 u8 max_frame_retries;
285 u8 max_cca_retries;
286 u8 max_be;
287 u8 min_be;
288
289 /* DMA (thus cache coherency maintenance) requires the
290 * transfer buffers to live in their own cache lines.
291 */
292
293 u8 buf[3] ____cacheline_aligned;
294 u8 buf_reg_tx[3];
295 u8 buf_read_tx[4];
296 u8 buf_read_rx[4];
297 u8 buf_stat_rx;
298 u8 buf_stat_tx;
299 u8 buf_cmd;
300 };
301
302 static int adf7242_soft_reset(struct adf7242_local *lp, int line);
303
adf7242_status(struct adf7242_local * lp,u8 * stat)304 static int adf7242_status(struct adf7242_local *lp, u8 *stat)
305 {
306 int status;
307
308 mutex_lock(&lp->bmux);
309 status = spi_sync(lp->spi, &lp->stat_msg);
310 *stat = lp->buf_stat_rx;
311 mutex_unlock(&lp->bmux);
312
313 return status;
314 }
315
adf7242_wait_status(struct adf7242_local * lp,unsigned int status,unsigned int mask,int line)316 static int adf7242_wait_status(struct adf7242_local *lp, unsigned int status,
317 unsigned int mask, int line)
318 {
319 int cnt = 0, ret = 0;
320 u8 stat;
321
322 do {
323 adf7242_status(lp, &stat);
324 cnt++;
325 } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS));
326
327 if (cnt >= MAX_POLL_LOOPS) {
328 ret = -ETIMEDOUT;
329
330 if (!(stat & STAT_RC_READY)) {
331 adf7242_soft_reset(lp, line);
332 adf7242_status(lp, &stat);
333
334 if ((stat & mask) == status)
335 ret = 0;
336 }
337
338 if (ret < 0)
339 dev_warn(&lp->spi->dev,
340 "%s:line %d Timeout status 0x%x (%d)\n",
341 __func__, line, stat, cnt);
342 }
343
344 dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line);
345
346 return ret;
347 }
348
adf7242_wait_rc_ready(struct adf7242_local * lp,int line)349 static int adf7242_wait_rc_ready(struct adf7242_local *lp, int line)
350 {
351 return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY,
352 STAT_RC_READY | STAT_SPI_READY, line);
353 }
354
adf7242_wait_spi_ready(struct adf7242_local * lp,int line)355 static int adf7242_wait_spi_ready(struct adf7242_local *lp, int line)
356 {
357 return adf7242_wait_status(lp, STAT_SPI_READY,
358 STAT_SPI_READY, line);
359 }
360
adf7242_write_fbuf(struct adf7242_local * lp,u8 * data,u8 len)361 static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len)
362 {
363 u8 *buf = lp->buf;
364 int status;
365 struct spi_message msg;
366 struct spi_transfer xfer_head = {
367 .len = 2,
368 .tx_buf = buf,
369
370 };
371 struct spi_transfer xfer_buf = {
372 .len = len,
373 .tx_buf = data,
374 };
375
376 spi_message_init(&msg);
377 spi_message_add_tail(&xfer_head, &msg);
378 spi_message_add_tail(&xfer_buf, &msg);
379
380 adf7242_wait_spi_ready(lp, __LINE__);
381
382 mutex_lock(&lp->bmux);
383 buf[0] = CMD_SPI_PKT_WR;
384 buf[1] = len + 2;
385
386 status = spi_sync(lp->spi, &msg);
387 mutex_unlock(&lp->bmux);
388
389 return status;
390 }
391
adf7242_read_fbuf(struct adf7242_local * lp,u8 * data,size_t len,bool packet_read)392 static int adf7242_read_fbuf(struct adf7242_local *lp,
393 u8 *data, size_t len, bool packet_read)
394 {
395 u8 *buf = lp->buf;
396 int status;
397 struct spi_message msg;
398 struct spi_transfer xfer_head = {
399 .len = 3,
400 .tx_buf = buf,
401 .rx_buf = buf,
402 };
403 struct spi_transfer xfer_buf = {
404 .len = len,
405 .rx_buf = data,
406 };
407
408 spi_message_init(&msg);
409 spi_message_add_tail(&xfer_head, &msg);
410 spi_message_add_tail(&xfer_buf, &msg);
411
412 adf7242_wait_spi_ready(lp, __LINE__);
413
414 mutex_lock(&lp->bmux);
415 if (packet_read) {
416 buf[0] = CMD_SPI_PKT_RD;
417 buf[1] = CMD_SPI_NOP;
418 buf[2] = 0; /* PHR */
419 } else {
420 buf[0] = CMD_SPI_PRAM_RD;
421 buf[1] = 0;
422 buf[2] = CMD_SPI_NOP;
423 }
424
425 status = spi_sync(lp->spi, &msg);
426
427 mutex_unlock(&lp->bmux);
428
429 return status;
430 }
431
adf7242_read_reg(struct adf7242_local * lp,u16 addr,u8 * data)432 static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data)
433 {
434 int status;
435 struct spi_message msg;
436
437 struct spi_transfer xfer = {
438 .len = 4,
439 .tx_buf = lp->buf_read_tx,
440 .rx_buf = lp->buf_read_rx,
441 };
442
443 adf7242_wait_spi_ready(lp, __LINE__);
444
445 mutex_lock(&lp->bmux);
446 lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr);
447 lp->buf_read_tx[1] = addr;
448 lp->buf_read_tx[2] = CMD_SPI_NOP;
449 lp->buf_read_tx[3] = CMD_SPI_NOP;
450
451 spi_message_init(&msg);
452 spi_message_add_tail(&xfer, &msg);
453
454 status = spi_sync(lp->spi, &msg);
455 if (msg.status)
456 status = msg.status;
457
458 if (!status)
459 *data = lp->buf_read_rx[3];
460
461 mutex_unlock(&lp->bmux);
462
463 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__,
464 addr, *data);
465
466 return status;
467 }
468
adf7242_write_reg(struct adf7242_local * lp,u16 addr,u8 data)469 static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data)
470 {
471 int status;
472
473 adf7242_wait_spi_ready(lp, __LINE__);
474
475 mutex_lock(&lp->bmux);
476 lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr);
477 lp->buf_reg_tx[1] = addr;
478 lp->buf_reg_tx[2] = data;
479 status = spi_write(lp->spi, lp->buf_reg_tx, 3);
480 mutex_unlock(&lp->bmux);
481
482 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n",
483 __func__, addr, data);
484
485 return status;
486 }
487
adf7242_cmd(struct adf7242_local * lp,unsigned int cmd)488 static int adf7242_cmd(struct adf7242_local *lp, unsigned int cmd)
489 {
490 int status;
491
492 dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd);
493
494 if (cmd != CMD_RC_PC_RESET_NO_WAIT)
495 adf7242_wait_rc_ready(lp, __LINE__);
496
497 mutex_lock(&lp->bmux);
498 lp->buf_cmd = cmd;
499 status = spi_write(lp->spi, &lp->buf_cmd, 1);
500 mutex_unlock(&lp->bmux);
501
502 return status;
503 }
504
adf7242_upload_firmware(struct adf7242_local * lp,u8 * data,u16 len)505 static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len)
506 {
507 struct spi_message msg;
508 struct spi_transfer xfer_buf = { };
509 int status, i, page = 0;
510 u8 *buf = lp->buf;
511
512 struct spi_transfer xfer_head = {
513 .len = 2,
514 .tx_buf = buf,
515 };
516
517 buf[0] = CMD_SPI_PRAM_WR;
518 buf[1] = 0;
519
520 spi_message_init(&msg);
521 spi_message_add_tail(&xfer_head, &msg);
522 spi_message_add_tail(&xfer_buf, &msg);
523
524 for (i = len; i >= 0; i -= PRAM_PAGESIZE) {
525 adf7242_write_reg(lp, REG_PRAMPG, page);
526
527 xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i;
528 xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE];
529
530 mutex_lock(&lp->bmux);
531 status = spi_sync(lp->spi, &msg);
532 mutex_unlock(&lp->bmux);
533 page++;
534 }
535
536 return status;
537 }
538
adf7242_verify_firmware(struct adf7242_local * lp,const u8 * data,size_t len)539 static int adf7242_verify_firmware(struct adf7242_local *lp,
540 const u8 *data, size_t len)
541 {
542 #ifdef DEBUG
543 int i, j;
544 unsigned int page;
545 u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL);
546
547 if (!buf)
548 return -ENOMEM;
549
550 for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) {
551 size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i;
552
553 adf7242_write_reg(lp, REG_PRAMPG, page);
554 adf7242_read_fbuf(lp, buf, nb, false);
555
556 for (j = 0; j < nb; j++) {
557 if (buf[j] != data[page * PRAM_PAGESIZE + j]) {
558 kfree(buf);
559 return -EIO;
560 }
561 }
562 }
563 kfree(buf);
564 #endif
565 return 0;
566 }
567
adf7242_clear_irqstat(struct adf7242_local * lp)568 static void adf7242_clear_irqstat(struct adf7242_local *lp)
569 {
570 adf7242_write_reg(lp, REG_IRQ1_SRC1, IRQ_CCA_COMPLETE | IRQ_SFD_RX |
571 IRQ_SFD_TX | IRQ_RX_PKT_RCVD | IRQ_TX_PKT_SENT |
572 IRQ_FRAME_VALID | IRQ_ADDRESS_VALID | IRQ_CSMA_CA);
573 }
574
adf7242_cmd_rx(struct adf7242_local * lp)575 static int adf7242_cmd_rx(struct adf7242_local *lp)
576 {
577 /* Wait until the ACK is sent */
578 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__);
579 adf7242_clear_irqstat(lp);
580 mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400));
581
582 return adf7242_cmd(lp, CMD_RC_RX);
583 }
584
adf7242_rx_cal_work(struct work_struct * work)585 static void adf7242_rx_cal_work(struct work_struct *work)
586 {
587 struct adf7242_local *lp =
588 container_of(work, struct adf7242_local, work.work);
589
590 /* Reissuing RC_RX every 400ms - to adjust for offset
591 * drift in receiver (datasheet page 61, OCL section)
592 */
593
594 if (!test_bit(FLAG_XMIT, &lp->flags)) {
595 adf7242_cmd(lp, CMD_RC_PHY_RDY);
596 adf7242_cmd_rx(lp);
597 }
598 }
599
adf7242_set_txpower(struct ieee802154_hw * hw,int mbm)600 static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm)
601 {
602 struct adf7242_local *lp = hw->priv;
603 u8 pwr, bias_ctrl, dbias, tmp;
604 int db = mbm / 100;
605
606 dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db);
607
608 if (db > 5 || db < -26)
609 return -EINVAL;
610
611 db = DIV_ROUND_CLOSEST(db + 29, 2);
612
613 if (db > 15) {
614 dbias = PA_DBIAS_HIGH_POWER;
615 bias_ctrl = PA_BIAS_HIGH_POWER;
616 } else {
617 dbias = PA_DBIAS_LOW_POWER;
618 bias_ctrl = PA_BIAS_LOW_POWER;
619 }
620
621 pwr = clamp_t(u8, db, 3, 15);
622
623 adf7242_read_reg(lp, REG_PA_CFG, &tmp);
624 tmp &= ~PA_BRIDGE_DBIAS(~0);
625 tmp |= PA_BRIDGE_DBIAS(dbias);
626 adf7242_write_reg(lp, REG_PA_CFG, tmp);
627
628 adf7242_read_reg(lp, REG_PA_BIAS, &tmp);
629 tmp &= ~PA_BIAS_CTRL(~0);
630 tmp |= PA_BIAS_CTRL(bias_ctrl);
631 adf7242_write_reg(lp, REG_PA_BIAS, tmp);
632
633 adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp);
634 tmp &= ~PA_PWR(~0);
635 tmp |= PA_PWR(pwr);
636
637 return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp);
638 }
639
adf7242_set_csma_params(struct ieee802154_hw * hw,u8 min_be,u8 max_be,u8 retries)640 static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be,
641 u8 max_be, u8 retries)
642 {
643 struct adf7242_local *lp = hw->priv;
644 int ret;
645
646 dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n",
647 __func__, min_be, max_be, retries);
648
649 if (min_be > max_be || max_be > 8 || retries > 5)
650 return -EINVAL;
651
652 ret = adf7242_write_reg(lp, REG_AUTO_TX1,
653 MAX_FRAME_RETRIES(lp->max_frame_retries) |
654 MAX_CCA_RETRIES(retries));
655 if (ret)
656 return ret;
657
658 lp->max_cca_retries = retries;
659 lp->max_be = max_be;
660 lp->min_be = min_be;
661
662 return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) |
663 CSMA_MIN_BE(min_be));
664 }
665
adf7242_set_frame_retries(struct ieee802154_hw * hw,s8 retries)666 static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
667 {
668 struct adf7242_local *lp = hw->priv;
669 int ret = 0;
670
671 dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries);
672
673 if (retries < -1 || retries > 15)
674 return -EINVAL;
675
676 if (retries >= 0)
677 ret = adf7242_write_reg(lp, REG_AUTO_TX1,
678 MAX_FRAME_RETRIES(retries) |
679 MAX_CCA_RETRIES(lp->max_cca_retries));
680
681 lp->max_frame_retries = retries;
682
683 return ret;
684 }
685
adf7242_ed(struct ieee802154_hw * hw,u8 * level)686 static int adf7242_ed(struct ieee802154_hw *hw, u8 *level)
687 {
688 struct adf7242_local *lp = hw->priv;
689
690 *level = lp->rssi;
691
692 dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n",
693 __func__, *level);
694
695 return 0;
696 }
697
adf7242_start(struct ieee802154_hw * hw)698 static int adf7242_start(struct ieee802154_hw *hw)
699 {
700 struct adf7242_local *lp = hw->priv;
701
702 adf7242_cmd(lp, CMD_RC_PHY_RDY);
703 adf7242_clear_irqstat(lp);
704 enable_irq(lp->spi->irq);
705 set_bit(FLAG_START, &lp->flags);
706
707 return adf7242_cmd_rx(lp);
708 }
709
adf7242_stop(struct ieee802154_hw * hw)710 static void adf7242_stop(struct ieee802154_hw *hw)
711 {
712 struct adf7242_local *lp = hw->priv;
713
714 disable_irq(lp->spi->irq);
715 cancel_delayed_work_sync(&lp->work);
716 adf7242_cmd(lp, CMD_RC_IDLE);
717 clear_bit(FLAG_START, &lp->flags);
718 adf7242_clear_irqstat(lp);
719 }
720
adf7242_channel(struct ieee802154_hw * hw,u8 page,u8 channel)721 static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
722 {
723 struct adf7242_local *lp = hw->priv;
724 unsigned long freq;
725
726 dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel);
727
728 might_sleep();
729
730 WARN_ON(page != 0);
731 WARN_ON(channel < 11);
732 WARN_ON(channel > 26);
733
734 freq = (2405 + 5 * (channel - 11)) * 100;
735 adf7242_cmd(lp, CMD_RC_PHY_RDY);
736
737 adf7242_write_reg(lp, REG_CH_FREQ0, freq);
738 adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8);
739 adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16);
740
741 if (test_bit(FLAG_START, &lp->flags))
742 return adf7242_cmd_rx(lp);
743 else
744 return adf7242_cmd(lp, CMD_RC_PHY_RDY);
745 }
746
adf7242_set_hw_addr_filt(struct ieee802154_hw * hw,struct ieee802154_hw_addr_filt * filt,unsigned long changed)747 static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw,
748 struct ieee802154_hw_addr_filt *filt,
749 unsigned long changed)
750 {
751 struct adf7242_local *lp = hw->priv;
752 u8 reg;
753
754 dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed);
755
756 might_sleep();
757
758 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
759 u8 addr[8], i;
760
761 memcpy(addr, &filt->ieee_addr, 8);
762
763 for (i = 0; i < 8; i++)
764 adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]);
765 }
766
767 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
768 u16 saddr = le16_to_cpu(filt->short_addr);
769
770 adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr);
771 adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8);
772 }
773
774 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
775 u16 pan_id = le16_to_cpu(filt->pan_id);
776
777 adf7242_write_reg(lp, REG_PAN_ID0, pan_id);
778 adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8);
779 }
780
781 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
782 adf7242_read_reg(lp, REG_AUTO_CFG, ®);
783 if (filt->pan_coord)
784 reg |= IS_PANCOORD;
785 else
786 reg &= ~IS_PANCOORD;
787 adf7242_write_reg(lp, REG_AUTO_CFG, reg);
788 }
789
790 return 0;
791 }
792
adf7242_set_promiscuous_mode(struct ieee802154_hw * hw,bool on)793 static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
794 {
795 struct adf7242_local *lp = hw->priv;
796
797 dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on);
798
799 lp->promiscuous = on;
800
801 if (on) {
802 adf7242_write_reg(lp, REG_AUTO_CFG, 0);
803 return adf7242_write_reg(lp, REG_FFILT_CFG,
804 ACCEPT_BEACON_FRAMES |
805 ACCEPT_DATA_FRAMES |
806 ACCEPT_MACCMD_FRAMES |
807 ACCEPT_ALL_ADDRESS |
808 ACCEPT_ACK_FRAMES |
809 ACCEPT_RESERVED_FRAMES);
810 } else {
811 adf7242_write_reg(lp, REG_FFILT_CFG,
812 ACCEPT_BEACON_FRAMES |
813 ACCEPT_DATA_FRAMES |
814 ACCEPT_MACCMD_FRAMES |
815 ACCEPT_RESERVED_FRAMES);
816
817 return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN);
818 }
819 }
820
adf7242_set_cca_ed_level(struct ieee802154_hw * hw,s32 mbm)821 static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
822 {
823 struct adf7242_local *lp = hw->priv;
824 s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX);
825
826 dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level);
827
828 return adf7242_write_reg(lp, REG_CCA1, level);
829 }
830
adf7242_xmit(struct ieee802154_hw * hw,struct sk_buff * skb)831 static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
832 {
833 struct adf7242_local *lp = hw->priv;
834 int ret;
835
836 /* ensure existing instances of the IRQ handler have completed */
837 disable_irq(lp->spi->irq);
838 set_bit(FLAG_XMIT, &lp->flags);
839 cancel_delayed_work_sync(&lp->work);
840 reinit_completion(&lp->tx_complete);
841 adf7242_cmd(lp, CMD_RC_PHY_RDY);
842 adf7242_clear_irqstat(lp);
843
844 ret = adf7242_write_fbuf(lp, skb->data, skb->len);
845 if (ret)
846 goto err;
847
848 ret = adf7242_cmd(lp, CMD_RC_CSMACA);
849 if (ret)
850 goto err;
851 enable_irq(lp->spi->irq);
852
853 ret = wait_for_completion_interruptible_timeout(&lp->tx_complete,
854 HZ / 10);
855 if (ret < 0)
856 goto err;
857 if (ret == 0) {
858 dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n");
859 ret = -ETIMEDOUT;
860 goto err;
861 }
862
863 if (lp->tx_stat != SUCCESS) {
864 dev_dbg(&lp->spi->dev,
865 "Error xmit: Retry count exceeded Status=0x%x\n",
866 lp->tx_stat);
867 ret = -ECOMM;
868 } else {
869 ret = 0;
870 }
871
872 err:
873 clear_bit(FLAG_XMIT, &lp->flags);
874 adf7242_cmd_rx(lp);
875
876 return ret;
877 }
878
adf7242_rx(struct adf7242_local * lp)879 static int adf7242_rx(struct adf7242_local *lp)
880 {
881 struct sk_buff *skb;
882 size_t len;
883 int ret;
884 u8 lqi, len_u8, *data;
885
886 adf7242_read_reg(lp, 0, &len_u8);
887
888 len = len_u8;
889
890 if (!ieee802154_is_valid_psdu_len(len)) {
891 dev_dbg(&lp->spi->dev,
892 "corrupted frame received len %d\n", (int)len);
893 len = IEEE802154_MTU;
894 }
895
896 skb = dev_alloc_skb(len);
897 if (!skb) {
898 adf7242_cmd_rx(lp);
899 return -ENOMEM;
900 }
901
902 data = skb_put(skb, len);
903 ret = adf7242_read_fbuf(lp, data, len, true);
904 if (ret < 0) {
905 kfree_skb(skb);
906 adf7242_cmd_rx(lp);
907 return ret;
908 }
909
910 lqi = data[len - 2];
911 lp->rssi = data[len - 1];
912
913 ret = adf7242_cmd_rx(lp);
914
915 skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */
916
917 ieee802154_rx_irqsafe(lp->hw, skb, lqi);
918
919 dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n",
920 __func__, ret, (int)len, (int)lqi, lp->rssi);
921
922 return ret;
923 }
924
925 static const struct ieee802154_ops adf7242_ops = {
926 .owner = THIS_MODULE,
927 .xmit_sync = adf7242_xmit,
928 .ed = adf7242_ed,
929 .set_channel = adf7242_channel,
930 .set_hw_addr_filt = adf7242_set_hw_addr_filt,
931 .start = adf7242_start,
932 .stop = adf7242_stop,
933 .set_csma_params = adf7242_set_csma_params,
934 .set_frame_retries = adf7242_set_frame_retries,
935 .set_txpower = adf7242_set_txpower,
936 .set_promiscuous_mode = adf7242_set_promiscuous_mode,
937 .set_cca_ed_level = adf7242_set_cca_ed_level,
938 };
939
adf7242_debug(struct adf7242_local * lp,u8 irq1)940 static void adf7242_debug(struct adf7242_local *lp, u8 irq1)
941 {
942 #ifdef DEBUG
943 u8 stat;
944
945 adf7242_status(lp, &stat);
946
947 dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n",
948 __func__, irq1,
949 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "",
950 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "",
951 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "",
952 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "",
953 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "",
954 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "",
955 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "",
956 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : "");
957
958 dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n",
959 __func__, stat,
960 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY",
961 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR",
962 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
963 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY",
964 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
965 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
966 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
967 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
968 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
969 #endif
970 }
971
adf7242_isr(int irq,void * data)972 static irqreturn_t adf7242_isr(int irq, void *data)
973 {
974 struct adf7242_local *lp = data;
975 unsigned int xmit;
976 u8 irq1;
977
978 mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400));
979 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1);
980
981 if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA)))
982 dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n",
983 __func__, irq1);
984
985 adf7242_debug(lp, irq1);
986
987 xmit = test_bit(FLAG_XMIT, &lp->flags);
988
989 if (xmit && (irq1 & IRQ_CSMA_CA)) {
990 adf7242_wait_status(lp, RC_STATUS_PHY_RDY,
991 RC_STATUS_MASK, __LINE__);
992
993 if (ADF7242_REPORT_CSMA_CA_STAT) {
994 u8 astat;
995
996 adf7242_read_reg(lp, REG_AUTO_STATUS, &astat);
997 astat &= AUTO_STATUS_MASK;
998
999 dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n",
1000 astat,
1001 astat == SUCCESS ? "SUCCESS" : "",
1002 astat ==
1003 SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "",
1004 astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "",
1005 astat == FAILURE_NOACK ? "FAILURE_NOACK" : "");
1006
1007 /* save CSMA-CA completion status */
1008 lp->tx_stat = astat;
1009 } else {
1010 lp->tx_stat = SUCCESS;
1011 }
1012 complete(&lp->tx_complete);
1013 adf7242_clear_irqstat(lp);
1014 } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) &&
1015 (irq1 & IRQ_FRAME_VALID)) {
1016 adf7242_rx(lp);
1017 } else if (!xmit && test_bit(FLAG_START, &lp->flags)) {
1018 /* Invalid packet received - drop it and restart */
1019 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n",
1020 __func__, __LINE__, irq1);
1021 adf7242_cmd(lp, CMD_RC_PHY_RDY);
1022 adf7242_cmd_rx(lp);
1023 } else {
1024 /* This can only be xmit without IRQ, likely a RX packet.
1025 * we get an TX IRQ shortly - do nothing or let the xmit
1026 * timeout handle this
1027 */
1028
1029 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n",
1030 __func__, __LINE__, irq1, xmit);
1031 adf7242_wait_status(lp, RC_STATUS_PHY_RDY,
1032 RC_STATUS_MASK, __LINE__);
1033 complete(&lp->tx_complete);
1034 adf7242_clear_irqstat(lp);
1035 }
1036
1037 return IRQ_HANDLED;
1038 }
1039
adf7242_soft_reset(struct adf7242_local * lp,int line)1040 static int adf7242_soft_reset(struct adf7242_local *lp, int line)
1041 {
1042 dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line);
1043
1044 if (test_bit(FLAG_START, &lp->flags))
1045 disable_irq_nosync(lp->spi->irq);
1046
1047 adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT);
1048 usleep_range(200, 250);
1049 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2));
1050 adf7242_cmd(lp, CMD_RC_PHY_RDY);
1051 adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous);
1052 adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be,
1053 lp->max_cca_retries);
1054 adf7242_clear_irqstat(lp);
1055
1056 if (test_bit(FLAG_START, &lp->flags)) {
1057 enable_irq(lp->spi->irq);
1058 return adf7242_cmd(lp, CMD_RC_RX);
1059 }
1060
1061 return 0;
1062 }
1063
adf7242_hw_init(struct adf7242_local * lp)1064 static int adf7242_hw_init(struct adf7242_local *lp)
1065 {
1066 int ret;
1067 const struct firmware *fw;
1068
1069 adf7242_cmd(lp, CMD_RC_RESET);
1070 adf7242_cmd(lp, CMD_RC_IDLE);
1071
1072 /* get ADF7242 addon firmware
1073 * build this driver as module
1074 * and place under /lib/firmware/adf7242_firmware.bin
1075 * or compile firmware into the kernel.
1076 */
1077 ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev);
1078 if (ret) {
1079 dev_err(&lp->spi->dev,
1080 "request_firmware() failed with %d\n", ret);
1081 return ret;
1082 }
1083
1084 ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size);
1085 if (ret) {
1086 dev_err(&lp->spi->dev,
1087 "upload firmware failed with %d\n", ret);
1088 release_firmware(fw);
1089 return ret;
1090 }
1091
1092 ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size);
1093 if (ret) {
1094 dev_err(&lp->spi->dev,
1095 "verify firmware failed with %d\n", ret);
1096 release_firmware(fw);
1097 return ret;
1098 }
1099
1100 adf7242_cmd(lp, CMD_RC_PC_RESET);
1101
1102 release_firmware(fw);
1103
1104 adf7242_write_reg(lp, REG_FFILT_CFG,
1105 ACCEPT_BEACON_FRAMES |
1106 ACCEPT_DATA_FRAMES |
1107 ACCEPT_MACCMD_FRAMES |
1108 ACCEPT_RESERVED_FRAMES);
1109
1110 adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN);
1111
1112 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2));
1113
1114 adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1);
1115 adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D);
1116
1117 adf7242_write_reg(lp, REG_IRQ1_EN0, 0);
1118 adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA);
1119
1120 adf7242_clear_irqstat(lp);
1121 adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF);
1122
1123 adf7242_cmd(lp, CMD_RC_IDLE);
1124
1125 return 0;
1126 }
1127
adf7242_stats_show(struct seq_file * file,void * offset)1128 static int adf7242_stats_show(struct seq_file *file, void *offset)
1129 {
1130 struct adf7242_local *lp = spi_get_drvdata(file->private);
1131 u8 stat, irq1;
1132
1133 adf7242_status(lp, &stat);
1134 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1);
1135
1136 seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1,
1137 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "",
1138 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "",
1139 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "",
1140 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "",
1141 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "",
1142 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "",
1143 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "",
1144 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : "");
1145
1146 seq_printf(file, "STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", stat,
1147 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY",
1148 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR",
1149 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
1150 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY",
1151 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
1152 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
1153 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
1154 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
1155 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
1156
1157 seq_printf(file, "RSSI = %d\n", lp->rssi);
1158
1159 return 0;
1160 }
1161
adf7242_debugfs_init(struct adf7242_local * lp)1162 static int adf7242_debugfs_init(struct adf7242_local *lp)
1163 {
1164 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-";
1165 struct dentry *stats;
1166
1167 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN);
1168
1169 lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1170 if (IS_ERR_OR_NULL(lp->debugfs_root))
1171 return PTR_ERR_OR_ZERO(lp->debugfs_root);
1172
1173 stats = debugfs_create_devm_seqfile(&lp->spi->dev, "status",
1174 lp->debugfs_root,
1175 adf7242_stats_show);
1176 return PTR_ERR_OR_ZERO(stats);
1177
1178 return 0;
1179 }
1180
1181 static const s32 adf7242_powers[] = {
1182 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
1183 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
1184 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
1185 };
1186
1187 static const s32 adf7242_ed_levels[] = {
1188 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
1189 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
1190 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
1191 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
1192 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
1193 -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000
1194 };
1195
adf7242_probe(struct spi_device * spi)1196 static int adf7242_probe(struct spi_device *spi)
1197 {
1198 struct ieee802154_hw *hw;
1199 struct adf7242_local *lp;
1200 int ret, irq_type;
1201
1202 if (!spi->irq) {
1203 dev_err(&spi->dev, "no IRQ specified\n");
1204 return -EINVAL;
1205 }
1206
1207 hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops);
1208 if (!hw)
1209 return -ENOMEM;
1210
1211 lp = hw->priv;
1212 lp->hw = hw;
1213 lp->spi = spi;
1214
1215 hw->priv = lp;
1216 hw->parent = &spi->dev;
1217 hw->extra_tx_headroom = 0;
1218
1219 /* We support only 2.4 Ghz */
1220 hw->phy->supported.channels[0] = 0x7FFF800;
1221
1222 hw->flags = IEEE802154_HW_OMIT_CKSUM |
1223 IEEE802154_HW_CSMA_PARAMS |
1224 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
1225 IEEE802154_HW_PROMISCUOUS;
1226
1227 hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
1228 WPAN_PHY_FLAG_CCA_ED_LEVEL |
1229 WPAN_PHY_FLAG_CCA_MODE;
1230
1231 hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY);
1232
1233 hw->phy->supported.cca_ed_levels = adf7242_ed_levels;
1234 hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels);
1235
1236 hw->phy->cca.mode = NL802154_CCA_ENERGY;
1237
1238 hw->phy->supported.tx_powers = adf7242_powers;
1239 hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers);
1240
1241 hw->phy->supported.min_minbe = 0;
1242 hw->phy->supported.max_minbe = 8;
1243
1244 hw->phy->supported.min_maxbe = 3;
1245 hw->phy->supported.max_maxbe = 8;
1246
1247 hw->phy->supported.min_frame_retries = 0;
1248 hw->phy->supported.max_frame_retries = 15;
1249
1250 hw->phy->supported.min_csma_backoffs = 0;
1251 hw->phy->supported.max_csma_backoffs = 5;
1252
1253 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1254
1255 mutex_init(&lp->bmux);
1256 init_completion(&lp->tx_complete);
1257
1258 /* Setup Status Message */
1259 lp->stat_xfer.len = 1;
1260 lp->stat_xfer.tx_buf = &lp->buf_stat_tx;
1261 lp->stat_xfer.rx_buf = &lp->buf_stat_rx;
1262 lp->buf_stat_tx = CMD_SPI_NOP;
1263
1264 spi_message_init(&lp->stat_msg);
1265 spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg);
1266
1267 spi_set_drvdata(spi, lp);
1268 INIT_DELAYED_WORK(&lp->work, adf7242_rx_cal_work);
1269 lp->wqueue = alloc_ordered_workqueue(dev_name(&spi->dev),
1270 WQ_MEM_RECLAIM);
1271
1272 ret = adf7242_hw_init(lp);
1273 if (ret)
1274 goto err_hw_init;
1275
1276 irq_type = irq_get_trigger_type(spi->irq);
1277 if (!irq_type)
1278 irq_type = IRQF_TRIGGER_HIGH;
1279
1280 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr,
1281 irq_type | IRQF_ONESHOT,
1282 dev_name(&spi->dev), lp);
1283 if (ret)
1284 goto err_hw_init;
1285
1286 disable_irq(spi->irq);
1287
1288 ret = ieee802154_register_hw(lp->hw);
1289 if (ret)
1290 goto err_hw_init;
1291
1292 dev_set_drvdata(&spi->dev, lp);
1293
1294 adf7242_debugfs_init(lp);
1295
1296 dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq);
1297
1298 return ret;
1299
1300 err_hw_init:
1301 mutex_destroy(&lp->bmux);
1302 ieee802154_free_hw(lp->hw);
1303
1304 return ret;
1305 }
1306
adf7242_remove(struct spi_device * spi)1307 static int adf7242_remove(struct spi_device *spi)
1308 {
1309 struct adf7242_local *lp = spi_get_drvdata(spi);
1310
1311 debugfs_remove_recursive(lp->debugfs_root);
1312
1313 cancel_delayed_work_sync(&lp->work);
1314 destroy_workqueue(lp->wqueue);
1315
1316 ieee802154_unregister_hw(lp->hw);
1317 mutex_destroy(&lp->bmux);
1318 ieee802154_free_hw(lp->hw);
1319
1320 return 0;
1321 }
1322
1323 static const struct of_device_id adf7242_of_match[] = {
1324 { .compatible = "adi,adf7242", },
1325 { .compatible = "adi,adf7241", },
1326 { },
1327 };
1328 MODULE_DEVICE_TABLE(of, adf7242_of_match);
1329
1330 static const struct spi_device_id adf7242_device_id[] = {
1331 { .name = "adf7242", },
1332 { .name = "adf7241", },
1333 { },
1334 };
1335 MODULE_DEVICE_TABLE(spi, adf7242_device_id);
1336
1337 static struct spi_driver adf7242_driver = {
1338 .id_table = adf7242_device_id,
1339 .driver = {
1340 .of_match_table = of_match_ptr(adf7242_of_match),
1341 .name = "adf7242",
1342 .owner = THIS_MODULE,
1343 },
1344 .probe = adf7242_probe,
1345 .remove = adf7242_remove,
1346 };
1347
1348 module_spi_driver(adf7242_driver);
1349
1350 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1351 MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver");
1352 MODULE_LICENSE("GPL");
1353
